Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal. The phase locked loop (PLL) includes a divider configured to divide the output clock signal to generate a divided clock signal, a time-pulse converter configured to generate a time-pulse conversion signal that has a pulse corresponding to a phase difference between the reference clock signal and the divided clock signal, and a digitally controlled oscillator including an LC resonance circuit for generating the output clock signal and configured to control a frequency of the output clock signal that is determined to correspond to a time constant of the LC resonance circuit according to the time-pulse conversion signal, wherein a sustainment time of changed capacitance is continuously controlled according to a change in the phase difference between the reference clock signal and the divided clock signal.

Abstract: A frequency synthesizer for dual-band high frequency RF application. The frequency synthesizer first uses a frequency-locked loop circuit (“FLL”) to achieve self-calibration and frequency-locking, and then uses a phase-locked loop circuit (“PLL”) to achieve phase-locking. During the FLL, the PLL is de-activated by control signals from the digital control and state machine of the FLL. The varactor of the VCO is initially connected to a fixed voltage, thus isolating the varactor from the PLL. The FLL adjusts the VCO's capacitor array by varying the five binary control bits from the state machine and digital control, until frequency-locking and self-calibration is achieved. Then, those five binary weighting control bits are also fixed for the VCO. The PLL is then activated to perform a fine-tuning and phase-locking loop, where the varactor of the VCO is controlled by the signal from the charge pump and the low-pass filter.

Abstract: DC components are removed by a first and a second capacitor from a normal signal and its inverted signal from a first and a second input terminal, and the signals are input to a DC level generating circuit. The DC level generating circuit newly adds a DC component to the respective signals from which the DC components are removed by the first and the second capacitors, and extracts only a DC voltage from a feedback voltage with a low-pass filter using the fist and the second capacitors. The circuit of the DC level generating circuit which includes the low-pass filter using the first and the second capacitors is configured so that a high-frequency cut-off frequency other than that included into a loop gain by the low-pass filter is not included. Consequently, only one high-frequency cut-off frequency exists in the loop gain, thereby preventing a feedback circuit from oscillating.