By Phase Patents (Class 327/2)
  • Patent number: 10651864
    Abstract: A receiver may include a time-interleaved charge sampler comprising a charge sampler switch in series with a charge sampler capacitor. The receiver may also include a current buffer configured to drive the time-interleaved charge sampler.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: May 12, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Timothy Donald Gathman, Yuhua Guo, Lai Kan Leung, Elias Dagher, Dinesh Jagannath Alladi
  • Patent number: 10477668
    Abstract: A method, system, and apparatus for vector control of radio frequency signals in narrow band devices such as Super-conducting Radio Frequency (SRF) cavities driven by injection locked magnetrons using carrier amplitude modulation by spectral energy spreading via phase modulation comprises coupling a magnetron to a cavity associated with a particle accelerator and injection locking the magnetron. A modulated amplitude and modulated phase of a drive signal is provided to the magnetron powering the cavity associated with the particle accelerator by removing power from a carrier according to a modulation scheme and providing vector control of the cavity radio frequency vector.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: November 12, 2019
    Assignee: Fermi Research Alliance, LLC
    Inventors: Brian E. Chase, Ralph J. Pasquinelli
  • Patent number: 10111173
    Abstract: An apparatus is provided which comprises: a mixer to mix a first signal of a first frequency with a second signal of a second frequency, and to generate a first output; a switched-capacitor multiplier, coupled to the mixer, to receive the first output and to provide a second output with reduced noise; and an amplifier, coupled to the switched-capacitor multiplier, to amplify the second output.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Erkan Alpman, Ahmad B. Khairi, Stefano Pellerano, Ashoke Ravi
  • Patent number: 9793884
    Abstract: Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a clock generator circuit configured to provide first and second clock signals responsive to an input dock signal. A duty phase interpolator circuit may be coupled to the dock generator circuit and configured to provide a first and second duty cycle corrected interpolated clock signals. A duty cycle adjuster circuit may be coupled to the duty phase interpolator circuit and configured to receive the first and second duty cycle corrected interpolated clock signals and provide a duty cycle corrected dock signal responsive thereto. A duty cycle detector may be coupled to the duty cycle adjuster circuit and configured to detect duty cycle error of the duty cycle corrected clock signal and provide the adjustment signals to correct the duty cycle error.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: October 17, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Yantao Ma
  • Patent number: 9721513
    Abstract: The invention provides a NAND gate latched driving circuit and a NAND gate latched shift register. The NAND gate latched driving circuit includes multiple cascade connected shift register circuits, each of the shift register circuits including a clock control transmission circuit and a NAND gate latch circuit. The clock control transmission circuit is triggered by a first clock pulse of a clock signal to transmit a driving pulse of a former stage to the NAND gate latch circuit, the driving pulse then is latched by the NAND gate latch circuit. The NAND gate latch circuit further is triggered by a subsequent second clock pulse of a first clock signal to output the latched driving pulse. By the above solution, the NAND gate latched driving circuit of the invention is suitable for CMOS process and can achieve low power consumption and wide noise tolerance.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: August 1, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Sikun Hao
  • Patent number: 9711108
    Abstract: Described is an apparatus that comprises: a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit operable to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulation (PFM) output.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: July 18, 2017
    Assignee: Intel Corporation
    Inventors: Fenardi Thenus, Peng Zou, Raghu Nandan Chepuri, Henry K. Koertzen
  • Patent number: 9678125
    Abstract: In accordance with an embodiment, a method of detecting a phase difference between a first signal and a second signal include latching a state of the first signal using the second signal as a clock to produce a first latched signal, latching a state of the second signal using the first signal as a clock to produce a second latched signal summing the first latched signal and the second latched signal to produce an indication of whether the first signal is leading or lagging the second signal.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: June 13, 2017
    Assignee: Infineon Technologies AG
    Inventor: Valentyn Solomko
  • Patent number: 9455725
    Abstract: A phase detector includes a plurality of sampling circuits, a logic circuit, a plurality of demultiplexers and a decision circuit, wherein the plurality of sampling circuits use a plurality of clock signals with different phases to sample a data signal respectively to generate a plurality of sampling results; the logic circuit generate N phase-leading signals and N phase-lagging signals according the plurality of sampling results; the plurality of demultiplexers perform demultiplex operations to the N phase-leading signals and the N phase-lagging signals respectively to generate M phase-leading output signals and M phase-lagging output signals respectively; and the decision circuit generates a final phase-leading signal and a final phase-lagging signal according the M phase-leading output signals and the M phase-lagging output signals.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: September 27, 2016
    Assignee: M31 Technology Corporation
    Inventors: Cheng-Liang Hung, Chun-Cheng Lin, Chih-Hsien Chang, Chao-Hsin Fan Jiang
  • Patent number: 9411893
    Abstract: Traffic management reports are created from data provided by vehicle sensor devices placed at different fixed locations in a region. Data of vehicles that pass each of the vehicle sensor devices are captured and communicated to a central computer database. At the central computer database, a traffic priority enforcement report is created from the vehicle data. The traffic priority enforcement report incorporates vehicle data from a plurality of vehicles. The vehicle data is for a plurality of previous, non-current times so as to allow for analysis of past vehicle data.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: August 9, 2016
    Assignee: Intuitive Control Systems, LLC
    Inventors: Christopher S. Johnson, Jason S. Geiger, John T. Graef
  • Patent number: 9331676
    Abstract: The present invention relates to a pulse signal generation circuit for changing a pulse width of an input pulse signal and outputting an output pulse signal having the changed pulse width. In an aspect, the pulse signal generation circuit may include a control signal generator configured to generate at least one control signal according to a pulse width of a input pulse signal and a pulse signal generator configured to control a pulse width of an input pulse signal in response to a control signal and to generate an output pulse signal with the controlled pulse width. The control signal controls the pulse width of the output pulse signal.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: May 3, 2016
    Assignee: SK Hynix Inc.
    Inventor: Jung-Hyun Kim
  • Patent number: 9305622
    Abstract: A method and apparatus for performing a data strobe-to-data delay calibration is disclosed. In one embodiment, a data strobe signal, along with data, is conveyed from a memory controller to a memory. An initial delay calibration procedure may be performed to align the data and the data strobe signals at the memory, with subsequent calibrations performed there between in order to compensate for changes due to various factors such as voltage and temperature. In the calibrations performed between the delay calibration procedures, a calibrated delay value may be multiplied by a first scaling factor and a second scaling factor to generate a scaled code. A DLL configured to convey the data strobe signal may then be programmed based on this code.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: April 5, 2016
    Assignee: Apple Inc.
    Inventor: Robert E. Jeter
  • Patent number: 9240848
    Abstract: An eye quality monitoring system may include an eye quality monitor that includes a charge pump that is configured to output (a) a first charge in a first direction upon detection of a first transition of a sampled non-return-to-zero (NRZ) data signal in a first region of a unit interval of an eye pattern, and (b) a second charge in a second direction upon detection of a second transition of the sampled NRZ data signal in a second region of the unit interval of the eye pattern. The first direction is opposite from the second direction. The eye quality monitor is configured to form an eye quality output that relates to a quality of the eye pattern based on the first and second charges.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: January 19, 2016
    Assignee: Tyco Electronics Corporation
    Inventor: Iain Ross Mactaggart
  • Patent number: 9077319
    Abstract: A clock phase shift detector circuit may include a phase detector that receives a first and a second clock signal, whereby the phase detector generates a phase signal based on a phase difference between the first and the second clock signal. A first integrator is coupled to the phase detector, receives the phase signal, and generates an integrated phase signal. A second integrator receives the first clock signal and generates an integrated first clock signal. A comparator is coupled to the first and the second integrator, whereby the comparator receives the integrated phase signal and the integrated first clock signal. The comparator may then generate a control signal that detects a change between the phase difference of the first and the second clock signal and an optimized phase difference based on an amplitude comparison between the integrated phase signal and the integrated first clock signal.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: July 7, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kai D. Feng, Jong-ru Guo, Trushil N. Shah, Ping-Chuan Wang, Zhijian Yang
  • Patent number: 9076551
    Abstract: A system includes a control circuit and first, second, and third ground-referenced single-ended signaling (GRS) driver circuits that are each coupled to an output signal. The control circuit is configured to generate a first, second, and third set of control signals that are each based on a respective phase of a clock signal. Each GRS driver circuit is configured to pre-charge a capacitor to store a charge based on the respective set of control signals during at least one phase of the clock signal and drive the output signal relative to a ground network by discharging the charge during a respective phase of the clock signal.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: July 7, 2015
    Assignee: NVIDIA Corporation
    Inventors: William J. Dally, John W. Poulton, Thomas Hastings Greer, III
  • Patent number: 9031182
    Abstract: A method for clock recovery and data recovery from a data stream on a communication channel includes sampling a data stream on the communication channel at a sampling frequency determined by a clock signal and generating a sampled signal. The method further includes determining a phase shift between the communication data stream and the sampled signal and modifying the phase of the clock signal on the basis of the phase shift to obtain a desired phase difference between the sampled signal and the data stream.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: May 12, 2015
    Assignee: Power-One Italy S.p.A.
    Inventors: Massimo Valiani, Davide Tazzari, Filippo Vernia
  • Patent number: 8988126
    Abstract: An apparatus for controlling a latency in a synchronous semiconductor device. The apparatus includes a first counting block for counting a cycle of a first clock signal to thereby generate a first binary code; a second counting block for counting a cycle of a second clock signal to thereby generate a second binary code. The second clock signal is obtained by delaying the first clock signal by a predetermined delay amount, A code comparison block stores the second binary code in response to a command and compares the first binary code with the second binary code to thereby generate a latency control signal.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: March 24, 2015
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Si-Hong Kim, Sang-Sic Yoon
  • Patent number: 8957704
    Abstract: A digital phase selector circuit that switches an output clock between N input clock phases is described. The phase selector utilizes a special output mux and switches clock phases during a safe zone to avoid glitches. The phase selector is used in the feedback path of a PLL to implement functions such as spread spectrum or fractional reference clocks. An example with N=4 and an optimized latch mux is shown.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: February 17, 2015
    Assignee: Synopsys, Inc.
    Inventors: Skye Wolfer, David A. Yokoyama-Martin
  • Patent number: 8952705
    Abstract: Systems and methods for transition delay measuring are presented. A transition delay measuring method can include oscillating a signal between states and tracking an indication associated with an isolated attribute of the transitions between the states. Oscillations can include asymmetric transitions between the states and the tracked isolated attribute can be a delay in completing transitions between the states in one direction or vice versa. The asymmetric transitions can include transitions between the first state and the second state that are faster than slower transitions between the second state and the first state or vice versa. The tracked indication can be utilized in analysis of the isolated transition delay characteristics. The results can be utilized in analysis of various further features and characteristics (e.g., examination of leakage current related power consumption, timing of asymmetric operation, etc.). The analysis can include examination of fabrication process and operating parameters.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: February 10, 2015
    Assignee: Nvidia Corporation
    Inventors: Ilyas Elkin, Wojciech Jakub Poppe
  • Patent number: 8917113
    Abstract: A phase detection device includes a clock divider configured to divide a clock signal and generate a plurality of divided clock signals, a recoverer configured to generate a recovered clock signal having substantially the same frequency as the clock signal based on the plurality of divided clock signals, and a phase detector configured to detect a phase of the recovered clock signal in response to a data strobe signal.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: December 23, 2014
    Assignee: SK Hynix Inc.
    Inventor: Keun Soo Song
  • Patent number: 8903747
    Abstract: A software optimization system isolates an effect of a change in a control variable from effects of ongoing, unknown changes in other variables. The system discards effects due to noise so that effects of interest to a programmer are more easily visible. The software optimization system treats variations in one or more control variables and in the output of the system as signals. The system varies the control variable at a specific frequency unlikely to correlate with uncontrolled variations in external variables. The system uses digital signal processing (DSP) techniques to filter the output, isolating the frequency of the control variable variation. The system then compares the resulting filtered output to the input to determine the approximate effect of the variation in the control variable.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: December 2, 2014
    Assignee: Microsoft Corporation
    Inventors: Eric L. Eilebrecht, Vance P. Morrison, Erika Fuentes
  • Patent number: 8896348
    Abstract: In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. An equalizing circuit precharges/equalizes the two sense nodes.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: November 25, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Koji Kuroki, Ryuji Takishita
  • Patent number: 8870454
    Abstract: During operation of the device, a drive circuit may provide a drive signal having a fundamental frequency to two electrothermal filters (ETFs) having different temperature-dependent time constants. In response to the drive signal, the two ETFs may provide signals having the fundamental frequency and phases relative to the drive signal corresponding, respectively, to the time constants of the ETFs. Then, phase-shift values of the phases may be measured using a phase detector, and a signal may be output based on the phase-shift values. Note that the signal may correspond to a value that is a function of a temperature of the device.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: October 28, 2014
    Assignee: Stichting voor de Technische Wetenschappen
    Inventors: Kofi A. A. Makinwa, Caspar P. L. Van Vroonhoven
  • Patent number: 8823416
    Abstract: A phase detector for a phase-locked loop includes a phase detector that is configured to become unstable, oscillate and drift rapidly in frequency in a predictable manner when a reference frequency signal is not available. When applied, for example, to a power converter connected to a power distribution grid, the predictable oscillatory and rapid frequency drift behavior when the phase detector is unstable allows very rapid and reliable detection of disconnection from the grid, referred to as islanding.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: September 2, 2014
    Assignee: Virginia Tech Intellectual Properties, Inc.
    Inventors: Timothy N. Thacker, Dushan Boroyevich, Fred Wang, Rolando Burgos
  • Patent number: 8803570
    Abstract: In a multiphase electrical power assignment, a processor: receives instructions to connect a bi-directional power device to a multiphase premise power source; determines that the power device is to be coupled to a target phase's phase connection; confirms that the power device is not coupled to any phase connections; and couples the power device to the phase connection, where the power device's power signal is synchronized with the phase connection's power signal. When the power device is in a connected state, the processor: issues a command to place each phase connection switch in an open state; in response to confirming that the phase connection switches are in the open state, issues commands to the power device so that a power signal of the power device will be synchronized with the target phase; and closes the phase connection switch corresponding to the target phase.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: August 12, 2014
    Assignee: STEM, Inc
    Inventors: Lynn Smith, Stacey Reineccius
  • Publication number: 20140167820
    Abstract: A phase detection range is enabled to be expanded to an arbitrary number of times of a cycle of a reference clock, and in the case of application to a DLL circuit, an operation cycle is enabled to be freely selected. A phase comparison device includes a divider that generates a division clock obtained by receiving a reference clock and dividing it by two; an inverter that inverts a phase of the division clock to generate a division inverted clock; a DFF circuit that synchronizes the division inverted clock with a delay clock to generate a synchronized clock; a DFF circuit that synchronizes the clock with the feedback clock to generate a final synchronized clock; and a phase comparator that receives the division clock and the final synchronized clock to compare phases of the division clock and the final synchronized clock.
    Type: Application
    Filed: July 17, 2012
    Publication date: June 19, 2014
    Applicant: MegaChips Corporation
    Inventor: Shoichiro Kashiwakura
  • Patent number: 8686797
    Abstract: There is provided a phase locked loop circuit which includes a frequency divider, a phase comparator, a filter, and an output signal oscillator. The frequency divides a feedback signal by a specific ratio and the feedback signal is used for synchronizing a phase of a reference signal and a phase of an output signal. The phase comparator compares the phases of the reference signal, the output signal, and the feedback signal and adjusts a gain of an analog signal used for generating the output signal in accordance with increase or decrease of the ratio. The filter filters the analog signal to pass signals in a specific frequency band, the gain of the analog signal having been adjusted by the phase comparator and the output signal oscillator outputs the output signal on the basis of the analog signal.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: April 1, 2014
    Assignee: Fujitsu Limited
    Inventor: Ken Atsumi
  • Patent number: 8648625
    Abstract: There is provided a frequency synthesizer capable of improving phase noise. A sinusoidal signal with a frequency set by a frequency setting part is output as a digital signal from a set signal output part, and the digital signal is D/A-converted. A difference between a sinusoidal signal with a frequency corresponding to an output frequency of a voltage controlled oscillating part and a sinusoidal signal output from a D/A converting part is amplified by a differential amplifier, and an amplified signal is input via an A/D converting part to a means for extracting a phase difference between the aforesaid sinusoidal signals. A voltage corresponding to a signal being the result of integration of the phase difference is input as a control voltage to the voltage controlled oscillating part. Then, a gain of the differential amplifier is set larger than a maximum value of phase noise degradation of the A/D converting part, whereby the phase noise degradation of the A/D converting part is cancelled.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: February 11, 2014
    Assignee: Nihon Dempa Kogyo Co., Ltd.
    Inventors: Kazuo Akaike, Nobuo Tsukamoto, Tsukasa Kobata
  • Patent number: 8604840
    Abstract: A method for reducing noise in a frequency synthesizer includes selecting a design variable k, calibrating a feedback time delay (Td), such that Td=kTVCO, where TVCO is the period of the synthesizer output signal. The method further includes estimating an instantaneous quantization error to a number of bits equal to q, defining a reference bias current of Icp/(k2q), where Icp is a charge pump current signal, and applying the estimated instantaneous quantization error to a current array to produce a down modification signal (?I). The current array is biased by the reference bias current. The down modification signal (?I) is summed with the charge pump current signal Icp to modulate a down current portion of the charge pump current signal Icp.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: December 10, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Mahmoud R. Ahmadi, Jafar Savoj
  • Patent number: 8604835
    Abstract: In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. Also provided an equalizing circuit precharging/equalizing the two sense nodes (FIG. 2).
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: December 10, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Koji Kuroki, Ryuji Takishita
  • Patent number: 8587345
    Abstract: A device for detecting non-phase-modulated pulsed signals includes at least one amplifier receiving a radiofrequency signal, and restoring at least one first signal representative of the envelope of the input signal, and a second normalized signal, characterized in that a module for estimating the stability of the phase includes means for estimating the phase of the radiofrequency signal, and means for evaluating the temporal stability of the phase, the presence of a characteristic pulse being detected if the phase is stable according to determined criteria.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: November 19, 2013
    Assignee: Thales
    Inventors: Emilie Boulanger, Frankie Letellier
  • Patent number: 8575967
    Abstract: This description relates to an edge detector including a pulse generator configured to generate a first pulse when a first clock and a second clock are at a same logic level and generate a second pulse when the first clock and the second clock are at different logic levels. The edge detector further includes a first RC circuit configured to charge the first pulse and a second RC circuit configured to charge the second pulse. The edge detector further includes a circuitry that, based on a width of the first pulse or of the second pulse, is configured to provide a select signal to select an edge of the second clock for triggering.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: November 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Chun Yang, Jinn-Yeh Chien
  • Publication number: 20130176056
    Abstract: An inverter delay compensation circuit includes a comparison determination unit including a first delay circuit configured for receiving a reference signal and having an inverter chain and a second delay circuit configured for receiving the reference signal and more insensitive to a PVT variation than the first delay circuit, and configured to compare delay amounts of signals obtained by passing the reference signal through the first and second delay circuits, respectively, and the comparison determination unit configured for generating a plurality of control signals; and a compensation circuit unit configured to compensate for a delay amount of an input signal in response to the plurality of control signals and configured to output an output signal.
    Type: Application
    Filed: September 1, 2012
    Publication date: July 11, 2013
    Applicant: Sk HYNIX INC.
    Inventors: Jong Sam KIM, Jin Hee Cho
  • Patent number: 8466713
    Abstract: Phase detection techniques in which an input signal is sampled to obtain several samples at different points in time with respect to a clock, said different points in time comprising an earliest point and latest point. The detection techniques further include generating a phase control signal obtained from the several samples of the input signal.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: June 18, 2013
    Inventors: Nebojsa Stojanovic, Theodor Kupfer, James Whiteaway, Jurgen Hauenschild, Soeren Gehrke
  • Patent number: 8432191
    Abstract: A phase-locked loop (PLL) includes PLL loop circuitry, a frequency divider, and a phase-frequency detector (PFD) that can produce both high-gain output signals to operate the PLL in a high-gain mode and normal output signals to operate the PLL in a normal (not high-gain) mode. A mode signal can be used to switch the PFD between high-gain mode and normal operational mode. When the mode signal indicates high-gain mode, the PFD output signals are extended by one or more additional clock cycles beyond their length when the mode signal indicates normal operational mode.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: April 30, 2013
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Robert Keith Barnes
  • Patent number: 8415983
    Abstract: A digital phase comparator is provided in which first phase difference signals and second phase difference signals are used as digital phase difference information. The first phase difference signals are generated by sampling a second clock signal with a first group of clock signals having regular intervals. The second phase difference signals are generated, using a second group of clock signals and a first group of signals which are obtained by delaying a second clock signal and a first signal generated by performing a logic operation on the first phase difference signal respectively at different regular intervals, by sampling the second group of clock signals with the first group of signals.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: April 9, 2013
    Assignee: NEC Corporation
    Inventor: Takashi Tokairin
  • Patent number: 8386244
    Abstract: The present invention provides a system and method for representing quasi-periodic (“qp”) waveforms comprising, representing a plurality of limited decompositions of the qp waveform, wherein each decomposition includes a first and second amplitude value and at least one time value. In some embodiments, each of the decompositions is phase adjusted such that the arithmetic sum of the plurality of limited decompositions reconstructs the qp waveform. These decompositions are stored into a data structure having a plurality of attributes. Optionally, these attributes are used to reconstruct the qp waveform, or patterns or features of the qp wave can be determined by using various pattern-recognition techniques. Some embodiments provide a system that uses software, embedded hardware or firmware to carry out the above-described method. Some embodiments use a computer-readable medium to store the data structure and/or instructions to execute the method.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: February 26, 2013
    Assignee: Digital Intelligence, L.L.C.
    Inventors: Carlos A. Ricci, Vladimir V. Kovtun
  • Patent number: 8368351
    Abstract: An apparatus and method for coupling a charging station to a power line segment that is terminated at a first end by a charging terminal are disclosed. The apparatus includes multiple taps coupled to the power line segment and circuitry coupled to the charging station and coupled to the multiple taps. The circuitry is configured to differentiate between communication signals propagating on the power line segment in the direction from the first end to a second end of the power line segment and communication signals propagating on the power line segment in the direction from the second end to the first end based at least in part on multiple measurements of respective phase shifts associated with different portions of a communication signal, each portion received over at least a first tap and a second tap.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: February 5, 2013
    Assignee: QUALCOMM Incorporated
    Inventor: James Zyren
  • Patent number: 8354862
    Abstract: A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: January 15, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chang Lin, Chan-Hong Chern, Steven Swei, Ming-Chieh Huang, Tien-Chun Yang
  • Patent number: 8354867
    Abstract: The present invention relates to a PLL circuit and an associated method that allows the PLL circuit to operate at a higher operating frequency with a wider bandwidth and a better out-band noise suppression. The PLL circuit comprises a delay locked loop (DLL), a phase-frequency detector (PFD), a loop filter, a voltage controlled oscillator (VCO) and a frequency divider.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: January 15, 2013
    Assignee: National Taiwan University
    Inventors: Shey-Shi Lu, Hsien-Ku Chen
  • Patent number: 8351558
    Abstract: The disclosure provides an effective means for fine-resolution determination of the frequency content of an RF signal using low speed digital circuits. The disclosure relates to a method and apparatus for decomposing a high frequency RF signal into several low frequency signals or data streams without loss of any information and without the use of extraneous circuit components such as local oscillators, mixers or offset phase-locked loops. Single or multiple phase oscillator outputs are fed directly to a single or multiple direct RF frequency-to-digital (DrfDC) circuits. The front end of the DrfDC circuit decomposes a high frequency signal into several low frequency signals without loss of any information. The low frequency signals are processed by the back-end of the DrfDC and converted into digital data streams. The digital data streams are then combined and averaged to represent the frequency of the input RF signal.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: January 8, 2013
    Assignee: Panasonic Corporation
    Inventors: Richard H. Strandberg, Paul Cheng-Po Liang
  • Patent number: 8254437
    Abstract: A transmitting apparatus, receiving apparatus and communication system are disclosed, and great improvement in an S/N ratio, preventing an actual throughput from decreasing, and preventing the number of circuits for synchronizing spread spectrum signals from increasing can be expected at the receiving apparatus side. The transmitting apparatus includes a pulse generating circuit, pulse repetition cycle determining circuit, peak power determining circuit, and modulator. The pulse generating circuit generates pulse strings, pulse repetition cycle determining circuit determines, based on a clock signal, a pulse repetition cycle of the pulse string generated by the pulse generating circuit. The peak power determining circuit determines a pulse peak power of the pulse string. The modulator modulates the pulse string with transmission data, and then generates a transmission signal.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: August 28, 2012
    Assignee: Panasonic Corporation
    Inventors: Suguru Fujita, Masahiro Mimura, Kazuaki Takahashi, Yoshinori Kunieda, Noriyuki Ueki
  • Patent number: 8248104
    Abstract: A phase comparator is provided that solves the problem that a VCO cannot be controlled with high precision. A frequency divider frequency-divides a VCO signal applied as input to an input terminal (10) in steps, and supplies the VCO signals of each step as output. A latch unit latches the VCO signal that is applied to the input terminal (10) and each VCO signal that was supplied from the frequency divider based on a reference signal that is applied to an input terminal (11). An output unit supplies the latch results realized by the latch unit as phase difference signals that indicate phase differences of the reference signal and the VCO signals.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: August 21, 2012
    Assignee: NEC Corporation
    Inventor: Tadashi Maeda
  • Patent number: 8217683
    Abstract: A basic symmetric ?/2 phase-detector receives four control signals that control a differential current at the detector's output. Each respective control signal is a linear combination of a respective pair of signals chosen from a first input signal, its logic complement, a second input signal and the logic complement of the latter. Operation is based on time-averaging the differential current, the result being zero at a phase difference of ?/2. By means of adding one or more additional current sources to the output, controlled by one or more of the control signals, the basic operation is skewed. The time-averaged output current is now made zero only at a value of the phase difference different from ?/2. In an embodiment with uniform current sources and resistors, the modified detector is configured for a phase difference of ?/2N .
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: July 10, 2012
    Assignee: NXP B.V.
    Inventor: Yann Le Guillou
  • Patent number: 8204166
    Abstract: An apparatus including a multiplexer configured to provide an output clock selected from a source clock, a destination clock, and a transition clock is provided. The apparatus further includes a phase difference calculation module configured to calculate a phase difference between the source clock and the destination clock and a clock generation module configured to generate a plurality of clocks. The apparatus further includes a clock selection module configured to select one of the plurality of clocks as the transition clock and a control circuit configured to provide: (1) a signal to the clock selection module for selecting one of the plurality of clocks as the transition clock based on the phase difference between the source clock and the destination clock and (2) a signal to the multiplexer to provide as the output clock one of the source clock, the destination clock, or the transition clock.
    Type: Grant
    Filed: October 8, 2007
    Date of Patent: June 19, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Srinivasa R. Bommareddy, Uday Padmanabhan, Samir J. Soni, Koichi E. Nomura, Nicholas F. Jungels, Vivek Bhan
  • Patent number: 8179163
    Abstract: Efficient techniques improve the linearity of a charge pump in fractional-N PLLs. A feedback clock pulse several VCO clock periods wide is formed and supplied to a phase frequency detector (PFD). The down pulse generated by the PFD is fixed to eliminate the nonlinearity associated with up and down current source mismatch. The up pulse is made to fall when the down pulse falls, that is, when the feedback clock pulse falls.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: May 15, 2012
    Assignee: Silicon Laboratories Inc.
    Inventor: Qicheng Yu
  • Publication number: 20120081152
    Abstract: The present disclosure provides a phase comparator including, a first latch, a second latch, a first detection circuit, a second detection circuit, and a charge-pump circuit having the function of a changeover switch.
    Type: Application
    Filed: August 26, 2011
    Publication date: April 5, 2012
    Applicant: Sony Corporation
    Inventors: Hidekazu Kikuchi, Hideo Morohashi
  • Publication number: 20120032705
    Abstract: A device for detecting non-phase-modulated pulsed signals or sequences of pulses of a determined frequency includes means for detecting tangling of pulses, at least one amplifier receiving a radiofrequency signal, and restoring at least one first signal representative of the envelope of the input signal, and a second normalized signal. A phase jump estimation module includes means for estimating the phase of the radiofrequency signal, means for evaluating a phase jump, the presence of pulse tangling being detected if the phase jump is of a greater value than a determined threshold value.
    Type: Application
    Filed: December 22, 2010
    Publication date: February 9, 2012
    Applicant: THALES
    Inventors: Emilie Boulanger, Frankie Letellier
  • Patent number: 8081013
    Abstract: A method for digital phase detection, comprises the steps of: providing a reference clock; receiving a feedback clock; determining a timing difference between the reference clock and the feedback clock; determining a polarity that indicates the leading or lagging relationship between the reference clock and the feedback clock; adaptively selecting one of at least two operating modes for generating a quantized level indicative of the timing difference, wherein in a first operating mode the quantized level is a constant maximum value and wherein in a second operating mode the quantized level is proportional to the timing difference; and generating a digital phase detection output as a combination of the polarity and the quantized level.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: December 20, 2011
    Assignee: Amlogic Co., Ltd.
    Inventors: Weicheng Zhang, Ming Shi, Wei-Hua Zou, Shu-Sun Yu, Chieh-Yuan Chao
  • Publication number: 20110267108
    Abstract: A first counter detects a rising edge of a clock signal, and generates a first signal having a multiplied cycle of the clock signal. A second counter detects a falling edge of the clock signal, and generates a second signal having a multiplied cycle of the clock signal. A first line transfers the first signal, while a second line transfers the second signal. A phase comparator is connected to the first line and the second line to generate a third signal based on a phase difference between the first signal and the second signal and output the third signal to one of the circuit units. A plurality of the phase comparators are connected to the first line and the second line, and are disposed between one of the ends of the first line and the second line and one of the circuit units.
    Type: Application
    Filed: July 19, 2011
    Publication date: November 3, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Mariko IIZUKA
  • Patent number: 8013636
    Abstract: A phase detection circuit determines phase difference between a periodic signal and a reference signal of substantially equal frequency. The circuit includes: a source input receiving the periodic signal; a feedback signal generator providing a feedback signal (PFB) with substantially the same frequency as the reference signal; a phase difference circuit coupled to the source input node and a second signal input node coupled to the feedback signal generator, determining an error signal from phase difference between the periodic signal and PFB; an integrator circuit integrating the error signal into an integration signal; and a digitizing circuit digitizing the integration signal. The feedback signal generator is coupled to the digitizing circuit, providing PFB based on the digitized integration signal, and selecting the phase of PFB from a number of fixed phases. The phase detection circuit generates a time-average of the phase of PFB selected from the plurality of fixed phases.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: September 6, 2011
    Assignee: Stichting voor de Technische Wetenschappen
    Inventors: Kofi Afolabi Anthony Makinwa, Caspar Petrus Laurentius van Vroonhoven