Abstract: An electronic device including a phase detector is provided. The phase detector includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first equalizer device. The first transistor has a first input terminal configured to receive a first signal. The second transistor has a second input terminal configured to receive a second signal. The third transistor is electrically connected to the first transistor and has a first output terminal. The fourth transistor is electrically connected to the second transistor and has a second output terminal. The first equalizer device is connected between the first output terminal and the second input terminal.

Abstract: A circuit includes a voltage-controlled oscillator (VCO) and a frequency divider. The frequency divider input is coupled to the VCO output. The circuit further includes a phase-frequency detector (PFD). A control output of the PFD is coupled to the VCO. A first PFD input is coupled to a first frequency divider output, and a second PFD input is coupled to a second frequency divider output. The first frequency divider output is configured to provide a first frequency divider signal and the second frequency divider output is configured to provide a second frequency divider signal 90 degrees out of phase with respect to the first frequency divider signal. The PFD is configured to detect an occurrence of at least two edges of a signal on the data input while the second frequency divider signal is continuously logic high across the at least two edges.

Abstract: Generator of physically unclonable cryptographic keys (PUF) has two adjustable speed ring oscillators (GPRS, GPRS?), which outputs (o-GPRS, o-GPRS?) are connected to inputs (i1-DF, i2-DF) of a phase detector (DF), which output (o-DF) is connected to control inputs of the adjustable speed ring oscillators (s-GPRS, s-GPRS?) through a control system (US) and is also connected to a output (o-PUF) of the generator of physically unclonable cryptographic keys (PUF) through a sample and compare circuit (URP). Generator has a initializing input (i-UCH) connected to both initializing inputs of the adjustable speed ring oscillators (i-GPRS, GPRS?) and to the first input of the sample and compare circuit (i-URP), which second input (z-URP) is connected to the output (o-GPRS?) of one of adjustable speed ring oscillators (GPRS?).

Abstract: A circuit includes a voltage-controlled oscillator (VCO) and a frequency divider. The frequency divider input is coupled to the VCO output. The circuit further includes a phase-frequency detector (PFD). A control output of the PFD is coupled to the VCO. A first PFD input is coupled to a first frequency divider output, and a second PFD input is coupled to a second frequency divider output. The first frequency divider output is configured to provide a first frequency divider signal and the second frequency divider output is configured to provide a second frequency divider signal 90 degrees out of phase with respect to the first frequency divider signal. The PFD is configured to detect an occurrence of at least two edges of a signal on the data input while the second frequency divider signal is continuously logic high across the at least two edges.

Abstract: A waveform synthesizer comprises a controllable oscillator for generating an oscillator waveform having an oscillator cycle; a reference input for accepting a reference signal having a reference cycle; and a waveform detector coupled to said oscillator and said reference input. The waveform detector is arranged to sample said waveform in response to said reference input and to determine waveform information about said oscillator. The waveform information is operative to adjust said controllable oscillator.

Abstract: It was found that certain VCO devices used in microwave frequency synthesizers exhibit prolonged ringing oscillation during extreme voltage jumps above a critical limit, but that this effect could be significantly reduced by splitting the voltage adjustment over multiple steps. This finding was used to improve the switching speed of such devices (e.g. wideband VCO with a computer processor, base frequency generator VCO and a frequency divider). Here, before implementing a command to switch frequencies (by changing the base frequency oscillator and frequency divider settings), the processor first determines if this change will require an extreme voltage jump likely to cause such oscillations. If so, the processor implements this voltage jump as a multiple step process, resulting in a significant reduction in the maximum time required to switch frequencies.

Abstract: This document describes various techniques for implementing low-energy GPS on a mobile device. A GPS module is activated, a sub-millisecond pseudo-range estimate is received from the GPS module, the GPS module is deactivated, the sub-millisecond pseudo-range estimate and a time stamp are transmitted to a remote entity, and location information based on the sub-millisecond pseudo-range estimate and time stamp is received from the remote entity.

Abstract: A method for serial data transmission between a position-measuring device and subsequent electronics over a bidirectional data channel includes transmitting data in data frames and in encoded form in accordance with a data transmission code. The data transmission in each case is initiated by an interface unit at a transmitter end with a start sequence having an encoding scheme that at least partially differs from an encoding scheme of a remainder of the data frames. After a reversal of data direction, an interface unit at a receiver end detects a beginning of the data transmission in each case by detection of the start sequence.

Abstract: Embodiments of a circuit are described. In this circuit, a modulation circuit provides a first modulated electrical signal and a second modulated electrical signal, where a given modulated electrical signal, which can be either the first modulated electrical signal or the second modulated electrical signal, includes minimum-shift keying (MSK) modulated data. Moreover, a first phase-adjustment element, which is coupled to the modulation circuit, sets a relative phase between the first modulated electrical signal and the second modulated electrical signal based on a phase value of the first phase-adjustment element. Additionally, an output interface, which is coupled to the first phase-adjustment element, is coupled to one or more antenna elements which output signals. These signals include a quadrature phase-shift-keying (QPSK) signal corresponding to the first modulated electrical signal and the second modulated electrical signal.

Abstract: A phase detector includes a phase comparing circuit configured to detect and output a phase difference between a first clock signal and a second clock signal, a latch circuit configured to latch an output signal of the phase comparing circuit and output a phase detection signal, and an initial voltage control circuit configured to control an initial voltage of an input terminal of the latch circuit according to a control signal.

Abstract: In accordance with an embodiment, a method of detecting a phase difference between a first signal and a second signal include latching a state of the first signal using the second signal as a clock to produce a first latched signal, latching a state of the second signal using the first signal as a clock to produce a second latched signal summing the first latched signal and the second latched signal to produce an indication of whether the first signal is leading or lagging the second signal.

Abstract: An alternative phase detector without the need for direct phase measurement is provided. The phase detector comprises three signal inputs (S1, S2, S3), a ratio determination circuit (RDC) for determining at least two ratios of the respective input signals, and a calculation circuit (CC) to derive a measure of a phase difference between at least two input signals.

Abstract: In accordance with an embodiment, a method of detecting a phase difference between a first signal and a second signal include latching a state of the first signal using the second signal as a clock to produce a first latched signal, latching a state of the second signal using the first signal as a clock to produce a second latched signal summing the first latched signal and the second latched signal to produce an indication of whether the first signal is leading or lagging the second signal.

Abstract: An apparatus and a method for detecting phase deficiency in an inverter is provided, the method including deciding whether a sector of the output current is a sector where current detection is possible based on switching operation status of the switching element in the inverter, maintaining a phase deficiency variable when deciding the current detection in the sector of the output current to be impossible, adding a count to a phase deficiency variable to accumulate when deciding the current detection in the sector of the output current to be possible and deciding the output current to be within a phase deficiency band, and determining as phase deficiency when the phase deficiency variable is greater than a prescribed detection level.

Abstract: A phase detection device includes a clock divider configured to divide a clock signal and generate a plurality of divided clock signals, a recoverer configured to generate a recovered clock signal having substantially the same frequency as the clock signal based on the plurality of divided clock signals, and a phase detector configured to detect a phase of the recovered clock signal in response to a data strobe signal.

Abstract: The present invention relates to a phase frequency detector (PFD) (100) for use as one of the blocks in a phase-locked loop. The PFD of the present invention has zero dead zone, has a simpler structure with a minimum number of transistors and requires a smaller area. The PFD of the present invention does not use any inverter or delay gate as found in the conventional PFD. Instead, the PFD of the present invention utilizes feedback transistors that save power and thus the PFD of the present invention is suitable to be used in low power applications.

Abstract: A method for reducing noise in a frequency synthesizer includes selecting a design variable k, calibrating a feedback time delay (Td), such that Td=kTVCO, where TVCO is the period of the synthesizer output signal. The method further includes estimating an instantaneous quantization error to a number of bits equal to q, defining a reference bias current of Icp/(k2q), where Icp is a charge pump current signal, and applying the estimated instantaneous quantization error to a current array to produce a down modification signal (?I). The current array is biased by the reference bias current. The down modification signal (?I) is summed with the charge pump current signal Icp to modulate a down current portion of the charge pump current signal Icp.

Abstract: A generator device with a generator regulator and a generator unit having a generator and a rectifier arrangement. The generator regulator has an operating voltage connection and a phase voltage connection. Furthermore, if during a control intervention of the phase voltage the DC voltage applied to the operating voltage connection exceeds a predefined limit for a predefined period of time, the generator regulator deactivates the control intervention of the phase voltage.

Abstract: A digital phase comparator is provided in which first phase difference signals and second phase difference signals are used as digital phase difference information. The first phase difference signals are generated by sampling a second clock signal with a first group of clock signals having regular intervals. The second phase difference signals are generated, using a second group of clock signals and a first group of signals which are obtained by delaying a second clock signal and a first signal generated by performing a logic operation on the first phase difference signal respectively at different regular intervals, by sampling the second group of clock signals with the first group of signals.

Abstract: An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal.

Abstract: A method for signal phase calibration includes providing multiple periodic clock signals, including a reference signal and multiple phase shifted versions of the reference signal. The signals have a common frequency and are shifted from one another by multiples of a phase offset. An edge of a first signal is detected. The first signal is one of multiple phase shifted versions of the reference signal. The edge is a transition from a first logic value to a second logic value. The second logic value of the first signal is compared, upon detection of the edge, to a logic value of a second signal that is one of the first plurality of periodic clock signals other than the first signal. An inversion of the first signal is selectively provided based on an outcome of the comparison.

Abstract: A method and a system for measuring amplitude and phase difference between two sinusoidal signals, using an adaptive filter. The method generally comprises measuring a sample of an output signal of a system excited by a sample of a reference signal; using an adaptive filter and the sample of the reference signal to determine a and b coefficients that minimize a prediction error on the sample of the output signal, iteratively, and determining the amplitude and/or phase of the output of the system using the a and b coefficients.

Abstract: The present invention relates to a PLL circuit and an associated method that allows the PLL circuit to operate at a higher operating frequency with a wider bandwidth and a better out-band noise suppression. The PLL circuit comprises a delay locked loop (DLL), a phase-frequency detector (PFD), a loop filter, a voltage controlled oscillator (VCO) and a frequency divider.

Abstract: There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.

Abstract: A phase comparator is provided that solves the problem that a VCO cannot be controlled with high precision. A frequency divider frequency-divides a VCO signal applied as input to an input terminal (10) in steps, and supplies the VCO signals of each step as output. A latch unit latches the VCO signal that is applied to the input terminal (10) and each VCO signal that was supplied from the frequency divider based on a reference signal that is applied to an input terminal (11). An output unit supplies the latch results realized by the latch unit as phase difference signals that indicate phase differences of the reference signal and the VCO signals.

Abstract: Efficient techniques improve the linearity of a charge pump in fractional-N PLLs. A feedback clock pulse several VCO clock periods wide is formed and supplied to a phase frequency detector (PFD). The down pulse generated by the PFD is fixed to eliminate the nonlinearity associated with up and down current source mismatch. The up pulse is made to fall when the down pulse falls, that is, when the feedback clock pulse falls.

Abstract: A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal.

Abstract: A phase detecting circuit includes a latch circuit that switches, based on an OR signal and an AND signal of two clock signals to be subjected to phase comparison, one of outputs used for generation of two pulse signals on an advance phase side and a delay phase side to a preparation operation state for performing the phase comparison and a circuit operation state after the phase comparison, and holds the output in the states.

Abstract: A method for digital phase detection, comprises the steps of: providing a reference clock; receiving a feedback clock; determining a timing difference between the reference clock and the feedback clock; determining a polarity that indicates the leading or lagging relationship between the reference clock and the feedback clock; adaptively selecting one of at least two operating modes for generating a quantized level indicative of the timing difference, wherein in a first operating mode the quantized level is a constant maximum value and wherein in a second operating mode the quantized level is proportional to the timing difference; and generating a digital phase detection output as a combination of the polarity and the quantized level.

Abstract: A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal includes a first counter for outputting a first counter value indicative of a number of clock cycles of the reference signal, and a second counter for outputting a second counter value indicative of a number of clock cycles of the feedback signal. An asynchronous comparator receives the first and second counter values and provides an output signal having a pulse width that is proportional to the difference between the first and second counter values. A pulse width detector receives the comparator output signal and produces an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value. A state machine controls the state of at least one lock indication signal according to the pulse width detector output signal.

Abstract: A pulse width (PW) digitizer comprises a current pump, a capacitor, a quantizer, a feedback controller, and a digital filter. The current pump provides a current signal in response to a PW signal. The capacitor obtains a voltage signal in response to the current signal. The quantizer obtains a digital signal in response to the voltage signal. The feedback controller determines a feedback PW signal in response to the digital signal. The feedback PW signal is fed back to the current pump for controlling the current signal converging to a specific value and controlling the digital signal switching between a first code and a second code. The digital filter counts times that the digital signal indicating the first code/the second code and accordingly obtains the PW of the PW signal.

Abstract: A digital phase-locked loop and a digital phase-frequency detector thereof are provided. The digital PFD includes a divisor switch unit, a low-resolution phase-error detecting unit, an accumulating unit, a high-resolution phase-error detecting unit, a constant unit, and a selector. The divisor switch unit receives and removes partial pulses of a feedback signal for obtaining a feedback clock. The low-resolution phase-error detecting unit detects phase error between a reference signal and the feedback clock to obtain a phase-error pulse width. The accumulating unit accumulates the feedback signal during the phase-error pulse width for obtaining an output selection signal. The high-resolution phase-error detecting unit detects phase error between the reference signal and the feedback signal to obtain a phase-error value. The constant unit provides at least one constant value. The selector selects and outputs one of the phase-error value and the constant value according to the output selection signal.

Abstract: A phase detection circuit determines phase difference between a periodic signal and a reference signal of substantially equal frequency. The circuit includes: a source input receiving the periodic signal; a feedback signal generator providing a feedback signal (PFB) with substantially the same frequency as the reference signal; a phase difference circuit coupled to the source input node and a second signal input node coupled to the feedback signal generator, determining an error signal from phase difference between the periodic signal and PFB; an integrator circuit integrating the error signal into an integration signal; and a digitizing circuit digitizing the integration signal. The feedback signal generator is coupled to the digitizing circuit, providing PFB based on the digitized integration signal, and selecting the phase of PFB from a number of fixed phases. The phase detection circuit generates a time-average of the phase of PFB selected from the plurality of fixed phases.

Abstract: Provided is an apparatus comprising a delaying section that generates a plurality of delayed signals by delaying a single first input signal by different delay amounts; a first acquiring section that acquires each of a plurality of input second input signals at a first phase of a reference clock; a second acquiring section that acquires each of the plurality of second input signals at a second phase of the reference clock, which is different from the first phase; and a change point detecting section that detects a change point of one of the first input signal and a second input signal, based on values of the plurality of signals acquired by the first acquiring section and values of the plurality of signals acquired by the second acquiring section.

Abstract: Disclosed is a phase-frequency comparator stabilizing a loop band width by a simple circuit, there is provided a phase-frequency comparator which is a phase-frequency comparator of inputting a reference clock and a feedback clock and outputting an up signal to a frequency synthesizer and a down signal to the frequency synthesizer, which is provided with a first phase-frequency comparing circuit, a second phase comparing circuit, and a delay circuit portion inputting the reference clock and the feedback clock and providing a predetermined relative delay to an input of the first phase-frequency comparing circuit and an input of the second phase comparing circuit, in which frequency comparison is carried out by the first phase-frequency comparing circuit, and phase comparison is carried out by the first phase-frequency comparing circuit and the second phase comparing circuit controlling a latch.

Abstract: A circuit, with applications to phase-locked loops and frequency synthesis, where a divider circuit shuffles between dividing the output of a voltage-controlled oscillator by N or N+1, where N is an integer, and where a phase frequency detector provides three logic signals to a charge pump so that one of three values of current may be sourced to a loop filter, with the result that the circuit behaves as a conventional phase-locked loop having a fictitious divider circuit that is capable of dividing the output of the voltage-controlled oscillator by a non-integral value.

Abstract: A device for determining an interference with a regulated voltage provided by a control loop with a unit for monitoring a control variable of the control loop and a unit for generating a notification signal if the control variable or a change in the time of the control variable is beyond a tolerance range around a normal value.

Abstract: Apparatus and methods detect missing clock edges. An improved phase frequency detector (PFD) can be used in, for example, a phase locked loop (PLL) or a delay locked loop (DLL). Conventional PFDs can miss clock edges. Disclosed is a missing clock edge detection circuit that reliably detects these missing clock edges to correctly activate switches of a charge pump of the PLL or DLL. Embodiments exhibit relatively little of the characteristic polarity reversal of conventional PLL or DLL circuits, which then enables embodiments to operate faster and acquire phase lock quicker than conventional circuits. Such techniques are useful in clock synthesis, clock recovery, and the like. The invention can further include an optional circuit that detects when the missing clock edge detection circuit may have inaccurately determined (false positive) that a clock edge had been missed, to override the corrective action by the missing clock edge detection circuit.

Abstract: A control indication assembly. A first control mounted on a surface of a computer is coupled to a first sensor, to a first sensing circuit to send an electrical signal to the first control when a user-touch occurs to the first sensor, and to a first indicator to indicate an occurrence of said user-touch. A second control mounted on a surface of a display which is coupled to the computer is coupled to a second sensor, to a second sensing circuit to send an electrical signal to said second control when said user-touch occurs to the display, and to a second indicator to indicate an occurrence of the user-touch. The first and second control are configured such that the first and second indicator are synchronized to exhibit identical behaviors when the user-touch occurs to either the first control or the second control.

Abstract: Methods, devices, modules, and systems for a band-gap reference voltage detection circuit are provided. One embodiment for a band-gap reference voltage detection circuit includes a Brokaw cell having a band-gap reference voltage, and a circuit portion for indicating the magnitude of an input voltage signal with respect to the band-gap reference voltage. The input voltage is applied to transistor bases of the Brokaw cell.

Abstract: A method for calculating coordinate values of a measuring machine is provided. The method includes receiving signals in three dimensions from a raster ruler signal generator, identifying a direction of each signal and multiply a frequency of each signal. The method further includes counting each of multiplied signals in each dimension, sending the counted data to the MCU. The method further includes adding the counted data of each of the multiplied signals in each dimension to obtain an accumulated number in each dimension and calculating coordinate values of the measuring machine according to the accumulated number in each dimension and a proportionality factor of the raster ruler signal generator.

Abstract: A phase detection circuit arranged as sigma-delta modulator for determining a phase difference between a periodic signal and a reference signal, the periodic signal and the reference signal having a substantially equal frequency, includes: a source input configured to receive the periodic signal whose phase relationship with respect to the reference signal is to be determined; a feedback signal generator configured to provide a feedback signal, the feedback signal and reference signal having substantially the same frequency; a phase difference circuit coupled to the source input node and a second signal input node coupled to the feedback signal generator, and configured to determine an error signal as a function of the phase difference between the periodic signal and the feedback signal; an integrator circuit coupled to the phase difference circuit, configured to receive the error signal and to integrate the error signal to provide an integration signal; a digitizing circuit coupled to the integration circuit

Abstract: A phase-locked loop frequency synthesizer including phase detector circuitry and divider circuitry producing a divided signal. The phase detector circuitry receives a reference signal, a divided signal fed back from the divider circuitry, and generates control pulses which control a charge pump in accordance with a frequency and phase relationship between the reference signal and the divided signal. The divider circuitry has a main divider which divides an input signal by a division ratio selected from a pair of dual modules division ratios, and outputs the divided input signal as an output signal and an auxiliary divider which produces serial output data, each bit of which serves as a dual modules selection signal to cause the main divider to operate using one of the pair of dual modules main division ratios. The auxiliary divider produces the divided signal once per cycle and outputs the pulse to the phase detector circuitry.

Abstract: Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal. A multiplexer may also be provided for receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. Some embodiments may include a power saving mode.

Abstract: An embodiment of the present invention provides a system for detecting a phase-shifted signal at high frequencies in data and clock recovery circuitry. An up-pulse generator, in one embodiment, provides output pulses having a duration exceeding the duration of input pulses upon detection of a phase-shifted signal leading the reference signal. A down-pulse generator provides output pulses having a duration exceeding the duration of input pulses upon detection of a phase-shifted signal lagging the reference signal.

Abstract: A phase comparator includes an edge detecting unit to which a reference signal is input and to which a referred signal based on the reference signal is input as a feedback signal. The edge detecting unit detects an edge of the reference signal and an edge of the referred signal. The phase comparator also includes a phase-difference detecting unit that detects a phase difference between the edge of the reference signal and the edge of the referred signal. The phase comparator also includes a phase-difference-signal output unit that outputs a phase-difference signal for current control based on the phase difference. The phase comparator also includes an input-break detecting unit that detects an input break of the reference signal when an edge of the referred signal is again detected after an edge of the referred signal is detected and before an edge of the reference signal is detected.

Abstract: Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.

Abstract: A phase detector includes transistors that generate first and second phase error signals. The phase detector resets the first phase error signal in response to at least one of the first and the second phase error signals through a first reset path having a maximum reset delay that is equal to or less than a sum of switching delays of three transistors in the first reset path. The phase detector resets the second phase error signal in response to at least one of the first and the second phase error signals through a second reset path having a maximum reset delay that is equal to or less than a sum of switching delays of three transistors in the second reset path.

Abstract: An apparatus and method for detecting a phase difference between an input signal and a reference signal in an all-digital phase locked loop (PLL) are provided. In a preferred embodiment, an N-stage tapped delay line and N-bit parallel latch are used to create a snapshot of the input signal by latching the output of the tapped delay line using the reference signal to clock the latch. An edge detector and encoder circuit translate the latched snapshot into a numerical phase difference value. A difference between this phase difference value and a desired phase difference is calculated and then added to an accumulator. The result in the accumulator is a numerical phase error value that can be fed to a numerically controlled oscillator (NCO). The output of the NCO can, in turn, be fed back into the phase/frequency comparator as the input signal, thus forming a fully-digital PLL.

Abstract: A semiconductor, which includes a first phase detecting unit configured to detect a phase of a second clock on the basis of a phase of a first clock, and generate a first detection signal corresponding to a result of the detection, a second phase detecting unit configured to detect a phase of a delayed clock, which is generated by delaying the second clock by a predetermined time, on the basis of the phase of the first clock, and generate a second detection signal corresponding to a result of the detection, and a logic level determining unit configured to determine a logic level of a feedback output signal according to the first detection signal, the second detection signal and the feedback output signal.