Abstract: A write current driving circuit in which drains of the transistors A1 and B1 are commonly connected to the base of the transistor T1, drains of the transistors C1 and D1 are commonly connected to the base of the transistor T2, inverted signal of the input signal into the transistors C1 and D1 is inputted into the transistors A1 and B1. Therefore, the transistors T1 and T2 can speedily be switched ON/OFF with suppressed power consumption. Transistors A2, C2 and transistors B2, D2 are connected in parallel with the transistors A1, C1 and NMOS transistors B1, D1 respectively, and the transistors A2, C2, B2, and D2 are turned ON only for a specified period of time immediately after the transistors T1 and T2 are switched ON/OFF.

Abstract: A current detection circuit having a voltage conversion section for converting current flowing to a load to a voltage; an amplifier section having an operational amplifier for amplifying the voltage converted by the voltage conversion section; a constant current circuit section having a constant current circuit connected to an input of the operational amplifier; and a current detection section for detecting a load current from a voltage amplified by the amplifier section. The constant current circuit section shifts the input offset voltage to the operational amplifier of the amplifier section. As a result, a dead zone in which a load current cannot be detected due to the input offset voltage of the operational amplifier can be eliminated.

Abstract: A circuit and method to drive an H-bridge circuit are disclosed. The H-bridge circuit uses NMOS transistors for both the upper and lower sets of transistors. An inductive head is coupled between the terminals of the transistors. When a logic signal is received, one of the upper transistors is driven. The upper transistor selected to be driven is responsive to the logic signal. A corresponding lower transistor is also driven, forcing current through the inductive head in a first direction. The driving circuit for the lower transistors includes a programmable circuit structured to capacitively couple the output of the driving circuit to a pull-up voltage, thereby allowing the amount of current forced through the inductive head to be maximized for optimum data transfer. Within the programmable voltage boost circuit are several logic gates, each coupled to a capacitor of differing value.

Abstract: The microstructure includes an electronic circuit formed by a plurality of transistors (6) and a flat coil formed by a conductive wire or a conductive path (14). The coil (10) is arranged on an upper face (8) of the semiconductor substrate (4). The coil (10) generates a magnetic field (B) in this substrate (4) in the vicinity of the transistors (6) which are situated in superposition with said coil (10). The source (20) and the collector (22) of the sensitive transistors (6) are aligned along a direction perpendicular to the wire or path (14) in the portion of the coil situated in proximity to each of said transistors (6). Thus, the electric current (I) flowing in the transistors (6) is substantially parallel to the magnetic field (B).

Abstract: An H-driver circuit is provided that has a mechanism for selectively reducing one or more RC time constants within the H-driver circuit. Selectively reducing one or more RC time constants within the H-driver circuit reduces the turn-ON time of one or more of the H-driver circuit's pull-up transistors, and increases the speed of the H-driver circuit with little increase in power consumption. Each RC time constant preferably is selectively reduced via a feedback path between an output terminal of the H-driver circuit and a resistance reducer operatively coupled to the pull-up transistor whose turn-ON time is to be reduced. Preferably the resistance reducer comprises a transistor, more preferably a MOSFET and most preferably a p-channel MOSFET.

Abstract: A circuit configuration for pulsed current regulation of inductive loads includes a freewheeling configuration which is connected in parallel with the inductive load and has a current-measuring device in order to measure current exclusively while a switching device is in an open state. This avoids an otherwise customary shunt resistor and associated power loss.

Abstract: A high voltage tolerant CMOS input/output interface circuit. In this circuit, a process feature called “dual-gate” or “thick-oxide” process is used on any devices that will be exposed to high voltage. The thick-oxide devices have a larger capacitance and lower bandwidth, and therefore, preferably, they are only used where exposure to high voltage can cause damage. The remaining devices on the interface circuit may all use a standard process with the thinner oxide, allowing the I/O and the core IC to run at maximum speed. The circuit design topology also limits the number of devices that are exposed to high voltage. Preferably, the protection scheme is broken down into two parts: the driver and receiver.

Abstract: A magnetic recording control circuit for controlling current through a magnetic recording head includes a switch network, a signal coupler, and first and second voltage clamps. The switch network is connected to first and second magnetic recording head node regions and includes first, second, third, and fourth switches each having a variable magnitude conduction path and a control region. The signal coupler includes an input region and a plurality of output regions each connected to the control region of a corresponding switch. The first and second voltage clamps limit voltage differences between the magnetic recording head node regions and the control regions of the first and second switches.

Abstract: A hard disk drive write channel architecture improves the rise-time while utilizing a same supply voltage to provide a boosted voltage, thereby improving the rise-time only when it is needed. The voltage is then connected to the inductive write head through a switch after an appropriate delay, so as to compensate for the delay between the switching of Data line and the peaking of the voltage at the corresponding write terminal. In addition, the same delayed version of the Data line is applied to the inputs of the switching circuit to delay the signal inputs such that the delay timing matches appropriately.

Abstract: An electronic power conversion circuit includes cryogenically cooled MOSFET power switching devices arranged in a switch-mode configuration and responsive to control signals for reducing capacitive discharge and commutation losses in the circuit by controlling the period between switch-on and switch-off time (i.e., “deadtime”) of the MOSFET devices. When one of the MOSFET devices of the circuit is switched off, the opposing MOSFET, after the short deadtime period, is switched on to serve as a commutating device rather, than the opposing MOSFET's intrinsic drain-source diode. The power conversion circuit may include a half-bridge circuit or combinations thereof.

Abstract: For current control of an inductive load (4), preferably an electromagnetic pressure regulator, a process is proposed in which an actual current value is detected synchronously and with a delay in relation to the output signal of a current regulator (2). Hereby is prevented the detection of transients superimposed on the actual current value.

Abstract: An integrated full bridge circuit includes four transistors divided into two series-connected pairs of transistors each forming a half bridge circuit. Resistor elements each connect a respective one of the pairs of transistors to a reference potential. Other resistor elements are each connected to a respective one of two separate supply terminals inside a housing. Each of the other resistor elements is connected to one of the transistors of a respective one of the pairs of transistors at a junction. Driver transistors each have a load path with two connections and a type complementary to the transistors connected to the other resistor elements. One of the connections is connected upstream of the control terminal of a respective one of the transistors connected to the other resistor elements. The other of the connections in each of the half bridge circuits is connected to the junction in the other of the half bridge circuits. The advantage is power loss reduction.

Abstract: Circuit arrangement for switching an inductive load, for example in clocked voltage regulators, includes a switching transistor which is operated in a high-side circuit and is connected to a free-running transistor in a half-bridge arrangement, with the inductive load to be switched positioned in a node between the switching transistor and the free-running transistor. The circuit arrangement also includes a driving circuit for the switching transistor. The switching transistor is connected to an auxiliary transistor in a current balancing arrangement, and the current balancing mode of the transistors can be controlled as a function of a potential present in the node.

Abstract: A bridge circuit uses active feedback to control drive phase turn on to substantially eliminate shoot-through current. Voltage sensor 66 senses H-bridge transistor voltage turn off levels and causes control circuit 64 to latch which causes enable circuit 62 to allow the next phase of H-bridge transistor turn on. A critical aspect of the invention is to ensure all H-bridge transistors are off before the enable circuit allows the next phase to turn any H-bridge transistors on.

Abstract: An overshoot and damping control circuit for high speed L-R-C drivers. By properly configuring four transistors in conjunction with a high speed driver, negative feedback can be utilized to generate a spike of current to correct for overshoot which results when driving an inductive load with high speed signals. This same configuration also provides the additional benefit of providing a signal which dampens the ringing which results from driving an inductive load with a high speed signal.

Abstract: A motor control circuit controls operation of a motor for making or breaking one or more pairs of contacts of a power switching device such as a circuit breaker. The motor control circuit includes a logic circuit responsive to a control input signal and an enable signal for producing an active signal state when both the control signal and the enable signal are present, and for producing an inactive logic signal state when either of the control signal and the enable signal is not present. A switching control signal producing circuit is responsive to said active state of the logic signal for producing a switching control signal for operating the motor for a predetermined time interval sufficient to perform one of opening and closing of the one or more pairs of contacts.

Abstract: A controller for controlling the voltage slew-rate of an inductive load connected to the drain of a field effect transistor is disclosed. The controller includes a current generator electrically connected between the gate and the drain of the field effect transistor, the current generator providing a current at the gate of the field effect transistor to offset a feed back current at the gate of the transistor due to gate-drain capacitance of the transistor. The current generator includes capacitor means having one end electrically connected to the drain of the field effect transistor, a current multiplier electrically connected between another end of the capacitor means and the gate of the field effect transistor, and a current source electrically connected to the gate of the field effect transistor. The current multiplier includes at least one current mirror, and the current source includes a constant current source.

Abstract: A simulation circuit has a simulation circuit path that simulates operation of the write current circuit path of a write current driver. A simulation transistor simulates operation of the driver transistor and a monitor circuit monitors current at the base of the simulation transistor to derive a compensation current based on variations in base current, including breakdown of the simulation transistor. The compensation current is combined with the driver current to derive the write driver current for the driver transistor of the write current driver. In another form, the simulation circuit path is a scaled-down electrical equivalency of the write current circuit path so that the simulation current is a scaled fraction of the write current and power requirements are reduced. In one form, current is added to the compensation current to accommodate unidirectional nature of current mirrors in the monitor circuit.

Abstract: A device for switching inductive loads includes a series circuit which is connected between positive and negative poles of voltage source and has a load and a switch associated with the load. A free-running diode is connected parallel to the load. A guard circuit for guarding against mispolarization of the voltage source has an electronic switch connected in series with the free-running diode. The electronic switch is made conducting through a charge pump triggered by an oscillator, given correct polarization of the voltage source.

Abstract: An H-bridge circuit having a boost capacitor coupled to the gate of the low-side driver. A driver, in the form of a switching transistor is connected between the load and ground, thus providing a low-side driver. A capacitor is coupled to the gate of the low-side driver to provide a boosted voltage for rapid turn on of the gate. The size of the capacitor selected to be similar to the size of the capacitance associated with the low-side driver transistor.

Abstract: A write driver for an inductive load includes load terminals for connection to an inductive load, and a driver circuit responsive to first and second control signals to supply a drive current through the load in respective first and second directions. A voltage-mode H-bridge connected to the load terminals is operable to selectively supply a voltage across the load terminals and head. Program means operates the voltage-mode H-bridge for a predetermined time period following initiation of the respective first and second control signal to provide a voltage across the load terminals which quickly raises the write current to a steady state condition. Ringing is suppressed by employing an impedance-matched H-bridge for the driver circuit, the impedance-matched H-bridge having an impedance matched to the impedance of a transmission line connecting the load to the terminals.

Abstract: A drive circuit for a high-speed integrated circuit, bipolar switching regulator is disclosed. The circuit runs at megahertz frequencies, yet is efficient as previously available bipolar integrated circuit switching regulators operating at much lower frequencies. The circuitry provides three switch drive currents: a first (nominal) current that is provided while the switch is off in order to conserve power; a second (boosted) current, provided while the switch is transitioning from off to on in order to increase the speed at which the switching element switches on; and a third (drive) current, provided after the switch has turned on for maintaining the switch at a desired point in saturation. The drive current, additionally, varies as a function of the load on the switch in order, again, to conserve power. Additional circuitry increases the speed at which the switch turns off, by momentarily boosting base discharge current during the on-to-off transition period of the switch.

Abstract: Methods and apparatus for operating first and second switches arranged in a half-bridge configuration are described. First and second gate voltages on the first and second gates, respectively, of the first and second switches are controlled such that the first switch is on and the second switch is off. One of the first and second gate voltages is controlled such that the corresponding one of the first and second switches operates as a constant current source. After one of the first and second switches has been operating as a constant current source, the second gate voltage is controlled such that the second switch is on and the first gate voltage is controlled such that the first switch is off.

Abstract: A method and apparatus for changing the open-loop frequency response of an amplifier in a line driver when the load to the line driver is removed. The load is detected by measuring the current to the load. When the current falls below a predetermined amount, the load is assumed to be disconnected and the open-loop frequency response of the amplifier is changed to shift a dominant pole of the line driver to a sufficiently low frequency to ensure stability of the line driver.

Abstract: The ignition coil driver module of the present invention includes a control integrated circuit, formed of a low voltage semiconductor material, and a high current load driver integrated circuit, formed of a high voltage integrated circuit, housed within a common package. The high current load driver integrated circuit is responsive to a low voltage drive signal provided by the control integrated circuit to permit a load current to flow unrestricted through the load driver integrated circuit and an inductive load connected thereto. The control integrated circuit includes a sense resistor which receives the load current from the high current load driver integrated circuit, converts this current to a sense voltage, compares the sense voltage to a reference voltage generated within the control integrated circuit, and forces the low voltage drive signal to drop to a level which will limit the load current to a predetermined current value.

Abstract: A driver for producing a desired pulse width modulated current through a load is provided with a sequencer for generating a plurality of wave forms phase-shifted so as to have non-overlapping duty cycles. A target generator supplies a target current value to a comparator, which compares the target current value to a signal representative of a sensed current flowing through the load. A driver control is responsive to a duty-cycle of only one of the plurality of wave forms to selectively generate trigger signals for switching current through the load in response to the result of the comparison.

Abstract: In combination with a transistor designed to drive an inductive load, there is included a network connected between the output electrode (e.g., drain) and the control electrode (e.g., gate) of the transistor for limiting the overshoot and controlling the waveshape of the signal produced at the output electrode of the transistor, when the transistor is being turned-off. The network includes a series string of zener diodes with one or more by-pass capacitors connected across the zener diodes closest to the control electrode of the transistor for shaping the output signal produced at the output electrode of the transistor and for reducing electromagnetic radiation. The network also includes unidirectional conducting elements for discharging each bypass capacitor each time the transistor is turned-on. The zener diodes and the "discharging" unidirectional conducting elements of the network may be formed as integral parts of the same integrated circuit (IC).

Abstract: A trailing edge of a control signal of a transistor controller for controlling an output transistor is detected by an edge detector of a clamp controlling circuit. A surge voltage from a back electromotive voltage induced in an inductance L1 is absorbed from the output transistor, only for a given period immediately after the solenoid is turned off, by turning a switching transistor into an on-state by a timer to force a clamping circuit into conduction. At a normal operation, since the clamping circuit is cut off from an output terminal, the clamping voltage can be set in a manner to reduce to a normal voltage in an IGN-line. Therefore, a peak power value of a power loss caused by the surge voltage at the output transistor can be reduced, whereby generation of heat at the output transistor can be reduced. Therefore, the chip size of the power IC can be reduced.

Abstract: In an address electrode drive circuit of a plasma display panel, clamping diodes which yield a small forward voltage drop and have a fast switching speed are connected between the output terminal of the drive circuit and the power source and between the output terminal of the drive circuit and the ground. A backward current and voltage dashing from the load to the output transistors of the drive circuit are initially bypassed and absorbed with the clamping diodes and subsequently bypassed and absorbed with parasitic diodes of the output transistors, and the drive circuit is protected against the incoming surge current and voltage.

Abstract: A method and apparatus, for applying a current to a coil of a write head assembly of a disk drive, or the like, to cause the flux within the coil to rapidly reverse, has an H-bridge having two pair of two switchable transistors. Each pair of the transistors is connected between a supply voltage and a reference potential, and is adapted to be connected to the coil between the two transistors of each pair. The two transistors of the first pair may be connected to receive a control signal to turn on complementary transistors of the first and second pair of transistors to selectively control current flow in the coil in first or second directions. A reference current source supplies a reference current, and one of the transistors in each of the first and second pairs of transistors is connected when turned on to mirror the reference current to control the currents in the coil.

Abstract: An ignition system has several charging circuits connected to a common input circuit and controlled by a common triggering unit to fire respective igniters. The input circuit has a voltage source connected across a first capacitor, which provides the output terminals of the source. Each charging circuit has a second capacitor connected in series with one end of an inductance. A tapping of the inductance is connected to an input of the charging circuit via a diode and a thyristor, controlled by the triggering unit. The output of the charging circuit is provided by one electrode of the second capacitor and the opposite end of the inductance.

Abstract: A device for triggering an electromagnetic load. The load is formed by at least two partial inductances. The load can be connected to the ground via a first switching device, and a partial inductance can be connected to the ground via a second switching device. The first switching device is triggered as a function of a voltage measured between the partial inductance and the second switching device.

Abstract: A transient suppressor comprises a self-triggered silicon control rectifier (SCR) that forms a drive circuit for an NPN power transistor. The SCR and the NPN power transistor are combined, along with other elements, into an integrated circuit (IC) by a junction isolated BiCMOS process. The SCR self-triggers upon being subjected to an inductive flyback condition created by an inductive load and renders the NPN transistor conductive, thereby allowing the NPN power transistor, having a relatively large semiconductor region, to effectively snub the current created by the negative feedback condition. The transient suppressor may be used in either a high-side or low-side driver arrangement and the SCR/NPN power transistor combination may further be combined with load driving and other circuitry on a single integrated circuit.

Abstract: A method of controlling switching of a tri-state switching amplifier having two switching legs, two switches in each leg, and a load connected to the junction between the switches of each leg, a power supply and a capacitor connected to the opposite ends of each leg, a first pair of the switches defining an idle state in which current circulates through the load and the first pair of switches, a second pair of the switches defining a Charge state in which the load is connected to the power supply and current through the load increases and a third pair of switches defining a Discharge state in which the load is connected to the power supply and current through the load decreases, the method comprising generating a first PWM signal at the beginning of each pulse of a clock signal; generating a second PWM signal when a binary current error signal changes state; generating, at the beginning of each pulse of the clock signal, a Direction signal which is the inverse of the current error signal; and placing the ampl

Abstract: A control circuit controls the power supply to an electric motor and, comprises a power transistor NM of the NMOS type and a power transistor PM of the PMOS type arranged between two supply terminals VCC and GND, their intermediate node forming an output coupled to a coil Ei of the motor. The well B of the transistor PM is coupled to supply terminal VCC via an isolation diode ID, which has its anode connected to supply terminal VCC and has its cathode connected to the well B. The isolation diode ID ensures that the coil Ei is not short-circuited by the parasitic drain-well diode D of the transistor PM in case of a sudden power failure.

Abstract: A capacitive load drive is provided, which can perform faster and more efficient operation than an energy recovery circuit for effectively reducing ineffective energy of pulses applied to a capacitive load. An energy recovery circuit is connected to a first electrode of the capacitive load, to which pulses are applied. The energy recovery circuit comprises a coil and a capacitor connected in series for energy recovery, and a first and a second voltage clamp switches connected to the other terminal of the series circuit of the coil and the capacitor, the first voltage clamp switch being connected to a high voltage side terminal of the DC power supply, the second voltage clamp switch being connected to a low voltage side terminal of the DC power supply.

Abstract: A circuit is provided to switch a drive transistor in a write driver circuit controlled by a write control signal to direct write current in a selected direction through an inductive head. Current is selectively conducted from a control region of the drive transistor in response to switching of the write control signal. A first bias circuit limits voltage fluctuation at the control region of the drive transistor. A second bias circuit prevents saturation of the drive transistor.

Abstract: A write driver, having a pair of head nodes for connection to a write head, includes two diodes connected respectively the head nodes and the emitters of first and second upper drive transistors. The diodes, which are preferably Schottky diodes, increase the voltage necessary to breakdown the emitter pn junctions of the upper drive transistors, thereby enabling a greater head swing voltage, higher switching rates, and ultimately closer spacing of data on a magnetic medium. Additionally, a preferred embodiment of the write driver includes two voltage clamps, each coupled between a respective head node and a first supply node, to limit the magnitude of voltage spikes resulting from self-inductance of the write head.

Abstract: A method and a device for driving a load, particularly an electromagnetic load. The current flowing through the load is detected, and is controlled by a control device connected in series to the load. During a first phase, in addition to the control device, a first switching device is driven that is disposed parallel to the control device. During a third phase, in addition to the control device, a second switching device is driven that is disposed parallel to the control device.

Abstract: In a circuit, switch (1) switches a current from a reference voltage terminal through an inductive element (3). The energy stored in the magnetic field associated with the inductive element when a current is flowing is transferred on interruption of the current either capacitively or inductively to an energy storage element (4). The stored energy is then returned to re-energize the inductive element (3) when the current flow is restored by the switch (1).

Abstract: A current detecting resistor is inserted in an H-bridge circuit constructed to cause the flow of a current to an inductive load in both forward and reverse directions by four semiconductor switching elements and flywheel diodes respectively connected in reverse parallel to the semiconductor switching elements. An inductive load driving method and an H-bridge circuit control device prevent an erroneous operation caused by noise generated at the current detecting resistor. When a current flowing through the inductive load is controlled by a detection voltage generated by the current detecting resistor, the value of the detection voltage is ignored immediately after the connection of the inductive load to a power source. There is no risk that an erroneous operation is caused by a rush current and/or a through current.

Abstract: A switching device with a power FET for switching an inductive load to which a free-wheeling diode is connected in parallel, wherein the terminal of the series resistor facing away from the gate terminal is connected to a driver circuit which is so designed that it connects the specified terminal with a reverse potential in order to block the FET, wherein, at the beginning of the process of making the FET conductive, it connects the specified terminal with a high resistance to a control voltage source that puts the FET into the conductive state, in such a way that the current rise of the current flowing through the FET is slowed down to such an extent that, within a period of time in which the free-wheeling diode is not yet blocking after starting to make the FET conductive, an increase of the current to undesirable high values is prevented, so that damage to the power FET and the free-wheeling diode and/or other circuit elements and/or the occurrence of electromagnetic disturbances is reduced, and wherein, a

Abstract: An inductive load driving apparatus for controlling current supplied from a battery to an inductor such as a generator field coil is composed of a first N-channel MOSFET switching element connected between a high-side terminal of the inductor and a high-side terminal of the battery, a second N-channel MOSFET switching element connected in parallel with the inductive load and a protection circuit having a back-flow current detecting element turning off the second N-channel MOSFET switching element when the inductor does not generate back-flow current. The second N-channel MOSFET switching element is turned on when the first N-channel MOSFET switching element is turned off and turned off when the first switching element is turned on. The first and second N-channel MOSFET switching elements are disposed integrally with each other on a semiconductor chip.

Abstract: A network is connected between the drain and gate of a transistor for limiting the overshoot and controlling the waveshape of the signal produced at the drain of the transistor, when the transistor is being turned-off. The network includes a series string of zener diodes with one or more by-pass capacitors connected across one or more zener diodes for shaping the output signal produced at the drain of the transistor and for reducing electromagnetic radiation. The network also includes unidirectional conducting elements for discharging each bypass capacitor each time the transistor is turned-on. The zener diodes and the "discharging" unidirectional conducting elements of the network may be formed as integral parts of the same integrated circuit (IC). For best results, the bypass capacitors are connected across the zener diodes closest to the gate of the transistor.

Abstract: There is disclosed a multi-power supply integrated circuit including a first pMOS transistor which is formed in a first n-well and operated at a first supply voltage and a second pMOS transistor which is formed in a second n-well and operated at a second supply voltage being lower than the first supply voltage, wherein the first n-well and the second n-well are placed adjacently to put a boundary line therebetween and also the first supply voltage is supplied to both the first and second n-wells. Because a space between the first and second n-wells is made small, a gate array LSI with a reduced chip area is provided. A common n-well may be formed in place of the first and second n-wells.

Abstract: A low-noise output buffer in accordance with the present invention includes pre-driver circuitry coupled to core circuitry of an integrated circuit, output circuitry having a variable drive level that is responsive to the pre-driver output signal and powered by a first power supply, and noise reduction control circuitry coupled to the first power supply. The noise reduction control circuitry is powered by a second power supply which has less noise than the first power supply, and is arranged to develop a control signal that is coupled to the output circuitry to modify the drive level of the output circuitry to counteract noise detected on the first power supply. In some embodiments, the noise reduction control circuitry includes a first transistor and the output circuitry includes a second transistor which are arranged to form a stacked transistor pair.

Abstract: A circuit for the controlled recycle without oscillation of a discharge current from an inductive load. The circuit comprises an active element connected, in series with the inductive load, between first and second power supply terminals, and having a control terminal to which a driver circuit is connected. The circuit further includes a recycling regulating circuitry connected to a connection node between the active element and the inductive load, and sensitive to a voltage threshold at the connection node to generate, depending on attainment of that threshold, a power-on signal for application to the control terminal effective to start up recycling of the discharge current through the active element. The circuit further comprises a control circuit for controlling the voltage oscillation at the connection node at the end of the recycling.

Abstract: A high-side MOSFET gate protection shunt circuit is provided for protecting an output driving transistor (10). The output driving transistor (10) is operable to drive a load (18) on an output node (12). A sense resistor (26) is disposed between the supply voltage terminal and the output node (12). The gate of transistor (10) is driven by a current limited driver (20). In order to prevent the voltage across the gate oxide of transistor (10) from exceeding a predetermined voltage above which would be destructive to the transistor, a bypass transistor (32) is disposed between the output of the MOSFET driver (14) and the supply terminal (11). The gate of this transistor (32) is connected to the output node (12), such that the voltage on the gate of transistor (10) is limited to one threshold voltage below the voltage on the output node (12).

Abstract: A driving circuit for the electromagnetic relay provides a coil of the electromagnetic relay with stepped voltage having a first voltage which is slightly larger than a minimum operating voltage which caused the coil to generate magnetic field capable of closing contacts of the electromagnetic relay and a second voltage higher than the first voltage, in response to a triggering signal to trigger the electromagnetic relay. According to this structure, because the first voltage lower than the second voltage is applied to the coil firstly, the contacts are closed by attracting force of the coil risen gently. As a result, the bouncing of the moving contact can be prevented. In addition, the response time required for the closing of the contacts can be prevented to become long.

Abstract: An inductive load drive circuit includes a transistor for pulling-in an excitation current having a predetermined polarity and generated by an inductive load. The transistor is turned-on by a first idling loop when a drive voltage of the inductive load has a negative polarity, and the transistor is turned-on by a second idling loop when the drive voltage has a positive polarity. Though both of the first idling loop and the second idling operate on the basis of the drive voltage, in pulling the excitation current into the circuit, the drive voltage reaches a lower limit of a dynamic range at a time that the first idling loop is suitably operated while the drive voltage reaches an upper limit of the dynamic range at a time that the second idling loop is suitably operated.