Current Driver Patents (Class 327/108)
  • Patent number: 10447512
    Abstract: A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Feng Lin, Timothy M. Hollis
  • Patent number: 10425069
    Abstract: A signal output circuit includes a slope control circuit, a capacitor, a noise detector circuit and a fail-safe circuit. The slope control circuit charges and discharges the capacitor, the first terminal of which is connected to an output terminal, according to the control signal level, and drives transistors using the voltage of the second terminal of the capacitor, thereby controlling the slope of the output single. The noise detector circuit detects noise superimposed on the output terminal. When noise is detected, the fail-safe circuit performs a forced drive operation on the transistor to output the output signal at a level corresponding to the level of the control signal is output, regardless of the transistor being driven by the slope control circuit.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: September 24, 2019
    Assignee: DENSO CORPORATION
    Inventors: Norimasa Oka, Hiroshi Kawago
  • Patent number: 10411458
    Abstract: An overvoltage protection device including an output stage, a first switch and a first load providing circuit is provided. The output stage has a first input terminal to receive a first signal, and generates an output signal at an output terminal of the output stage according to the first signal. A first terminal of the first switch is coupled to the first input terminal of the output stage, and a control terminal of the first switch receives a second signal. The first signal is the delayed second signal. The first load providing circuit is coupled to a second terminal of the first switch. The first load providing circuit provides an impedance to the first input terminal when the first switch is turned on.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: September 10, 2019
    Assignee: ALi Corporation
    Inventors: Ching-Chung Cheng, Kuo-Kai Lin
  • Patent number: 10411652
    Abstract: An amplifier may include a first transistor. The amplifier may also include a second transistor coupled to the first transistor in an output stage of the amplifier. The amplifier may also include a level shift resistor coupled between a gate of the first transistor and a gate of the second transistor. The amplifier may further include a feedback bias circuit coupled to the gate of the first transistor and the gate of the second transistor through the level shift resistor. The feedback bias circuit may be configured to sense a common mode voltage of the output stage of the amplifier, and to compare the common mode voltage with a reference voltage to control a resistor bias current conducted by the level shift resistor.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: September 10, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Yu-Ching Yeh, Sean Joel Lyn, Cheng-Han Wang, Roger Brockenbrough
  • Patent number: 10389373
    Abstract: At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second transistors coupled to the network, and first and second resistors coupled to the first and second transistors. The DAC also comprises a voltage source coupled to the first resistor and a ground connection coupled to the second resistor. The DAC further includes a capacitor coupled to the first and second transistors and to the second resistor.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: August 20, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jagannathan Venkataraman, Eeshan Miglani
  • Patent number: 10389239
    Abstract: A power conversion device converting and outputting a characteristic of input power, includes: a power conversion unit including a normally-on type first switching element made of a nitride-based semiconductor material and converting the characteristic of power by a switching operation performed by the first switching element; an operation control unit controlling a switching operation of the first switching element; and an intelligent power switch including: a second switching element provided on a power input side of the power conversion unit and turning on/off power input to the power conversion unit; and a protection control unit including a current detection unit detecting a current flowing in the second switching element and controlling on/off of the second switching element and turn off the second switching element in a case where a current detected by the current detection unit exceeds a threshold value.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: August 20, 2019
    Assignees: FURUKAWA ELECTRIC CO., LTD., FURUKAWA AUTOMOTIVE SYSTEMS INC.
    Inventors: Kaoru Sugimoto, Ryosuke Tamura, Shusuke Kaya, Takezo Sugimura
  • Patent number: 10371756
    Abstract: An abnormality notification switch is switched on when a power storage module is abnormal but is switched off when the power storage module is normal. A first detection element outputs a signal indicating an abnormality of the power storage module when detecting that an electric current flows along an electric current line. A second detection element is inserted into an electric current line between a node and a second high-side reference potential that has a higher potential than a potential of a first high-side reference potential. The second detection element outputs a signal indicating an occurrence of a disconnection when detecting that no electric current flows along this electric current line. A retaining circuit retains a potential at the node higher than the first high-side reference potential and lower than the second high-side reference potential.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: August 6, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Yuta Kurosaki
  • Patent number: 10373562
    Abstract: The present application provides a gate driver circuit comprising at least one cascaded gate driver circuit unit. The low-level-holding enabling terminal of the gate driver circuit unit is connected to an adaptive voltage generating module. The adaptive voltage generating module generates a self-compensating voltage according to its constant current source and transmits to the low-level-holding enabling terminal, so as to provide an effective voltage level to the low-level-holding enabling terminal. Because the threshold voltage shift caused by pulling-down transistors in the low-level-holding module is embodied at the low-level-holding enabling terminal, the adaptive voltage generating module generates a self-compensating voltage with its constant current source according to the threshold voltage to compensate the increase of the threshold voltage.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: August 6, 2019
    Assignee: Peking University Shenzhen Graduate School
    Inventors: Shengdong Zhang, Chuanli Leng, Zhijin Hu, Congwei Liao
  • Patent number: 10374603
    Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: August 6, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Daniele Zella, Vanni Poletto, Mauro Foppiani
  • Patent number: 10374606
    Abstract: A lever shifter includes an output driver and a high-side gate driver. The high-side gate driver is configured to drive the high-side output transistor, and is coupled to an on pulse signal line that conducts an on pulse, and is coupled to an off pulse signal line that conducts an off pulse. The high-side gate driver includes a blocking circuit configured to enable generation of a drive signal to the high-side output transistor based on a voltage of a first of the on or off pulse signal line being greater than a first predetermined amount and a voltage of a second of the on or off signal line being less than a second predetermined amount.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: August 6, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Danyang Zhu, Jie Feng, Xiaonan Wang, Ball Fan
  • Patent number: 10361698
    Abstract: A gate drive circuit for generating asymmetric drive voltages comprises a gate drive transformer comprising: a primary winding responsive to a pulse width module (PWM) input signal to generate a bipolar signal having a positive bias voltage and a negative bias voltage; and a secondary winding responsive to the bipolar signal to generate a PWM output signal. A first charge pump is connected to the secondary winding responsive to the PWM output signal to generate a level shifted PWM output signal. A second charge pump is connected to the secondary winding to generate a readjusted PWM output signal by decreasing at least a portion of the level shifted PWM output signal. A gate switching device is connected to the first charge pump and second charge pump. A level shifted PWM output signal establishes an ON condition and the readjusted PWM output signal establishes an OFF condition of the gate MOSFET.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: July 23, 2019
    Assignee: Raytheon Company
    Inventors: Sriram Chandrasekaran, Michael S. Hockema
  • Patent number: 10355646
    Abstract: We disclose apparatus which may provide power amplification in millimeter-wave devices with reduced size and reduced power consumption, and methods of using such apparatus. One such apparatus comprises an input transformer; a first differential pair of injection transistors comprising a first transistor and a second transistor; a first back gate voltage source configured to provide a first back gate voltage to the first transistor; a second back gate voltage source configured to provide a second back gate voltage to the second transistor; a second differential pair of oscillator core transistors comprising a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are cross-coupled; a third back gate voltage source configured to provide a third back gate voltage to the third transistor; a fourth back gate voltage source configured to provide a fourth back gate voltage to the fourth transistor; and an output transformer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 16, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: See Taur Lee, Abdellatif Bellaouar
  • Patent number: 10348538
    Abstract: A transmitter may include a driver having a PMOS transistor and an NMOS transistor connected in series between a first power supply and a second power supply. The driver may be configured to output an output signal. The transmitter may further include a driver control circuit configured to control a gate voltage of the PMOS transistor and a gate voltage of the NMOS transistor based on a level of a data signal, an occurrence of a level transition of the data signal, and a direction of the level transition of the data signal.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: July 9, 2019
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Hyeongjun Ko, Mino Kim, Suhwan Kim, Deog-Kyoon Jeong
  • Patent number: 10340910
    Abstract: A drive circuit includes a first level shift circuit, a second level shift circuit, a pre-driver, and a high-side transistor. The first level shift circuit outputs a first switch signal. The second level shift circuit outputs a second switch signal. The pre-driver includes a first switch portion configured to perform switching in accordance with the first switch signal and a second switch portion configured to output a gate signal in accordance with the second switch signal. The high-side transistor outputs a high-side output signal to an output terminal with a second power supply voltage which is fed in accordance with the gate signal.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: July 2, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Takayuki Takida, Ryota Miwa, Takafumi Kiyono
  • Patent number: 10340913
    Abstract: Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period preceding the first portion.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Roy E. Greeff
  • Patent number: 10333327
    Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: June 25, 2019
    Assignee: Navitas Semiconductor, Inc.
    Inventors: Daniel Marvin Kinzer, Santosh Sharma, Ju Jason Zhang
  • Patent number: 10326411
    Abstract: An operational amplifier circuit is provided. The operational amplifier circuit includes a differential input stage circuit and a loading stage circuit. The differential input stage circuit includes an input circuit, a voltage maintaining circuit, and a current source. The input circuit includes a first input transistor and a second input transistor, for receiving a first and a second input signals, respectively. The voltage maintaining circuit includes a first branch circuit and a second branch circuit. The first branch circuit is coupled to the first input transistor for receiving the first input signal, and the second branch circuit is coupled to the second input transistor for receiving the second input signal. The current source is coupled to the first input transistor and the second input transistor. The loading stage circuit is coupled to the voltage maintaining circuit.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: June 18, 2019
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Chih-Wen Lu, Chih-Hsien Chou, Po-Yu Tseng, Jhih-Siou Cheng
  • Patent number: 10325659
    Abstract: Methods of operating an integrated circuit device, and integrated circuit devices configured to perform methods, including applying a particular voltage level to a first input of an input/output (I/O) buffer and to a second input of the I/O buffer, determining whether the I/O buffer is deemed to exhibit offset, and applying an adjustment to the I/O buffer offset while applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer if the I/O buffer is deemed to exhibit offset.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: June 18, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Qiang Tang, Ramin Ghodsi
  • Patent number: 10320377
    Abstract: An instrumentation device having a pulse output function for preventing breakage of a switching element even if a wrong wire is connected. A calculation unit includes: a positive power supply terminal; a negative power supply terminal; a signal terminal; a control circuit; an NPN-type transistor; a feedback circuit; a PTC thermistor; and an N-channel type MOSFET. The NPN-type transistor has a collector terminal connected to the positive power supply terminal, an emitter terminal connected to the negative power supply terminal, and a base terminal connected to the control circuit. The PTC thermistor is a resettable protection element, and is connected in series to the signal terminal. The N-channel type MOSFET has a drain terminal connected to the signal terminal through the PTC thermistor, a source terminal connected to the negative power supply terminal on a downstream side of the feedback circuit, and a gate terminal connected to the control circuit.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: June 11, 2019
    Assignee: OVAL CORPORATION
    Inventors: Tetsushi Kitano, Noriaki Nakayama, Yoshimine Tanabu, Kenji Washio
  • Patent number: 10312934
    Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a current source and a digital to analog convertor. The current source includes a current output circuit and an impedance gain circuit which is configured to increase output impedance of the current output circuit. The current output circuit includes a first PMOS transistor and a second PMOS transistor. The impedance gain circuit includes a first end, a second end, a third end which is connected to a supply voltage, and a fourth end which is connected to the ground. A source electrode of the first PMOS transistor is connected to the supply voltage, a drain electrode of the first PMOS transistor is connected to a source electrode of the second PMOS transistor and the first end of the impedance gain circuit, and a gate electrode of the first PMOS transistor is controlled by a first bias voltage.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: June 4, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Chunpeng Chen
  • Patent number: 10312904
    Abstract: A power semiconductor module having switching elements includes: a collector main terminal and a collector auxiliary terminal connected to a collector potential of the switching element; a gate auxiliary terminal connected to a gate potential of the switching element; and an emitter main terminal and an emitter auxiliary terminal connected to an emitter potential of the switching element. A power converter includes a voltage dividing circuit board that generates a divided voltage obtained by dividing a voltage between the collector auxiliary terminal and the emitter auxiliary terminal and transmits to a gate driving circuit. The voltage dividing circuit board is electrically connected to the collector auxiliary terminal and the emitter auxiliary terminal. A gate driving circuit changes a driving speed of the switching element according to the divided voltage.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: June 4, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yukio Nakashima, Takayoshi Miki
  • Patent number: 10305386
    Abstract: Systems and methods are provided for protecting a power conversion system. A system controller includes a two-level protection component and a driving component. The two-level protection component is configured to detect an output power of a power conversion system and generate a protection signal based on at least information associated with the output power. The driving component is configured to generate a drive signal based on at least information associated with the protection signal and output the drive signal to a switch associated with a primary current flowing through a primary winding of the power conversion system. The driving component is further configured to generate the drive signal corresponding to a first switching frequency to generate the output power equal to a first power threshold and generate the drive signal corresponding to a second switching frequency to generate the output power equal to a second power threshold.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: May 28, 2019
    Assignee: On-Bright Electronics (Shanghai) Co., Ltd.
    Inventors: Xiaomin Huang, Huawei Lv, Chao Yao, Qiang Luo, Lieyi Fang
  • Patent number: 10305708
    Abstract: Methods, systems, and apparatuses are described for improving the signal integrity of a differential pair of signals by mitigating a non-balanced channel deficiency. For example, signal integrity may be improved by independently shaping and/or independently controlling the slopes (e.g., the rising edge and/or falling edge) of each signal of a differential pair of signals to counteract the effects caused by non-balanced deficiencies to provide a balanced differential pair of signals (i.e., signals having symmetrical impedances, loads, etc.).
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: May 28, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Shwetabh Verma, Bhaskar Banerjee, Amiad Dvir, Assaf Naor
  • Patent number: 10305466
    Abstract: A semiconductor module including a semiconductor element, a controller, a cooler, and a temperature sensor are included. The controller is connected to the semiconductor module and controls switching operation of the semiconductor element. The temperature sensor measures a coolant temperature, which is a temperature of the coolant. The controller controls turn-off speed of the semiconductor element based on the coolant temperature. The controller increases the turn-off speed as the coolant temperature rises.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: May 28, 2019
    Assignee: DENSO CORPORATION
    Inventor: Yuu Yamahira
  • Patent number: 10291225
    Abstract: An isolated insulated gate bipolar transistor (IGBT) gate driver is provided which integrates circuits, in-module, to support the measurements of threshold voltage, and collector-emitter saturation voltage of IGBTs. The measured gate threshold and collector-emitter saturation voltage can be used as precursors for state of health predictions for IGBTs. During the measurements, IGBTs are biased under specific conditions chosen to quickly elicit collector-emitter saturation and gate threshold information. Integrated analog-to-digital converter (ADC) circuits are used to convert measured analog signals to a digital format. The digitalized signals are transferred to a micro controller unit (MCU) for further processing through serial peripheral interface (SPI) circuits.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: May 14, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiong Li, Anant Kamath
  • Patent number: 10276571
    Abstract: A system and method may determine the operating parameters, such as voltages, of MOS transistors within a circuit design by testing or simulation, for example and may identify a MOS transistor operating with its drain voltage higher than its gate voltage in the circuit. The design system and method may substitute a smaller transistor, having a high-k dielectric layer, for the original transistor in the circuit design.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: April 30, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyong-Taek Lee, Sang-Woo Pae, Hye-Jin Kim, June-Kyun Park, Hyun-Woo Lee
  • Patent number: 10277219
    Abstract: In accordance with an embodiment, an electronic circuit includes a first transistor device, at least one second transistor device, and a drive circuit. The first transistor device is integrated in a first semiconductor body, and includes a first load pad at a first surface of the first semiconductor body and a control pad and a second load pad at a second surface of the first semiconductor body. The at least one second transistor device is integrated in a second semiconductor body, and includes a first load pad at a first surface of the second semiconductor body and a control pad and a second load pad at a second surface of the second semiconductor body. The first load pad of the first transistor device and the first load pad of the at least one second transistor device are mounted to an electrically conducting carrier.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: April 30, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Rainald Sander, Andreas Meiser
  • Patent number: 10277380
    Abstract: A configurable transceiver includes a first transmitter, an edge rate controller, a second transmitter, a subtractor, a bandwidth controller and a main controller. The first transmitter is configured to generate a first signal for transmission via a transmission link. The second transmitter is configured to generate a replica signal associated with the first signal. The edge rate controller is communicatively coupled to the first and/or second transmitter and is configured to control an edge rate parameter of the first and/or second signal. The subtractor is configured to subtract the replica signal from a signal received via the transmission link. The bandwidth controller is configured to control a bandwidth parameter of a difference signal received from the output of the subtractor. The main controller chooses edge rate and bandwidth control words per desired link rates. It can also automatically find the maximum possible link speed.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: April 30, 2019
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Caglar Yilmazer, Arda K. Bafra, Umut Yilmazer
  • Patent number: 10270433
    Abstract: In various embodiments, a master-slave clock generation circuit may include a first delay circuit, a second delay circuit, a first tristate inverter, and a second tristate inverter. The first delay circuit may delay a clock signal and output a slave clock signal and a delayed clock signal. The first tristate inverter may selectively invert the clock signal based on a scan enable signal. The second tristate inverter may selectively invert the delayed clock signal based on the scan enable signal. The second delay circuit may delay a signal received from the first tristate inverter, the second tristate inverter, or both, and output a master clock signal. As a result, the master-slave clock generation circuit may be configured to output a master clock signal and a slave clock signal having differing sets of relative timing characteristics depending on whether the scan enable signal is asserted.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 23, 2019
    Assignee: Apple Inc.
    Inventor: Vivekanandan Venugopal
  • Patent number: 10262618
    Abstract: A GOA circuit includes GOA circuit units. Each GOA circuit has a holding module A first transistor and a second transistor in the holding module holds the voltage imposed on the first control node to be at high voltage level. Also, the transistors form a direct current passage between the first control node and a first fixed voltage at high voltage level so the voltage imposed on the first control node is not lowered due to electricity leakage. The GOA circuit unit can resolve the problem of easy leakage of electricity. When the scanning signals are output by the GOA circuit unit, the stability is highly ensured.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: April 16, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Mang Zhao, Gui Chen
  • Patent number: 10243549
    Abstract: There is provided a drive circuit for turning on/off a power element which controls a main current flow between a first main electrode and a second main electrode in response to a drive signal applied to a control electrode. The drive circuit includes a a first semiconductor switching element and a second semiconductor switching element which are connected in series with a semiconductor element and provided between the power supply terminal and the ground terminal, third semiconductor switching element and a fourth semiconductor switching element which are connected in series, and a control circuit which controls turn-on/off of the power element by turning on/off the first to fourth semiconductor switching elements. The semiconductor element has a positive temperature characteristic.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 26, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hidetomo Ohashi
  • Patent number: 10243467
    Abstract: The subject matter of this document can be embodied in a method that includes a voltage regulator having an input terminal and an output terminal. The voltage regulator includes a high-side transistor between the input terminal and an intermediate terminal, and a low-side transistor between the intermediate terminal and ground. The voltage regulator includes a low-side driver circuit including a capacitor and an inverter. The output of the inverter is connected to the gate of the low-side transistor. The voltage regulator also includes a controller that drives the high-side and low-side transistors to alternately couple the intermediate terminal to the input terminal and ground. The controller is configured to drive the low-side transistor by controlling the inverter. The voltage regulator further includes a switch coupled to the low-side driver circuit. The switch is configured to block charge leakage out of the capacitor during an off state of the low-side transistor.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 26, 2019
    Assignee: Volterra Semiconductor LLC
    Inventors: Chiteh Chiang, Marco A. Zuniga, Yang Lu
  • Patent number: 10243247
    Abstract: A bandstop filter includes a coupled line bandstop filter, a capacitor and a resistor. The coupled line bandstop filter includes a transmission line element and a shaped transmission line element. The shaped transmission line element includes a coupled line element disposed so as to electromagnetically couple with the transmission line element, and a second line element disposed so as not to be parallel with the transmission line element. The capacitor is electrically connected to the coupled line element. A portion of the received oscillating signal includes a bandstop frequency. Physical attributes of the coupled line bandstop filter, the capacitor and the resistor are such that the portion of the received oscillating signal including the bandstop frequency is attenuated.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: March 26, 2019
    Assignee: The United States of America as represented by Secretary of the Navy
    Inventors: Jia-Chi S. Chieh, Jason F. Rowland
  • Patent number: 10243552
    Abstract: There is provided a drive circuit for turning on/off a power element which controls a main current flow between a first main electrode and a second main electrode in response to a drive signal applied to a control electrode. The drive circuit includes a first semiconductor switching element and a second semiconductor switching element which are connected in series and provided between the power supply terminal and the ground terminal, a third semiconductor switching element and a fourth semiconductor switching element which are connected in series with a semiconductor element, and a control circuit which controls turn-on/off of the power element by turning on/off the first to fourth semiconductor switching elements. The semiconductor element has a negative temperature characteristic.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 26, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hidetomo Ohashi
  • Patent number: 10236868
    Abstract: A semiconductor device includes: a semiconductor chip including a level shift circuit to output a high amplitude signal from an input of a logical signal, the level shift circuit including a series coupling circuit coupled to a second power supply, a control circuit coupled to the series coupling circuit for controlling the series coupling circuit based on the logical signal, and a first potential conversion circuit coupled between the series coupling circuit and the control circuit and coupled to a first power supply. The series coupling circuit includes a plurality of first MOS transistors coupled in series between the second power supply and a reference power supply, and a plurality of second MOS transistors coupled in series between the second power supply and the reference power supply in series with the plurality of first MOS transistors.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: March 19, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Koji Takayanagi
  • Patent number: 10230366
    Abstract: A control portion and semiconductor switches included in a power supply system function as a current control device. The source of the semiconductor switch is connected to the source of the semiconductor switch. The two semiconductor switches connect the respective positive electrodes of a first power storage element and a second power storage element to each other. The control portion controls a current flowing between the drains of the two semiconductor switches by substantially simultaneously turning on or off the two semiconductor switches. The respective breakdown voltages between the drain and the source of the two semiconductor switches are different from each other.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: March 12, 2019
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Kazuki Masuda, Byeongsu Jeong
  • Patent number: 10224922
    Abstract: An output stage of an output buffer circuit includes a first drive transistor and a first cascode transistor (coupled in series between a first supply node and an output node) and a second drive transistor and a second cascode transistor (coupled in series between the output node and a second supply node). Gates of the first and second cascode transistors are biased with first and second bias voltages, respectively. The first bias voltage equals the first supply voltage at the first supply node when the first supply voltage is less than a threshold, and is fixed at a fixed voltage for any first supply voltage exceeding the threshold voltage. The second bias voltage equals a fixed voltage when the first supply voltage is less than a threshold voltage, and is offset from the first supply voltage by a fixed difference for any first supply voltage exceeding the threshold.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: March 5, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Manoj Kumar Kumar Tiwari, Saiyid Mohammad Irshad Rizvi
  • Patent number: 10223194
    Abstract: Data corrupted by a soft error is recovered. A storage device includes a first memory cell, a second memory cell, a sense circuit electrically connected to the first memory cell through a first sense line and to the second memory cell through a second sense line, a digital-analog converter circuit electrically connected to the first memory cell and the second memory cell through a bit line, and an analog-digital converter circuit. The digital-analog converter circuit has a function of applying voltages as first signals to the first memory cell and the second memory cell. Even when a soft error occurs in the first memory cell or the second memory cell, the storage device has a function of recovering data corrupted by the soft error because the sense circuit selects and outputs a higher one of the voltages applied to the first memory cell and the second memory cell.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: March 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Yoshiyuki Kurokawa
  • Patent number: 10223960
    Abstract: The transmission delay time of a receiver for receiving a differential signal is reduced. A first amplifier circuit is provided in an input stage of the receiver, and a second amplifier circuit is provided in an output stage of the receiver. The first amplifier circuit is a differential input, differential output amplifier circuit. The second amplifier circuit is a differential input, single-ended output amplifier circuit. A first power supply voltage and a second power supply voltage are input as a high-level power supply voltage and a low-level power supply voltage to the first amplifier circuit and the second amplifier circuit, respectively. The withstand voltage of transistors of a differential pair of the first amplifier circuit is higher than the withstand voltage of another transistor included in the first amplifier circuit and a transistor included in the second amplifier circuit.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: March 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Inoue, Kei Takahashi
  • Patent number: 10224919
    Abstract: A power switch device includes a switch which is configured to switch a load signal between an on state and an off state. A first terminal and a second terminal of the power switch device are configured to provide a supply voltage to the power switch device. The second terminal is further configured to provide a control signal to the power switch device. The control signal is generated by disconnecting the second terminal from an external voltage source. A storage circuit of the power switch device is configured to capacitively store a status of the supply voltage. A control circuit of the power switch device is configured to control operation of the power switch device depending on the stored status of the supply voltage.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: March 5, 2019
    Assignee: Infineon Technologies AG
    Inventors: Michael Asam, Carmelo Giunta
  • Patent number: 10213188
    Abstract: Disclosed herein are a high voltage switching circuit which includes one or more main switching devices connected to one or more current sources, and a control circuit unit configured to control a potential difference between terminals of each of the main switching devices within a predetermined range by receiving current from the one or more current sources.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: February 26, 2019
    Assignees: SAMSUNG ELECTRONICS CO., LTD., Industry-University Cooperation Foundation Hanyang University
    Inventors: Jong Keun Song, Taeho Jeon, Oh-Kyong Kwon, Sung-Jin Jung
  • Patent number: 10218397
    Abstract: A radio frequency (RF) front end device is disclosed. The device comprises a plurality of micro-electro-mechanical system (MEMS) transfer switches having a plurality of parallel switch inputs and parallel switch outputs. The device comprises a plurality of banks of a plurality of parallel signal conditioning devices and each bank comprising a plurality of parallel paths having an input side and an output side, at least two of the banks of the plurality of signal conditioning devices couple the input side to the plurality of parallel switch outputs of a preceding MEMS transfer switch and the output side to the plurality of parallel switch inputs of a succeeding MEMS transfer switch. The MEMS transfer switches are controlled to condition a wideband signal through a selected set of signal conditioning devices to improve selection sensitivity of at least one frequency in a wideband. A method and RF communications device are also disclosed.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: February 26, 2019
    Assignee: LOCKHEED MARTIN CORPORATION
    Inventors: Bryan Charles Gundrum, Steve Todd Nicholas, Lowell Kent Sherman
  • Patent number: 10217427
    Abstract: The present application relates to a gate drive unit circuit, comprising an input unit, an output unit, a pull-up node control unit, a pull-down node control unit and a pull-down unit. The input unit is used for transmitting a signal inputted by a first input signal terminal to a first node. The pull-up node control unit is used for transmitting a signal inputted by a first voltage terminal or a second voltage terminal to a pull-up node. The output unit is used for transmitting a signal inputted by a first control signal terminal to an output signal terminal. The pull-down node control unit is used for transmitting the input inputted by the first voltage terminal or the second voltage terminal to a pull-down node. The pull-down unit is used for transmitting a signal inputted by the second voltage terminal to the output signal terminal.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: February 26, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yuanbo Zhang, Seungwoo Han, Xing Yao
  • Patent number: 10199818
    Abstract: A system and method of over-voltage protection includes a switch coupled between a power source and a load, a detection circuit configured to detect an onset of an over-voltage event at the load; and a driver circuit coupled to the switch and the detection circuit. The driver circuit includes a boost sub-circuit that provides a low-resistance path for opening the switch in a boost mode, the boost mode being triggered by the onset of the over-voltage event and having a predetermined duration and a steady state sub-circuit that provides a high-resistance path for holding the switch open during steady state operation when the boost mode.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: February 5, 2019
    Assignee: Integrated Device Technology, Inc.
    Inventors: Rosario Pagano, Herman R. Paz, Siamak Abedinpour
  • Patent number: 10199916
    Abstract: A power switch driver for driving a control terminal of a power switch to drive a load, the power switch driver having a negative feedback circuit to control current delivered to the control terminal. The negative feedback circuit has a current output circuit having a current source and a current sink and serving for providing the current of the control terminal and configured to receive an output current control signal to control a magnitude of the current provided by the current output circuit, a terminal voltage input circuit for receiving a voltage from the control terminal and to output an indication of the voltage, an amplifier coupled to the terminal voltage input circuit for amplifying the terminal voltage indication to generate an amplifier output, and a reference voltage input circuit for receiving a reference voltage, having at least one resistor, and coupled to a charge supply input of the amplifier.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: February 5, 2019
    Assignee: MASCHINENFABRIK REINHAUSEN GMBH
    Inventors: Mark Snook, Robert John Leedham, Robin Lyle
  • Patent number: 10186199
    Abstract: An organic light emitting display device may include a display panel, a power supply, and a display driver, The display panel may comprise a plurality of scan lines, a plurality of data lines, and a plurality of pixels connected to the scan lines and to the data lines. The power supply may supply a first pixel voltage and a second pixel voltage to the pixels. The display driver may control the display panel. The display panel may display a first image in a first frame frequency during a first driving mode, and display a second image in a second frame frequency that is lower than the first frame frequency during a second driving mode, according to a control by the display driver.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: January 22, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jin Jeon
  • Patent number: 10187051
    Abstract: The present disclosure discloses a circuit and a method for controlling gate current of a semiconductor switching device. The circuit comprises a current controlled variable inductor connected to a gate terminal of the semiconductor switching device and a feedback control circuit. The feedback control circuit comprises a differential module to compute an instantaneous rate of change of gate current with respect to time, a reference generator to generate a reference voltage and a control unit to regulate value of inductance of the variable inductor for controlling the gate current of the semiconductor switching device.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: January 22, 2019
    Assignee: Hitachi, Ltd.
    Inventor: Ramachandra Sekhar Kondapalli
  • Patent number: 10177759
    Abstract: Switching circuitry includes first and second transistors in series between two terminals and including a common control node with a capacitance between the common control node and an intermediate point. A control circuit includes first and second circuits configured to charge and discharge the capacitance as a function of first and second control signals. The control circuit includes a third circuit having a plurality of diodes and a switch that operates when the voltage at the capacitance is greater than a threshold two diodes in cascade between the intermediate point and the common control node to enable current flow from the intermediate point to the common control node. When the voltage at the capacitance is smaller than the given threshold two diodes are connected in series between the common control node and the intermediate point to enable current flow from the common control node to the intermediate point.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: January 8, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Valeria Bottarel, Sandro Rossi
  • Patent number: 10177775
    Abstract: At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second transistors coupled to the network, and first and second resistors coupled to the first and second transistors. The DAC also comprises a voltage source coupled to the first resistor and a ground connection coupled to the second resistor. The DAC further includes a capacitor coupled to the first and second transistors and to the second resistor.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: January 8, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jagannathan Venkataraman, Eeshan Miglani
  • Patent number: 10176751
    Abstract: A drive circuit having an output terminal includes a buffer circuit including a first transistor and a second transistor that are connected in parallel between a power supply and the output terminal. The first transistor and the second transistor are controlled such that after the first transistor and the second transistor are simultaneously turned on, the second transistor is turned off earlier than the first transistor.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: January 8, 2019
    Assignee: JOLED INC.
    Inventors: Tetsuro Yamamoto, Hiroshi Fujimura