Abstract: A scan driver includes: a first transistor having a first electrode coupled to an output scan line, a second electrode coupled to a first power line, and a gate electrode coupled to a first node; a second transistor having a first electrode coupled to a first clock line, a second electrode coupled to the output scan line, and a gate electrode coupled to a second node; a third transistor having a first electrode coupled to the first node, a second electrode coupled to a first input scan line, and a gate electrode coupled to a second clock line; and a fourth transistor having a first electrode coupled to the second node and a second electrode and a gate electrode, which are coupled to a second input scan line, wherein the first input scan line and the second input scan line are different from each other.

Abstract: An apparatus to insure safe behavior in an inverter system. In one embodiment, the apparatus includes a first high side gate driver, a first low side gate driver, a microcontroller configured to control the first high side and low side gate drivers. A voltage regulator provides a supply voltage to the microcontroller. A first pair of high side voltage regulators provide a first pair of high side supply voltages to the first high side gate driver. A first pair of low side voltage regulators provide a first pair of low side supply voltages to the first low side gate driver.

Abstract: Devices and methods are provided for controlling dead-time of a direct current to direct current (DC-DC) converter. A control circuit includes a first transistor having a source/drain terminal coupled to an output voltage of the DC-DC converter configured to provide current based on the output voltage. The control circuit also includes a digital up/down counter having an output terminal electrically coupled to an input terminal of a delay cell of the DC-DC converter. A current sensing circuit of the control circuit is electrically coupled to an input terminal of the digital up/down counter configured to receive the current and drive the digital up/down counter based on the current.

Abstract: Disclosed is a method and a control circuit. The method includes operating a buffer circuit in a first operating mode or a second operating mode. Operating the buffer circuit in the first operating mode includes buffering, by a first capacitor of the buffer circuit, power provided by a power source and received by a load. Operating the buffer circuit in the second operating mode includes connecting a second capacitor in series with the first capacitor to form a capacitor series circuit, supplying power to the load by the capacitor series circuit, and regulating a first voltage across the capacitor series circuit. Regulating the first voltage includes transferring charge from the first capacitor to the second capacitor.

Abstract: Various implementations described herein are directed to a device having an input-output pad configured to receive and supply an input-output pad voltage. The device may include gate tracking circuitry that receives a first voltage, receives a second voltage different than the first voltage, receives node voltages and provides a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage and the node voltages. The device may include output circuitry that receives the first tracking voltage and the second tracking voltage from the gate tracking circuitry and provides the input-output pad voltage to the input-output pad based on the first tracking voltage and the second tracking voltage.

Abstract: A semiconductor device includes an on-die resistor circuit comprising an on-die resistor, a calibration circuit configured to perform a calibration operation on the on-die resistor, and a calibration control circuit configured to control the calibration operation of the calibration circuit. The calibration circuit includes a current generating circuit configured to supply a calibration current to the on-die resistor and a comparing circuit configured to compare the magnitude of a first input signal that is generated by the calibration current and the on-die resistor with a magnitude of a second input signal that is generated by the calibration current and an external resistor.

Abstract: The invention relates to a transmitter for transmitting a process variable to a programmable logic controller. In a current mode a 4-20 milliamp current is fed into a burden and in a voltage mode 0-10 Volt signals are generated. The transmitter includes a process value input, a current stage, a voltage stage and a U/I output for the current or the voltage signal, and a U/I control input for switching between the two modes. The transmitter is configured to feed a current which is dependent on the voltage across the burden into the current stage via a resistor and thus to compensate for a current loss at the voltage stage which is dependent on the voltage across the burden.

Abstract: The invention relates to a switch system (1) comprising a power line (2) for supplying a charge from a voltage source (+Vbat), said power line having a main switch (Q1) comprising a first main terminal (D) and a second main terminal (S), between which a main current (Ip) is intended to pass, and a control terminal (G) for selectively placing the main switch (Q1) in a closed, open or semi-closed state, the main switch (Q1) in its semi-closed state being equivalent to a variable resistor controlled by the control terminal and connected between the first and the second main terminal, characterized in that the switch system (1) further comprises a current-limiting device (3) designed to, when the main current (Ip) exceeds a maximum current threshold, decrease a control current (Ig) entering the control terminal (G), so as to cause the main switch (Q1) to transition from the closed state to the semi-closed state, so as to limit the main current.

Abstract: Power converting devices (100) for power tools. One embodiment provides a power converter device (100) including a power source (200), a power converter (210) coupled to the power source (200), and an electronic processor (220) coupled to the power converter (210) to control the operation of the power converter (210). The power converter (210) is configured to receive an input power in one form or at a first voltage from the power source and convert the input power to an output power in another form or at a second voltage. The power converter (210) includes at least one wide bandgap field effect transistor controlled by the electronic processor (220) to convert the input power to output power.

Abstract: The present invention relates to a method for recharging an energy store (102) used to drive a power semiconductor switch (100), wherein the energy store (102) and the power semiconductor switch (100) are at the same potential, wherein a switching state of the power semiconductor switch (100) is effected by a controller (204, 712), wherein the controller (204) assigns a respective potential value to the energy store (102) at a respective switching state (202) and wherein, by driving at least one charging switch (112, 114, 122, 132, 142, 152), charging of the energy store (102) is activated as soon as the potential value of the energy store (102) corresponds to a ground potential of a supply voltage (106, 216).

Abstract: A gate drive device drives a gate of each of two semiconductor switching elements constituting upper and lower arms of a half bridge circuit. The gate drive device detects a peak value of an element voltage that is a voltage of a main terminal of one of the two semiconductor switching elements, as one semiconductor switching element, or a change rate of the element voltage during a change period in which the element voltage changes. The gate drive device determines whether an energization to the one semiconductor switching element during the change period is a forward energization in which a current flows in a forward direction or a reverse energization in which the current flows in a reverse direction.

Abstract: There are an amplifier circuit which includes a first current source that is connected to a power supply line to which a first electric potential is supplied, a differential input circuit that is connected between the first current source and a first node and configured to receive a differential input signal, a second current source that is connected between a power supply line to which a second electric potential is supplied and the first node, and a load circuit that is connected between a power supply line to which the first electric potential is supplied and a second node, and an inductor circuit is further connected between the first node and the second node. Thereby, the amplifier circuit achieves both lower voltage and linearity.

Abstract: A gate drive device drives a gate of a semiconductor switching element constituting an upper or lower arm of a half bridge circuit which supplies an output current, which is alternating current, to a load. The gate drive device detects a peak value of an element voltage which is a voltage of a main terminal of the semiconductor switching element or a change rate of the element voltage when the semiconductor switching element is switching. The gate drive device acquires a maximum value among a plurality of peak values or a plurality of change rates during a predetermined detection period including a period in which the semiconductor switching element performs switching multiple number of times.

Abstract: A gate driving circuit and a display panel are provided. The gate driving circuit includes M shift registers and N clock signal lines; every N adjacent shift registers among the M shift registers are respectively connected to the N clock signal lines, where N is an even number greater than or equal to 4, and M is an integer greater than or equal to N; a signal output terminal (OUTPUT) of an ith shift register is connected to a signal input terminal (INPUT) of a (i+p)th shift register, where (N?4)/2?p?N/2, and i is taken from 1 to (M?p); and a pull-up reset signal terminal of a jth shift register is connected to a signal output terminal (OUTPUT) of a (j+q)th shift register, where 1<q?p<N/2, and j is taken from 1 to (M?q).

Abstract: An H-bridge integrated laser driver optimizes power dissipation, impedance matching, low-swing and high-swing reliability for electro-absorption modulated laser (EML) and directly modulated laser diode (DML) applications. The laser driver includes a retimer for converting low-speed parallel data to a high-speed serial bit stream and to an inverted representation of the high-speed parallel bit stream, an M-bit PMOS DAC configured to receive a first buffered bit stream, an N-bit NMOS DAC configured to receive a second buffered bit stream substantially synchronized with the first buffered bit stream. A protective device is coupled between the M-bit DAC and the N-bit DAC.

Abstract: A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.

Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

Abstract: In a first mode, a first feedback controller generates a first control signal SCTRL1 based on a signal at a first feedback pin, so as to control a first pre-driver. A second feedback controller ¥ generates a second control signal based on a signal at a second feedback pin, so as to control a second pre-driver. In a second mode, the first feedback controller ¥ generates the first control signal based on a signal at the first feedback pin, so as to control the first pre-driver. The second pre-driver drives the second pre-driver based on a third control signal received from a first circuit block.

Abstract: Embodiments included herein are directed towards a transmitter circuit. The circuit may include a most significant bit (“MSB”) main driver and a most significant bit boost driver operatively connected to the MSB main driver. The circuit may also include a least significant bit (“LSB”) main driver and a least significant bit boost driver operatively connected to the LSB main driver, wherein the MSB main driver and the LSB main driver are configured to receive two parallel non-return-to-zero (“NRZ”) data inputs.

Abstract: A semiconductor integrated circuit device includes a current leakage detector, a leakage compensation pulse generator, and a leakage compensation voltage generator. The current leakage detector is configured to compare an internal voltage signal with a plurality of reference voltage signals with different levels to generate a current leakage state signal. The leakage compensation pulse generator is configured to generate a bias level compensation signal based on the current leakage state signal and a temperature state signal. The leakage compensation voltage generator is configured to generate the internal voltage signal based on the bias level compensation signal.

Abstract: An oscillator capable of quick startup is provided. A transistor is provided between an output terminal of a certain stage inverter and an input terminal of the following stage inverter included in the voltage controlled oscillator. With the use of the on resistance of the transistor, the oscillation frequency of the clock signal is controlled. While supply of the power supply voltage is stopped, a signal that is input to the input terminal of the inverter just before supply of the power supply voltage is stopped is stored by turning off the transistor. This operation makes it possible to immediately output a clock signal that has the same frequency as that before supply of the power supply voltage is stopped at the time when the power supply voltage is supplied again.

Abstract: A method of driving an electrical load includes coupling a power supply source to a power supply pin of a driver circuit, and coupling an electrical load to at least one output pin of the driver circuit. A driver sub-circuit of the driver circuit produces at least one driving signal for driving the electrical load. The at least one driving signal is provided to the electrical load via the at least one output pin. The at least one driving signal is modulated to supply the electrical load with a load current and to subsequently interrupt the load current. A compensation current pulse is sunk from the power supply pin, at a compensation circuit of the driver circuit, in response to the load current being interrupted.

Abstract: A power domain change circuit includes an input circuit and an output circuit. The input circuit is suitable for operating in a first power domain and generating first and second intermediate processing signals. The output circuit is suitable for operating in a second power domain and generating a final output signal by averaging and combining transition jitter components of the first and second intermediate processing signals.

Abstract: A driving circuit, a method for driving the same, and a microfluidic device are provided. The driving circuit includes a constant voltage writing module configured to transmit a constant voltage to an output terminal of the driving circuit, an AC voltage writing module configured to transmit an AC voltage to the output terminal of the driving circuit, a first switch, and a first capacitor. The first switch includes an input terminal electrically connected to a third signal line, an output terminal electrically connected to control terminals of the AC voltage writing module and the constant voltage writing module, and a control terminal electrically connected to a first scan line. The first capacitor is configured to stabilize a potential of the output terminal the first switch.

Abstract: A power converter including a transformer, a resonant circuit including the transformer and a resonant capacitor having a characteristic resonant frequency and period, and output circuitry connected to the transformer for delivering a rectified output voltage to a load. Primary switches drive the resonant circuit, a switch controller operates the primary switches in a series of converter operating cycles which include power transfer intervals of adjustable duration during which a resonant current at the characteristic resonant frequency flows through a winding of the transformer. The operating cycles may also include energy recycling intervals of variable duration for charging and discharging capacitances within the converter.

Abstract: Voltage level conversion circuits include PMOS pull-down devices or NMOS pull-up devices, and inverters with outputs that determine gate voltages of these devices. The inverters are powered by moving supply voltages, for example complementary supply voltages generated from a pair of cross-coupled inverters. The cross-coupled inverters may implement a data storage latch with the moving supply voltages generated from the internal data storage nodes of the latch.

Abstract: An electronic device may have a display. A gaze detection system may gather information on a user's point of gaze on the display. Based on the point-of-gaze information, control circuitry in the electronic device may produce image data for an image with areas of different resolutions. A full-resolution portion of the image may overlap the point of gaze. Lower resolution portions of the image may surround the full-resolution portion. The display may have a pixel array. The pixel array may include rows and columns of pixels. Data lines may be used to supply data to the columns of pixels in accordance with row selection signals supplied to the rows of pixels. Display driver circuitry may be used to display the image using the pixel array. The display driver circuitry may have row selection circuitry and column expander circuitry that are responsive to a resolution mode selection signal.

Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.

Abstract: A method of generating ultrasound by driving an array of ultrasonic transducers comprises a charge transfer procedure. The charge transfer procedure comprises switching a terminal of a first ultrasonic transducer of the array, at a first electric potential, to a charge distribution bus; switching a terminal of a second ultrasonic transducer of the array, at a second electric potential different than the first potential, to the charge distribution bus; and allowing charge to flow between the first ultrasonic transducer and the second ultrasonic transducer through the charge distribution bus.

Abstract: The present invention discloses a wordline driver circuit for a random-access memory (RAM), which can reduce leakage during power down mode. The circuit includes a pre-driver stage on header and footer. The pre-driver stage includes a strap buffer defining a header and comprising a first switch connecting a first set of wordlines to a first voltage. The pre-driver stage includes an input-output buffer defining a footer and comprising a second switch connecting a second set of wordlines to a second voltage. In the pre-driver stage, the strap buffer further includes a third switch connecting the second set of wordlines to the first voltage and a fourth switch connecting the first set of wordlines to the second voltage.

Abstract: A multi-level pulser circuit comprises a set of first input pins for receiving respective positive voltage signals at different voltage levels, a set of second input pins for receiving respective negative voltage signals at different voltage levels, and a reference input pin configured to receive a reference voltage signal intermediate the positive voltage signals and the negative voltage signals. The circuit comprises an output pin configured to supply a pulsed output signal. The circuit further comprises control circuitry configured to selectively couple the output pin to one of the first input pins, the second input pins and the reference input pin to generate the pulsed output signal at the output pin.

Abstract: A power drive circuit includes a power conversion module, a plurality of gate drivers, a waveform processing unit, a control unit, a weighting unit, and a comparator. Each gate driver includes a drive resistance setting value. The waveform processing unit outputs a current absolute value waveform of an AC power. The weighting unit generates a trigger voltage. When the comparator determines that the current absolute value waveform is greater than the trigger voltage, the comparator outputs a slew rate control signal to each of the gate drivers. When the gate driver receives the slew rate control signal, each of the gate drivers decreases the drive resistance setting value of the gate driver.

Abstract: A driver circuit includes an output terminal adapted for driving a data signal through a coupling capacitor to an external device. A first transistor is employed to drive the signal, and an N-type metal-oxide semiconductor (NMOS) transistor couples power to the first transistor. The NMOS transistor includes a first terminal connected to a positive terminal of a voltage supply, a second terminal coupled to an output terminal through a termination resistor, a gate terminal, and a bulk terminal connected to the negative terminal of the voltage supply. A charge pump circuit supplies a voltage to a gate terminal of the NMOS transistor, and is operable to provide a first voltage higher than that of the voltage supply to activate the NMOS device, and, responsive to detecting a ramp-down of the supply voltage, transition to providing the supply voltage to the NMOS device gate terminal.

Abstract: A gate driver on array (GOA) circuit and a display panel is provided. The GOA circuit includes a plurality of cascading GOA units. A current stage of the GOA units includes: a pull-up module, a pull-up control circuit unit, and a selection module. The pull-up module includes a first transistor. A source of the first transistor is connected to the selection module, a gate is connected to the pull-up control module through a first node, and a drain is configured to output a scan signal of the current stage. The selection module is configured to receive a first control signal and a second control signal to control the clock signal to transmit to the source of the first transistor.

Abstract: An improved power converter produces power through a power switch in response to an activation signal that has an on-time and a switching frequency. An on-time signal has a constant on-time and controls the on-time of the activation signal. An error signal indicates that the switching frequency is not equal to a reference frequency. A step up signal and a step down signal are based on the error signal. A count signal is increased in response to the step up signal and decreased in response to the step down signal. An on-time pulse has a duration that is related to a value of the count signal. The on-time pulse controls the constant on-time of the on-time signal and maintains the switching frequency at about the reference frequency.

Abstract: The present disclosure relates to a memory device comprising: an array of memory cells; a plurality of boundary cells able to manage serial and parallel data; mixed pads connected to the memory cells through low speed paths, the mixed pads being configured to be contacted by probes of a testing machine; high speed pads connected to the boundary cells through high speed paths; a three state multiplexer block connected to the memory cells and to the boundary cells and configured to receive thereto at least a first input signal and a second input signal, the three state multiplexer block being also connected to the mixed pads; ESD networks connected to the mixed pads; an enabling circuit connected to one of the mixed pads, configured to receive an external enabling signal and to provide the three state MUX with an internal enabling signal; wherein the enabling circuit comprises: a tester presence detector circuit connected to the mixed pad; and a logical gate having respective input terminals connected to t

Abstract: A transmission device according to the disclosure includes a driver section that is able to transmit a data signal by using three or more predetermined number of voltage states and set voltages in each of the voltage states; and a control section that sets an emphasis voltage that is based on a transition among the predetermined number of the voltage states, and thereby causes the driver section to perform emphasis.

Abstract: A power conversion device converts power between a direct-current (DC) circuit and an alternating-current (AC) circuit. The power conversion device includes a power converter circuit which includes a plurality of unit converters connected in series, and a controller. The unit converter includes one or more switching elements and a capacitor. The controller transmits, to the unit converter through a first transmission medium, information on a switching command for the unit converter. The unit converter transmits, to the controller through a second transmission medium, information on at least one condition of the unit converter. The first transmission medium is an optical fiber, and the second transmission medium is a wireless communication channel.

Abstract: The present disclosure relates to a data-driving device and a system for driving a display device and, more specifically, a data-driving device and a system for reducing power consumption of a display device by reducing a static current of the data-driving device.

Abstract: Provided a source driver integrated circuit (IC) and a display driving device eliminating an existing input pad and internal wiring of a source driver integrated circuit (IC) for receiving a sensing reference voltage from an external voltage source by allowing the sensing reference voltage for initializing pixels during sensing of the pixels to be generated by an internal voltage source, rather than the external voltage source.

Abstract: A switch driver circuit includes a plurality of pullup transistors. The plurality of pullup transistors includes a first pullup transistor coupled between a voltage supply and a first output node. A plurality of pulldown transistors includes a first pulldown transistor coupled between the first output node and a ground node. A slope control circuit is coupled to the ground node. A plurality of global connection switches includes a first global connection switch coupled between the first output node and the slope control circuit.

Abstract: The present disclosure relates to a driving control circuit, method and device for a gallium nitride (GaN) transistor, and a medium. An ADriver pin and an electronic switch are added to an existing flyback power supply circuit. The electronic switch includes a first terminal connected to the ADriver pin, a second terminal connected between a driving resistor and a GaN transistor, and a third terminal connected between a current detection resistor and a current sense pin. By improving the driving control circuit and the driving control method for the GaN transistor, the present disclosure can effectively prevent the false turn-on problem due to high-frequency oscillation between the leakage inductance of the transformer and the parasitic capacitance after the GaN transistor is turned off, and drives the GaN transistor more reliably.

Abstract: According to an embodiment a semiconductor device includes a semiconductor layer including first trenches and second trenches, a first gate electrode in the first trench, a second gate electrode in the second trench, a first gate electrode pad, a second gate electrode pad, a first wiring connecting the first gate electrode pad and the first gate electrode, and a second wiring connecting the second gate electrode pad and the second gate electrode. The semiconductor layer includes a first connection trench. Two first trenches adjacent to each other are connected to each other at end portions by the first connection trench. At least one of the second trenches is provided between the two first trenches. The second gate electrode in the at least one second trench is electrically connected to the second wiring between the two first trenches.

Abstract: A data storage apparatus is provided to include a memory device including memory cells for storing data; and an interface circuit coupled as an interface between the host device and the memory device and configured to transmit a transmission signal to the host. The interface circuit includes a delay circuit configured to generate a delay code and is configured to generate an additional signal to be combined with the transmission signal based on the delay code.

Abstract: Micro light-emitting diode display driver architectures and pixel structures are described. In an example, a driver circuit for a micro light emitting diode device includes a current mirror. A linearized transconductance amplifier is coupled to the current mirror. The linearized transconductance amplifier is to generate a pulse amplitude modulated current that is provided to a set of micro LEDs connected in parallel to provide fault tolerance architecture.

Abstract: An electronic device may include one or more output buffers each including a pair of final p-channel metal oxide semiconductor (PMOS) and n-channel metal oxide semiconductor (NMOS) transistors, a first pre-buffer to drive the PMOS transistor, and a second pre-buffer to drive the NMOS transistor. Each output buffer receives power from a pre-buffer supply filtering circuit, which may include a supply capacitor for stabilizing supply voltage, a low-pass first pre-buffer supply filter to filter the voltage supplied to the first pre-buffer, and a low-pass second pre-buffer supply filter the voltage supplied to the second pre-buffer.

Abstract: Disclosed is a transmitter which includes a channel driver that includes a pull-up transistor and a pull-down transistor connected between a power node and a ground node and outputs a voltage between the pull-up transistor and the pull-down transistor as a transmit signal, and a pre-driver that controls the pull-up transistor and the pull-down transistor in response to a driving signal and controls the channel driver such that the transmit signal is overshot at a rising edge of the driving signal and the transmit signal is undershot at a falling edge of the driving signal.

Abstract: Various implementations described herein are directed to a device having first circuitry with wordline drivers coupled to wordlines. The device may have second circuitry with switch structures that are coupled between a first voltage and ground. The switch structures may be configured to provide a second voltage to a power connection of each wordline driver based on the first voltage.

Abstract: A method of wireless communication, the method including: identifying a resource block assignment for a non-data uplink resource within a set of resource blocks; determining a first range of resource blocks below the resource block assignment for the non-data uplink resource and identifying a second range of resource blocks above the resource block assignment for the non-data uplink resource; calculating a first bandwidth associated with the first range of resource blocks and calculating a second bandwidth associated with the second range of resource blocks; and configuring a first wireless communication device to work within a discrete bandwidth level sufficient to encompass a larger one of the first bandwidth and the second bandwidth, wherein the discrete bandwidth level is less than a full uplink bandwidth assigned by a network serving the first wireless communication device.

Abstract: Driver circuits to invert an input signal and to generate an output signal based on the inverted input signal are presented. The voltage level of the logical high value of the output signal is adjustable. The driver circuit has a high side switching element coupled between a supply terminal and the output terminal of the driver circuit. The driver circuit has a low side switching element coupled between the output terminal of the driver circuit and a reference potential. The driver circuit has a regulation transistor, wherein a controlled section of the regulation transistor is coupled in series with the high side switching element and the low side switching element between the supply terminal and the reference potential. The driver circuit has a feedback circuit to regulate the output voltage by generating a regulation voltage at a control terminal of the regulation transistor.