Current Driver Patents (Class 327/108)
  • Patent number: 11190171
    Abstract: A Schmitt trigger voltage comparator circuit is provided including a voltage reference input, a current source having a first voltage controlled current source connected to the voltage reference input and a second voltage controlled current source connected to a signal input for converting the signal input to a input current and the voltage reference input to a reference current, a current mirror having an input connected to the output of the first voltage controlled current source configured and arranged to invert the direction of the first current and an output of the current mirror connected to the output of the second voltage controlled current source, and a sequence controller for generating digital signals to control a first plurality of switches and a second plurality of switches. The first plurality of switches control the first and second voltage controlled current sources and the second plurality of switches control the current mirror.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: November 30, 2021
    Assignee: Nexperia B.V.
    Inventors: Walter Luis Tercariol, Maikel Pieter Sturkenboom, Geethanadh Asam
  • Patent number: 11190168
    Abstract: A driver system may include a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: November 30, 2021
    Assignee: Cirrus Logic, Inc.
    Inventors: Jing Bai, Tejasvi Das, Xin Zhao, Lei Zhu, Xiaofan Fei
  • Patent number: 11190173
    Abstract: According to certain aspects, a driver includes an output transistor coupled between a first rail and an output of the driver, a first current source coupled to a gate of the output transistor, a second current source, and a switch, wherein the switch and the second current source are coupled in series between the gate of the output transistor and a second rail. The driver also includes a current sensor configured to generate a sense current based on an output current of the driver, and a reference current source configured to generate a reference current, wherein the current sensor and the reference current source are coupled to a control input of the switch.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: November 30, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Jize Jiang, Kan Li
  • Patent number: 11183992
    Abstract: A signal buffer is disclosed. The signal buffer may include one or more bias signal generators to bias one or more transistors. The bias signal generators may generate power supply compensated or ground compensated bias signals. The bias signal generators may include a capacitor to provide a high frequency signal path.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: November 23, 2021
    Assignee: Xilinx, Inc.
    Inventors: Roswald Francis, Bruno Miguel Vaz
  • Patent number: 11171660
    Abstract: A phase detection circuit is configured to receive an input clock signal and a reference clock signal. The phase detection circuit is configured to generate a divided clock signal from the reference clock signal. The phase detection circuit is configured to generate a phase detection signal after comparing the phase of the input clock signal with the divided clock signal.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: November 9, 2021
    Assignee: SK hynix Inc.
    Inventors: Da In Im, Young Suk Seo
  • Patent number: 11146265
    Abstract: A circuit for regenerative gate charging includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first switch timing profile, and transmits the output control signals to the output control circuit. In accordance with the first switch timing profile, the output control circuit holds switches of the bridged inductor driver in an ON state for a first period and holds all of the switches in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second switch timing profile using the sampled voltages.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: October 12, 2021
    Assignee: Silanna Asia Pte Ltd
    Inventors: Cameron Brown, Yashodhan Vijay Moghe
  • Patent number: 11146262
    Abstract: A reference voltage generator is disclosed. The reference voltage generator may include an operational transconductance amplifier (OTA), a bias generator, a first flipped voltage follower, a bias filter, a control signal filter, and a second flipped voltage follower. The OTA and the first flipped voltage follower may generate a control signal based on a reference voltage and a bias voltage from the bias generator. The bias filter may filter the bias voltage and the control signal filter may filter the control signal. The second flipped voltage follower may generate the output voltage based on the filtered bias voltage and the filtered control signal.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: October 12, 2021
    Assignee: Xilinx, Inc.
    Inventors: Yipeng Wang, Kee Hian Tan
  • Patent number: 11125586
    Abstract: A sensor arrangement has a current mirror structure that is configured to provide respective base currents at each of a plurality of output current paths based on an input current. For each of the output current paths, a respective adjustment current source is provided that is digitally controllable and is connected to the respective output current path for adjusting the base current of said output current path. For each of the output current paths, a current biased sensor element is coupled in said output current path. The sensor arrangement further has a selection element for selectively connecting one of the output current paths to an evaluation block based on a selection signal. The evaluation block is configured to generate a sensing value corresponding to a resulting current in the connected output current path, to compare the sensing value with an average value, and to update the average value based on the sensing value.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: September 21, 2021
    Assignee: AMS AG
    Inventors: Dalibor Kolar, Gerhard Oberhoffner, Simone Sabatelli, Dominik Ruck
  • Patent number: 11126017
    Abstract: A driving circuit includes a plurality of differential amplifier circuits each electrically connected to a power supply line. Each differential amplifier circuit includes a differential pair circuit and a series resistance circuit. In the differential pair circuit, a first transistor and a second transistor are electrically connected to the power supply line through a first load resistor and a second load resistor, respectively. A center node is electrically connected between the first transistor and the second transistor. Each differential amplifier circuit generates a differential output signal in accordance with a differential incoming signal. The series resistance circuit includes a resistor and a line element. The line element includes a signal line which extends straight with a distance between the signal line and a ground line extending in parallel thereto. The resistor and the line element are connected in series between the center node and a static potential line.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: September 21, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Taizo Tatsumi
  • Patent number: 11114432
    Abstract: A semiconductor device includes a voltage input circuit node and a ground voltage node. A first transistor is coupled between the voltage input circuit node and the ground voltage node. A triggering circuit is coupled between the voltage input circuit node and the ground voltage node in parallel with the first transistor. The triggering circuit includes a trigger diode. An output of the triggering circuit is coupled to a control terminal of the first transistor. A load is powered by coupling the load between the voltage input circuit node and the ground voltage node.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: September 7, 2021
    Assignee: Semtech Corporation
    Inventors: Lei Hua, William Allen Russell, Changjun Huang, Bo Liang, Pengcheng Han
  • Patent number: 11114837
    Abstract: A ground overcurrent control system includes ground circuit with a first section and a second section. The first section is electrically connected to a ground member of an electrical connector and the second section is electrically connected to a ground reference. A switch element is positioned between the first section of the ground circuit and the second section of the ground circuit. A controller is configured to determine the current within the ground circuit while current is passing through the switch element and, upon the current exceeding a current threshold, the switch element is modified to an open condition. Upon determining that the voltage between the first section of the ground circuit and the ground reference is less than a voltage threshold, a command is generated to modify the switch element back to a closed condition.
    Type: Grant
    Filed: February 23, 2020
    Date of Patent: September 7, 2021
    Assignee: Molex, LLC
    Inventors: Gregory L. Bella, Jeffrey R. Ciarlette
  • Patent number: 11099594
    Abstract: The disclosed bandgap circuit is configured to provide a temperature stable reference current and/or voltage that is also adjustable. The stability can be facilitated by an improved matching of current mirrors provided by a source degeneration topology. The source degeneration can reduce random mismatches without requiring increased size or complexity of the current mirrors and can facilitate operation of the current mirrors in a weak inversion condition, in which random mismatches may be most severe. Further, the source degeneration may be adjusted to adjust a level and/or a temperature coefficient of the generated reference current and/or voltage.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: August 24, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Moez Kanoun
  • Patent number: 11082039
    Abstract: A GaN power switching device comprises a GaN transistor switch SW_MAIN has an integrated drain voltage sense circuit, which comprises GaN sense transistor SW_SEN and GaN sense resistor RSEN, which at turn-on form a resistive divider for sensing the drain voltage of SW_MAIN to provide a drain voltage sense output VDSEN. Fault detection logic circuitry of a driver circuit generates a fault signal FLT when VDSEN reaches or exceeds a reference voltage Vref, which triggers fast turn-off of the gate of SW_MAIN, e.g. within less than 100 ns of an overcurrent or short circuit condition. During turn-off, RSEN resets VDSEN to zero. For two stage turn-off, the driver circuit further comprises fast soft turn-off circuitry which is triggered first by the fault signal to pull-down the gate voltage to the threshold voltage, followed by a delay before full turn-off of the gate of SW_MAIN by the gate driver.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: August 3, 2021
    Assignee: GaN Systems Inc.
    Inventors: Di Chen, Larry Spaziani
  • Patent number: 11075629
    Abstract: In an embodiment, a digital output driver circuit comprises an output stage having first and second transistors. A drive stage is configured to drive control terminals of the first and second transistors and comprising switching circuitry and current generator circuitry. In a first configuration, the driver circuit is configured to connect a control terminal of the second transistor to the reference node to turn off the second transistor; and connect a first capacitance to the current generator circuitry and to a control terminal of the first transistor to turn on the first transistor. In a second configuration, the driver circuit is configured to turn off the first transistor and connect the control terminal of the second transistor to the current generator circuitry and to the second capacitance to turn on the second transistor.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: July 27, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventor: Andrea Agnes
  • Patent number: 11074954
    Abstract: According to one embodiment, a memory device includes: a first and a second interconnects; a memory cell including a variable resistive element, the memory cell between the first and second interconnects; and a write circuit including a current source circuit and a voltage source circuit, the write circuit writing data to the memory cell by using a write pulse. The write circuit supplies the write pulse to the memory cell by using the current source circuit in a first period from a first time of a start of supply of the write pulse to a second time, and supplies the write pulse to the memory cell by using the voltage source circuit in a second period from a third time to a fourth time of an end of the supply of the write pulse.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: July 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiaki Osada, Kosuke Hatsuda
  • Patent number: 11068429
    Abstract: An oscillation reduction unit for a bus system. The oscillation reduction unit has two transistors, which are situated anti-serially between a first bus wire of a bus of the bus system and a second bus wire of the bus, in which bus system an exclusive, collision-free access of a user station to the bus of the bus system is at least temporarily ensured, and a time control block for switching the two transistors and designed to switch on the two transistors while a signal on the first and/or second bus wire and/or a transmission signal, from which the signals on the first and/or second bus wire are generated, changes from a dominant state to a recessive state, and designed to switch off the two transistors if the signal on the first and/or second bus wire and/or the transmission signal is/are switched into the recessive state.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: July 20, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Cyrille Brando, Axel Pannwitz, Steffen Walker
  • Patent number: 11070203
    Abstract: A driver system may include a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: July 20, 2021
    Assignee: Cirrus Logic, Inc.
    Inventors: Jing Bai, Tejasvi Das, Xin Zhao, Lei Zhu, Xiaofan Fei
  • Patent number: 11061844
    Abstract: The present application relates to a circuit and a transceiver comprising the circuit. The circuit comprises two bus line terminals for coupling to a bus and a bridge circuit comprising two legs. Each leg comprises an adjustable pull resistance and an adjustable push resistance connected in series with a respective one of the two bus line terminals. The adjustable pull resistances and the adjustable push resistances of the bridge circuit enable to independently adjust a driver impedance and to independently adjust a differential driver voltage on the bus. The circuit may further comprise an edge detector is coupled to a transmit data input and configured to detect a transition on the transmit data input and to adjust the impedances of the adjustable pull resistances and the adjustable push resistances in response to the detected transition.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: July 13, 2021
    Assignee: NXP B.V.
    Inventors: Clemens Gerhardus Johannes de Haas, Johannes Petrus Antonius Frambach, Thomas John William Donaldson
  • Patent number: 11038518
    Abstract: Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: June 15, 2021
    Assignee: KANDOU LABS, S.A.
    Inventors: Kiarash Gharibdoust, Armin Tajalli, Pavan Kumar Jampani, Ali Hormati
  • Patent number: 11038499
    Abstract: A drive apparatus that drives a control terminal of a main switching element establishing/cutting off an electrical connection between a first main terminal and a second main terminal is provided, including first to fourth switching elements establishing/cutting off electrical connections between a positive terminal of a power source and the control terminal, the positive terminal and the second main terminal, the control terminal and a negative terminal of the power source, and the second main terminal and the negative terminal, respectively, and a resistance of at least one among a path between the control terminal and the second main terminal via the first to second switching elements, a path via the first and fourth switching elements, a path via the second to third switching elements, and a path via the third to fourth switching element is different from a resistance of at least one of the others.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 15, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Nobuharu Kusakari
  • Patent number: 11012066
    Abstract: A plurality of drive circuits each drive a corresponding one of a plurality of power semiconductor elements connected in parallel. Each of the drive circuits includes a control command unit, a current detector, a differentiator, and an integrator. The current detector detects a gate current that flows into a gate terminal of a corresponding one of the power semiconductor elements after the control command unit outputs a turn-on command. The differentiator performs time differentiation of the gate current detected by the current detector. The integrator performs time integration of the gate current detected by the current detector. Based on a differential value and an integral value in each of the drive circuits, the determination unit determines whether an overcurrent state occurs or not in any of the plurality of power semiconductor elements.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: May 18, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasushige Mukunoki, Takeshi Horiguchi
  • Patent number: 11011985
    Abstract: A voltage reducing circuit comprises a power switch circuit portion comprising a high-side and low-side field-effect-transistors connected at a switch node. The power switch circuit portion has an on-state wherein the high-side transistor is enabled and the low-side transistor is disabled and, vice versa, an off-state. An energy storage circuit portion comprising an inductor connected to the switch node is arranged to provide an output voltage. A drive circuit portion receives a pulse width modulation control signal and outputs pulse width modulated (PWM) drive signals. A pre-biasing circuit portion applies bias voltages to the gate terminals of the high-side and low-side transistors in response to the PWM drive signals, wherein the pre-biasing circuit portion is arranged such that the bias voltage applied to the gate terminal of the currently disabled transistor is set to an intermediate voltage before switching between the on-state and off-state.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: May 18, 2021
    Assignee: Nordic Semiconductor ASA
    Inventor: Samuli Antti Hallikainen
  • Patent number: 11005454
    Abstract: A disclosed pre-driver circuit includes multiple signal generation stages configured to receive different bias voltages from local switching bias circuit(s). In some embodiment, pre-driver circuit has multiple switching bias circuits, each with a bias voltage node connected to a corresponding stage. In other embodiments, the pre-driver circuit has a single switching bias circuit with multiple bias voltage nodes and a multi-input/multi-output multiplexor with inputs connected to the bias voltage nodes and outputs connected to the stages. The switching bias circuit(s) and a primary inverter in each stage all receive the same input signal. When this input signal transitions, the switching bias circuit(s) supply bias voltages to the stages and the primary inverters turn on in sequence and slowly, thereby ensuring that pre-driver signals generated by the different stages transition in sequence and at a relatively slow rate. Once the last pre-driver signal transitions, the switching bias circuit(s) turn off.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: May 11, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Dzung T. Tran, Sushama Davar
  • Patent number: 10998817
    Abstract: Devices and methods are provided for controlling dead-time of a direct current to direct current (DC-DC) converter. A control circuit includes a first transistor having a source/drain terminal coupled to an output voltage of the DC-DC converter configured to provide current based on the output voltage. The control circuit also includes a digital up/down counter having an output terminal electrically coupled to an input terminal of a delay cell of the DC-DC converter. A current sensing circuit of the control circuit is electrically coupled to an input terminal of the digital up/down counter configured to receive the current and drive the digital up/down counter based on the current.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chia-Chun Chang, Alan Roth, Eric Soenen, Tysh-Bin Liu
  • Patent number: 10998712
    Abstract: A power supply control apparatus includes: a semiconductor switching element switched with PWM control; a PWM signal output unit outputting a PWM signal; a current circuit outputting a current related to a current flowing through the semiconductor switching element; a filter circuit converting the current that is output from the current circuit to a voltage; an overcurrent protection circuit turning off the semiconductor switching element based on a voltage value of the voltage filtered by the filter circuit; a voltage detection unit detecting the voltage value of the voltage at a timing near an end of a pulse of a PWM signal; a temperature estimation unit estimating, a temperature of an electric wire through which a current flows that also flows through the semiconductor switching element; and an electric wire protection unit turning off the semiconductor switching element based on the temperature estimated by the temperature estimation unit.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: May 4, 2021
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Shunichi Sawano, Yuuki Sugisawa, Kota Oda, Keisuke Mase
  • Patent number: 10960919
    Abstract: A control device includes an inverter, a first drive unit, a first booster, a second drive unit, and a second booster. The inverter has a plurality of high potential switching elements and a plurality of low potential switching elements, and supplies electric power from a power supply to the motor. The first drive unit controls an operation of the high potential switching elements. The first booster is connected to the first drive unit, boosts the voltage of the power supply, and outputs the boosted voltage to the first drive unit. The second drive unit controls an operation of the low potential switching elements. The second booster is connected to the second drive unit, boosts the voltage of the power supply, and outputs the other boosted voltage to the second drive unit.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: March 30, 2021
    Assignee: DENSO CORPORATION
    Inventor: Takahiro Yamanaka
  • Patent number: 10944410
    Abstract: In accordance with an embodiment, a ring oscillator includes a plurality of stages coupled in a ring configuration, where stage of the plurality of stages has an input node coupled to an output node of a previous stage of the plurality of stages. Each stage of the plurality of stages includes: a ring oscillator transistor having a control node coupled to the input node, and a load path coupled to the output node; a direct injection circuit having a load path coupled between the control node of the ring oscillator transistor and the output node, and a control node coupled to a first oscillator input node; and a tail injection circuit having a load path coupled between the output node and a first power supply node, and a control node coupled to a second oscillator input node.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 9, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Alessandro Garghetti, Luigi Grimaldi, Matteo Bassi, Dmytro Cherniak
  • Patent number: 10938388
    Abstract: According to one embodiment, a control circuit is connected to an element portion including a first element. The first element includes a first gate, a first collector, and a first emitter. The control circuit performs a first operation and a second operation. In at least a portion of the first operation, the control circuit causes a first current to flow from the first collector toward the first emitter. In at least a portion of the second operation, the control circuit causes a second current to flow from the first emitter toward the first collector. A first time constant of a switching of the first element in the first operation is different from a second time constant of a switching of the first element in the second operation.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 2, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tatsunori Sakano, Kazuto Takao
  • Patent number: 10923015
    Abstract: A display device may include a plurality of pixels that may display image data on a display. The display device may also include a circuit that may receive pixel data including a gray level for at least one pixel of the plurality of pixels. The circuit may then receive an emission clock signal using a clock circuit based on the pixel data, such that the emission clock signal may cause the at least one pixel to receive a current for an amount of time based on the gray level. The circuit may then gate off the clock circuit after the amount of time.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: February 16, 2021
    Assignee: Apple Inc.
    Inventors: Derek K. Shaeffer, Hopil Bae, Yafei Bi, Wei H. Yao, Xiaofeng Wang
  • Patent number: 10921769
    Abstract: The description that follows relates to a circuit having galvanic isolation. According to an exemplary embodiment, the circuit has a transmission circuit, coupled to a galvanically isolating device, that is designed to transmit a first signal via the galvanically isolating device. The circuit further has a first receiver circuit, coupled to the galvanically isolating device, that is designed to receive the transmitted first signal from the galvanically isolating device. A second receiver circuit coupled to the galvanically isolating device is designed to receive the transmitted first signal from the galvanically isolating device and to take the received first signal as a basis for generating a wake-up signal.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: February 16, 2021
    Assignee: Infineon Technologies AG
    Inventor: Thorsten Hinderer
  • Patent number: 10917008
    Abstract: An output stage circuit of a power conversion circuit includes a first power switch, a driving circuit, a first current source, a second current source and a combining circuit. The first power switch is coupled to a second terminal of a bootstrap capacitor. The driving circuit is coupled to the first terminal of the bootstrap capacitor and the first power switch and provides a control signal to the first power switch. The first current source generates a first current according to the control signal. The second current source generates a second current according to a reference voltage which is a first voltage at the first terminal or a second voltage at the second terminal. The combining circuit, coupled to the driving circuit, the first current source and the second current source, generates a switch operation indicating signal to the driving circuit according to the first current and second current.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: February 9, 2021
    Assignee: UPI SEMICONDUCTOR CORP.
    Inventors: Chih-Wen Hsiao, Chien-Ming Chen
  • Patent number: 10910946
    Abstract: An apparatus has a comparator circuitry (e.g., auto-zero comparator) with a first input, a second input, a third input; and an output; a first device (e.g., a low-side switch) coupled to the first and second inputs of the comparator; and a circuitry (e.g., a self-tuning logic) to generate a digital code which represents a comparator offset adjustment with reference to detection of current through a second device (e.g., an inductor), wherein the digital code (e.g., a multibit digital signal) is provided to the third input of the comparator circuitry.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventor: Christopher Schaef
  • Patent number: 10909435
    Abstract: The purpose of the present invention is to provide an apparatus for managing baggage and a method for managing baggage with which improved usability can be obtained. In order to solve the problem, an apparatus for managing baggage is provided with: a reader unit which reads tag information of a wireless tag attached to a baggage; a storage unit in which the tag information read by the reader unit is stored; and a control unit which makes a determination of a forgotten baggage by comparing the tag information stored in the storage unit with tag information newly read by the reader unit.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: February 2, 2021
    Assignee: MAXELL, LTD.
    Inventors: Motoyuki Suzuki, Kazuhiko Yoshizawa, Yasunobu Hashimoto, Shigetaka Kimura, Shinji Shibuya
  • Patent number: 10903825
    Abstract: A phase correction circuit, a phase correction method and an electric energy metering device are provided. The phase correction circuit includes a reference voltage circuit and a current correction circuit. The reference voltage circuit includes a first predetermined number of first delay D flip-flops and a first synchronization D flip-flop. The current correction circuit includes a second predetermined number of second delay D flip-flops, a second synchronization D flip-flop and a data selector. The data selector outputs a current signal of one of the second delay D flip-flops to the second synchronization D flip-flop. The second predetermined number is greater than or equal to the first predetermined number. In a case that the second predetermined number is equal to the first predetermined number, each of the second predetermined number and the first predetermined number is greater than 1.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: January 26, 2021
    Assignee: HANGZHOU VANGO TECHNOLOGIES, INC.
    Inventors: Boqiang Wu, Nick Nianxiong Tan, Changyou Men
  • Patent number: 10886692
    Abstract: The present invention relates to telecommunication techniques and integrated circuit (IC) devices. In a specific embodiment, the present invention provides a laser deriver apparatus that includes a main DAC section and a mini DAC section. The main DAC section processes input signal received from a pre-driver array and generates an intermediate output signal. The mini DAC section provides a compensation signal to reduce distortion of the intermediate output signal. The intermediate output signal is coupled to output terminals through a cascode section and/or a T-coil section. There are other embodiments as well.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: January 5, 2021
    Assignee: INPHI CORPORATION
    Inventors: Karim Abdelhalim, Jorge Pernillo, Halil Cirit, Michael Le
  • Patent number: 10885870
    Abstract: An electronic device includes; a timing controller that generates a command to-be-sent to a display driver integrated circuit (DDI) selected from among a plurality of display driver integrated circuits (DDIs) connected to the timing controller through data lines and a shared channel The DDI is selected by a DDI control signal transferred from the timing controller to the DDI through a corresponding data line among the data lines, and the command is transferred from the timing controller to the DDI through the shared channel.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: January 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyongho Kim, Jinho Kim, Jaeyoul Lee, Hyunwook Lim, Youngmin Choi
  • Patent number: 10886917
    Abstract: The present invention concerns a circuit for converting a first control signal referenced to a first potential into a second signal referenced to a second variable potential, including: a first transistor between a first terminal for supplying said second signal and a second terminal at said second variable potential; and at least one first branch including, in series between a gate of the first transistor and a third terminal at said first potential, a second transistor, a first resistive element, and a third transistor, a gate of the third transistor being intended to receive the first signal and a gate of the second transistor being coupled to the second terminal, the gate of the second transistor being further coupled, by a first clipping element, to its source.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: January 5, 2021
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Dominique Bergogne
  • Patent number: 10886904
    Abstract: Certain aspects of the present disclosure generally relate to a power stage. The power stage generally includes a first transistor, a second transistor having a drain coupled to a drain of the first transistor, a first gate drive circuit coupled between an input node of the power stage and a gate of the first transistor, and a second gate drive circuit having a first signal path coupled between the input node and a gate of the second transistor. In certain aspects, the second gate drive circuit comprises a plurality of buffers in the first signal path, and a plurality of electronic devices coupled to the plurality of buffers and configured to apply a delay associated with driving the gate of the second transistor to track a delay associated with driving the gate of the first transistor via the first gate drive circuit.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: January 5, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Qubo Zhou, Yan Wang
  • Patent number: 10879894
    Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: December 29, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Daniele Zella, Vanni Poletto, Mauro Foppiani
  • Patent number: 10879888
    Abstract: The invention relates to a method for actuating at least one semiconductor switch, in particular in a component of a motor vehicle. The at least one semiconductor switch can be switched with a control voltage (1) according to the following method steps: a1) specifying the control voltage (1) in a tolerance range (2) and a2) monitoring whether a control voltage (1) actually being applied to the at least one semiconductor switch exceeds at least one threshold (4, 5), wherein at least the following method step is carried out at at least one control time: b1) ascertaining a difference between the control voltage (1) actually being applied to the at least one semiconductor switch and the at least one threshold, the control voltage (1) specified according to step a1) being manipulated according to the at least one control time using the result from step b1).
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: December 29, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Rostislav Rogov, Thorsten Baumhoefer
  • Patent number: 10868521
    Abstract: Apparatus, devices, and systems to provide a low quiescent current load switch are disclosed. A disclosed load switch circuit includes a transconductor to convert a voltage to a current input to a transistor gate, the current input to the transistor gate to control the gate to deliver power to a load from a power supply. The example circuit includes a resistor to provide power from a charge pump to the gate as controlled by the transconductor. A disclosed apparatus includes a driver to control a gate of a transistor, the gate to enable the transistor to deliver power to a load from a power supply when the gate is activated, and a gate slope control to control a rate of change over time of a voltage associated with the gate to activate the gate and to disable the driver when the gate is activated.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: December 15, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jae Won Choi, Sungho Beck, Abidur Rahman
  • Patent number: 10868531
    Abstract: A signal-multiplexing device according to the present embodiment has a structure that is capable of satisfactorily handling an increase in a data rate. The signal-multiplexing device includes M pre-stage buffers and an output buffer. An m-th pre-stage buffer Bm outputs an m-th input signal when the signal levels of both an m-th control signal Cm and an n-th control signal Cn of M control signals are significant, and the m-th pre-stage buffer Bm enters into a high-impedance state when the signal level of at least one of the m-th control signal Cm and the n-th control signal Cn is non-significant. The output buffer Bout sequentially outputs input signals that have been respectively outputted from the M pre-stage buffers at different timings.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: December 15, 2020
    Assignee: THINE ELECTRONICS, INC.
    Inventor: Yusuke Fujita
  • Patent number: 10868946
    Abstract: An actuator includes a magnet, a driving coil, a driver, and a position detector. The magnet is disposed on one surface of a lens barrel. The driving coil is disposed at a proximity of the magnet. The driver is configured to apply a driving signal to the driving coil to move the lens barrel along an optical axis. The position detector is configured to generate an oscillation signal of which a frequency is changed based on movement of the magnet and configured to compare oscillation signals generated in a first position and a second position of the lens barrel to detect a present position of the lens barrel.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: December 15, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong Woo Lee, Joo Hyoung Lee, Je Hyuk Ryu, Woo Young Choi, Yong Woon Ji, Soo Woong Lee, Byung Joo Hong, Joo Yul Ko
  • Patent number: 10854588
    Abstract: A semiconductor device includes a normally-on junction FET having a first gate electrode, a first source electrode and a first drain electrode, a normally-off MOSFET having a second gate electrode, a second source electrode and a second drain electrode, and a voltage applying unit which applies a voltage to the first gate electrode. The first source electrode of the junction FET is electrically connected to the second drain electrode of the MOSFET, and the junction FET is thus connected to the MOSFET in series, and the voltage applying unit applies a second voltage with a polarity opposite to that of a first voltage applied to the first gate electrode when the junction FET is brought into an off-state, to the first gate electrode when the MOSFET is in an on-state.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: December 1, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hisashi Toyoda, Koichi Yamazaki, Koichi Arai, Tatsuhiro Seki
  • Patent number: 10855264
    Abstract: A circuit for generating differential reference voltages, a circuit for detecting a signal peak, and an electronic device. In the circuit for generating reference voltages, a common-mode extraction circuit receives a first differential signal and a second differential signal, extracts a common-mode level from the first differential signal and the second differential signal, and applies the common-mode level to a non-inverting input terminal of a first operational amplifier. The first operational amplifier, a main control switch, a first voltage dividing resistor, a second voltage dividing resistor, and a first direct current power source constitute a feedback loop, to generate differential reference voltages matching with the common-mode level. Adjusting a current provided by the first direct current power source can change the differential reference voltages, obtaining a reference for to-be-detected amplitude of the signals.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: December 1, 2020
    Assignee: LONTIUM SEMICONDUCTOR CORPORATION
    Inventors: Cheng Tao, Xiangyu Ji, Yu Chen, Jiaxi Fu, Haiyan Wei
  • Patent number: 10855267
    Abstract: An electronic switch includes a first NMOS transistor connected between a positive input terminal and an output terminal; a first diode, a second resistor, a first capacitor, and a third switching element sequentially connected in series between a drain of the first NMOS transistor and a negative input terminal; a first resistor connected between a positive input terminal and a node between the first capacitor and the third switching element; a third resistor connected between a gate of the first NMOS transistor and a node between the second resistor and the first capacitor; and a second capacitor, a second diode, and a fourth resistor connected in parallel between a source of the first NMOS transistor and a node between the third resistor and the gate of the first NMOS transistor.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: December 1, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Long Ning, Gang Li
  • Patent number: 10848148
    Abstract: An electronic circuit includes a first switch driver, a second switch driver, and a switch node coupled to the first and second switch drivers, and configured to couple to a motor. The electronic circuit also includes slew rate measurement circuitry coupled to the switch node and configured to measure a slew rate of switching operations at the switch node. The electronic circuit also includes a controller coupled to the first switch driver, to the second switch driver, and to the slew rate measurement circuitry, and configured to compare a measured slew rate provided by the slew rate measurement circuitry with a target slew rate, and to selectively adjust control signals to at least one of the first and second switch drivers based on a comparison result. The first and second switch drivers are configured to drive switches to power the motor based on the control signals.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: November 24, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Michael Edwin Butenhoff, Rakesh Raja, Nicholas James Oborny
  • Patent number: 10841071
    Abstract: A data communication system, including master-side and slave-side data communication apparatuses configured to perform bidirectional communication with each other via a single-wire communication line. The master-side data communication apparatus includes first and second transistors performing switching according respectively to an input clock and write data, and a master-side data reproduction circuit reproducing read data transmitted from the slave-side. The slave-side data communication apparatus includes a clock reproduction circuit and a slave-side data reproduction circuit configured to respectively reproduce the input clock and the write data transmitted from the master-side, and a third transistor performing switching both according to the input clock reproduced by the clock reproduction circuit and according to the read data.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: November 17, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masashi Akahane
  • Patent number: 10833894
    Abstract: The present disclosure provides a hybrid-mode laser drive circuit and an optical emitting system. An equalizer circuit is configured to generate, according to a data signal and a clock signal, an equalization signal for compensating a hybrid-mode laser drive circuit; the hybrid-mode laser drive circuit is connected to an output end of the equalizer circuit, and is configured to generate a corresponding drive signal according to an output signal of the equalizer circuit, so as to drive a light emitting diode to generate a corresponding optical signal; a third current source is connected between a power supply voltage and an output end of the hybrid-mode laser drive circuit; an anode of the light emitting diode is connected to the output end of the hybrid-mode laser drive circuit and a cathode of the light emitting diode is connected to a power supply ground.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: November 10, 2020
    Assignee: PhotonIC Technologies (Shanghai) Co., Ltd.
    Inventors: Shang Hu, Tingyu Yao, Rui Bai, Xuefeng Chen, Pei Jiang
  • Patent number: 10826484
    Abstract: A waveform conversion circuit for converting a control signal of a control node ranging from a high voltage level to a low voltage level of a reference node into a driving signal of a first node is provided. The waveform conversion circuit includes a first resistor, a unidirectional conducting device, and a voltage clamp unit. The first resistor is coupled between the control node and the first node. The unidirectional conducting device unidirectionally discharges the first node to the control node. The voltage clamp unit is coupled between the first node and the reference node and is configured to clamp a driving signal.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: November 3, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-I Hu, Po-Chin Chuang