Current Driver Patents (Class 327/108)
  • Patent number: 10811081
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for charging memory data lines when a high charge level is to be written to a memory. The apparatus may include a write amplifier that includes one or more additional pull-up drivers for charging the memory data lines. Control logic may control when additional pull-up drivers are activated. Control logic may control when main data lines are coupled to shared data lines. Methods for charging memory data lines may include providing control signals that indicate which main data lines are coupled to shared data lines and when a write command is received. Methods may include providing a signal that is indicative of the data to be written. The control signals and signal indicative of the data to be written may be used to activate one or more pull-up drivers to charge one or more data lines.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shinichi Takayama, Ken Saito
  • Patent number: 10802997
    Abstract: A semiconductor integrated circuit operates with a voltage supplied from a first power supply IC to transmit and receive data to and from an external memory. The semiconductor integrated circuit includes: an interface circuit operating with a voltage supplied from a second power supply IC and accessing the external memory to transmit and receive data to and from the external memory; a determination circuit which determines, based on a result of the access by the interface circuit, an AC timing specification between the external memory and the interface circuit to generate control information for controlling an output voltage of the second power supply IC in accordance with the AC timing specification; and a voltage control circuit which controls the output voltage of the second power supply IC in accordance with the control information.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: October 13, 2020
    Assignee: SOCIONEXT INC.
    Inventors: Hironori Kubo, Norihiko Mizobata, Makoto Hirano, Akihiro Suzuki, Masahiro Takeuchi
  • Patent number: 10804894
    Abstract: According to one embodiment, a semiconductor device includes an output reset circuit. The output reset circuit including: a first circuit configured to monitor a power-supply voltage and generate a reset signal; a logic circuit configured to control a logic level of an output signal in accordance with the reset signal; a second circuit configured to generate a current in accordance with the power-supply voltage and the reset signal; a third circuit configured to generate a control signal in accordance with the current and the reset signal; and a fourth circuit configured to control the output signal in accordance with the control signal.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: October 13, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Junichi Todaka
  • Patent number: 10797586
    Abstract: A power module included a plurality of normally-on semiconductor switches based on a wide bandgap substrate, the normally-on semiconductor switches connected in parallel; and a balancing unit including a capacitor and a balancing semiconductor switch connected in series, which are connected in parallel to the normally-on semiconductor switches.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: October 6, 2020
    Assignee: ABB Schweiz AG
    Inventors: Uwe Drofenik, Francisco Canales, Chunlei Liu, Franziska Brem
  • Patent number: 10784849
    Abstract: An energy storage element control circuit includes a charge transistor having a first node adapted to be coupled to an output node of the energy storage element control circuit and a second node adapted to be coupled to a terminal of an energy storage element. The energy storage control circuit also includes a boot capacitor having a first node and a second node. The energy storage element further includes a comparator that includes a first input node coupled to the first node of the charge transistor and a second input node adapted to be coupled to the terminal of the energy storage element. The comparator also includes an output node.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 22, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Bradford Lawrence Hunter, Kenneth J. Maggio, Christopher Lee Betty
  • Patent number: 10784859
    Abstract: A gate drive circuit for generating asymmetric drive voltages comprises a gate drive transformer comprising: a primary winding responsive to a pulse width module (PWM) input signal to generate a bipolar signal having a positive bias voltage and a negative bias voltage; and a secondary winding responsive to the bipolar signal to generate a PWM output signal. A first charge pump is connected to the secondary winding responsive to the PWM output signal to generate a level shifted PWM output signal. A second charge pump is connected to the secondary winding to generate a readjusted PWM output signal by decreasing at least a portion of the level shifted PWM output signal. A gate switching device is connected to the first charge pump and second charge pump. A level shifted PWM output signal establishes an ON condition and the readjusted PWM output signal establishes an OFF condition of the gate MOSFET.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: September 22, 2020
    Assignee: Raytheon Company
    Inventors: Sriram Chandrasekaran, Michael S. Hockema
  • Patent number: 10778404
    Abstract: A Serializer/Deserializer (SERDES) circuit is disclosed. The circuit includes an input/output (I/O) pad for coupling to a dual duplex SerDes link. A transmit circuit is coupled to the I/O pad, and includes transmit rate selection circuitry to select between data transmission at a full rate or a sub-rate. A receive circuit is coupled to the I/O pad, and includes receive rate selection circuitry to select between data receipt at the full rate or the sub-rate. Data transmitted by the transmit circuit is at a data rate different than data received by the receive circuit.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: September 15, 2020
    Assignee: Marvell Asia Pte., LTD
    Inventor: Ramin Farjadrad
  • Patent number: 10778218
    Abstract: A gate drive circuit for generating asymmetric drive voltages comprises a gate drive transformer comprising: a primary winding responsive to a pulse width module (PWM) input signal to generate a bipolar signal having a positive bias voltage and a negative bias voltage; and a secondary winding responsive to the bipolar signal to generate a PWM output signal. A first charge pump is connected to the secondary winding responsive to the PWM output signal to generate a level shifted PWM output signal. A second charge pump is connected to the secondary winding to generate a readjusted PWM output signal by decreasing at least a portion of the level shifted PWM output signal. A gate switching device is connected to the first charge pump and second charge pump. A level shifted PWM output signal establishes an ON condition and the readjusted PWM output signal establishes an OFF condition of the gate MOSFET.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: September 15, 2020
    Assignee: Raytheon Company
    Inventors: Sriram Chandrasekaran, Michael S. Hockema
  • Patent number: 10775816
    Abstract: In one embodiment, a control circuit for a high side driver controls a store mode and a maintain mode. An embodiment of the control circuit stores a voltage that is greater than an input voltage which results in storing a large charge for at least a portion of one of the cycles. The charge is used to supply operating voltage to the driver for at least a portion of another of the cycles.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: September 15, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atsuhiro Ichikawa, Keita Ikai
  • Patent number: 10778220
    Abstract: A data output buffer includes a pull-up main driver outputting output data having a high level through an output pad by performing an emphasis operation according to input data, a pull-down main driver outputting the output data having a low level through the output terminal according to the input data, an active inductor controller selectively outputting an inductor activating voltage by detecting a rising or falling period of the input data, and an active inductor selectively performing a de-emphasis operation on the output terminal in response to the inductor activating voltage.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventors: Jin Ha Hwang, Keun Seon Ahn
  • Patent number: 10778208
    Abstract: A circuit includes a first transistor and a second transistor having respective control terminals coupled to receive first and second bias voltages. A first electronic switch is coupled in series with, and between current paths of the first and second transistors to provide an output current line between a circuit output node and ground. A second electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between a bias node and a charge transfer node in the output current line. A third electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between the charge transfer node and the control terminal of the second transistor.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: September 15, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Zamprogno, Alireza Tajfar
  • Patent number: 10769992
    Abstract: The present application discloses a display panel and a display device. The display panel comprises a plurality of data signal lines; a plurality of scan signal lines intersecting with the plurality of data signal lines, to define a plurality of sub-pixels in an array, and each of the sub-pixels comprising a pixel driving circuit, and an external compensation circuit, comprising a power supply unit, a sampling unit and a data signal generation unit, being connected to the data signal lines, and transmitting a compensated data signal via the data signal lines to the pixel driving circuits. In the present implementation, voltage compensation is performed by the external compensation circuit on the driving transistor and the organic light emitting diode in the pixel driving circuit, to improve the driving capability of the pixel driving circuit and increases the display precision of the display panel.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: September 8, 2020
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventors: Yue Li, Dongxu Xiang, Gang Liu
  • Patent number: 10771296
    Abstract: A method uses a controlled oscillator to output an oscillation signal in accordance with a control signal. The method operates by using a first divide-by-1.5 circuit to convert the oscillation signal into a first divided-down signal, using a second divide-by-1.5 circuit to convert the first divided-down signal into a second divided-down signal, using a divide-by-2 circuit to convert the second divided-down signal into a LO (local oscillator) signal, using a modulator to modulate the LO signal into a RF (radio frequency) signal in accordance with a baseband signal, and using a controller to establish the control signal in accordance with a relative timing between a reference signal and the oscillation signal.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: September 8, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10771050
    Abstract: A gate driving circuit that drives a gate of a main switching device is provided, where the gate driving circuit includes: a first resistor connected between a first potential and the gate of the main switching device; a second resistor connected between a second potential being lower than the first potential and the gate of the main switching device; a first switching device connected in series with the first resistor between the first potential and the gate of the main switching device; a second switching device connected in series with the second resistor between the second potential and the gate of the main switching device; and a control circuit that changes at least one resistance value of a resistance value of the first resistor and a resistance value of the second resistor according to a length of an ON period during which the main switching device is turned on.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: September 8, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hirotoshi Kaneda
  • Patent number: 10755750
    Abstract: Disclosed is an improved load switch driver for Power Management Integrated Circuit (PMIC) devices. In one embodiment, a PMIC is disclosed comprising a gate driver, the gate driver connected to the gate of a switch; an operation frequency generator connected to the gate driver and configured to supply a periodic voltage to the gate driver; and a voltage sensor, the voltage sensor connected to the operation frequency generator and the source of the switch, the voltage sensor configured to monitor a drain-source voltage of the switch and lower the frequency of the operation frequency generator to a second frequency in response to detecting a collapse of the drain-source voltage.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Matthew David Rowley
  • Patent number: 10742207
    Abstract: Provided is a switch drive circuit that drives a plurality of switches mutually connected in parallel including a charge unit allowing charge current to flow to the gate of the switch; an off switch connecting between the gate of the switch and the ground; a detection unit detecting whether charge state of the gate of the switch is in a predetermined state; and a changeover unit that changes a state of off switches when the charge units allow the charge current to flow to the gate. The changeover unit changes the state of the off switches to be ON when detection units do not detect the charge state of the gate being in the predetermined state, and to change the state of the off switches to be OFF when detection units detect the charge state of the gate being in the predetermined state.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: August 11, 2020
    Assignee: DENSO CORPORATION
    Inventor: Akifumi Araragi
  • Patent number: 10742168
    Abstract: An output circuit includes first and second nodes, a regulator, a pre-driver, and an output driver. The regulator outputs a second voltage to the second node based on a first voltage applied to the first node. The output driver receives a signal from the pre-driver and outputs a second signal. The regulator short-circuits the first and second nodes while the pre-driver is in a standby state, and controls the second voltage to be different from the first voltage after the pre-driver transitions from the standby state to a normal operation state.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: August 11, 2020
    Assignee: Seiko Epson Corporation
    Inventor: Minoru Kozaki
  • Patent number: 10742209
    Abstract: Methods and circuitry for driving a device are disclosed. An example of the circuitry includes a voltage sensing circuit coupled to an input of a transistor, the voltage sensing circuit having a first output at a node, the voltage sensing circuit comprising a capacitive voltage divider, and a current sensing circuit coupled to the input of the transistor and to the voltage sensing circuit, the current sensing circuit having a second output, the current sensing circuit comprising a resistive divider coupled to the input of the transistor.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: August 11, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Olivier Trescases, Johan Tjeerd Strydom, Rajarshi Mukhopadhyay
  • Patent number: 10734892
    Abstract: A level shifter causes a switch to open or close by selecting one of two stored logical values to generate a gate-drive voltage to cause a transition in the switch.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: August 4, 2020
    Assignee: pSemi Corporation
    Inventor: Gregory Szczeszynski
  • Patent number: 10734989
    Abstract: According to one embodiment, an electronic circuit includes a plurality of first transistors, a control circuit, a sample hold circuit and a calculation circuit. The control circuit selectively performs a first operation and a second operation, the first operation supplying a driving control signal to a gate terminal of a semiconductor switching element using the plurality of first transistors, and the second operation supplying a pulse current for measurement to the gate terminal using part of the plurality of first transistors. The sample hold circuit samples a voltage of the gate terminal during a period in which the pulse current is supplied to the gate terminal in the second operation. The calculation circuit calculates a gate resistance of the semiconductor switching element based on the sampled voltage.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: August 4, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Shusuke Kawai
  • Patent number: 10734976
    Abstract: A driving circuit for driving a power switch. The driving circuit and the power switch are collaboratively defined as an equivalent circuit. The equivalent circuit includes a first equivalent capacitor corresponding to an input capacitor of the power switch, an equivalent inductor, and a second equivalent capacitor corresponding to a parasitic parameter of at least one driving switch. In the charging procedure or the discharging of the first equivalent capacitor, a change amount of charges in the first equivalent capacitor while a voltage of the input capacitor is changed from a voltage corresponding to no inductor current to a set voltage is larger than or equal to a change amount of charges in the second equivalent capacitor while the voltage of the input capacitor is changed from the voltage corresponding to no inductor current to a steady voltage.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 4, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Peiqing Hu, Jianhong Zeng, Haoyi Ye
  • Patent number: 10735000
    Abstract: A disclosed pre-driver includes multiple signal generation stages and a switching bias circuit with a first switch and a second switch. The first switch and primary inverters in each of the stages all receive the same input signal. When the input signal transitions, the first switch turns on the bias circuit to supply a bias voltage to each of the stages. However, the primary inverters do not concurrently turn on. Instead, due to the bias voltage and some additional circuitry within each stage, the primary inverters turn on in sequence and slowly, thereby ensuring that pre-driver signals generated and output by the different stages, respectively, transition in sequence and at a relatively slow rate. Once the last pre-driver signal transitions, the second switch turns off the switching bias circuit. Optionally, a selected one of multiple bias voltages could be used in order to tune delay and transition times.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 4, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Dzung T. Tran, Sushama Davar
  • Patent number: 10729311
    Abstract: A signal processing system includes: a transmission channel; a common-mode signal transmitting circuit configured to output an uplink signal to the transmission channel in a common mode; a common-mode signal detecting circuit configured to detect a common-mode signal from the uplink signal transmitted by the transmission channel; a downlink reference clock signal generating circuit configured to generate a downlink reference clock signal at a second frequency with reference to the first clock edge of the common-mode signal detected by the common-mode signal detecting circuit; a downlink data generating circuit configured to generate downlink data; a differential signal transmitting circuit configured to output, as a downlink signal, the downlink data generated by the downlink data generating circuit to the transmission channel in a differential mode; and a differential signal receiving circuit configured to extract a differential signal from the downlink signal.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: August 4, 2020
    Assignee: OLYMPUS CORPORATION
    Inventor: Masato Osawa
  • Patent number: 10727833
    Abstract: A hybrid output data path is provided that supports high-voltage signaling and low-voltage signaling. The high-voltage signaling is powered by a high-power supply voltage that is greater than a low-power supply voltage that powers the low-voltage signaling.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: July 28, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Young Uk Yim, Jacob Schneider, Satish Krishnamoorthy, Ashwin Sethuram, Chang Ki Kwon, Mostafa Naguib Abdulla
  • Patent number: 10727828
    Abstract: The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 28, 2020
    Assignee: ANALOG DEVICES, INC.
    Inventor: Lawrence A. Singer
  • Patent number: 10720922
    Abstract: According to one embodiment, a semiconductor device includes: a boost circuit configured to apply a first voltage to a gate terminal; a first switching element, a first resistor, and a second resistor that are coupled in parallel between the gate terminal and a source terminal; a second switching element coupled in series with the second resistor between the gate terminal and the source terminal; a switching element control circuit configured to switch, in response to a change of a voltage from the first voltage applied from the boost circuit to the gate terminal to being indeterminate, the first switching element to on state after switching the second switching element to on state. A resistance value of the second resistor is smaller than a resistance value of the first resistor.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: July 21, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventor: Junichi Chisaka
  • Patent number: 10720108
    Abstract: An organic light emitting display device may include a display panel, a power supply, and a display driver. The display panel may comprise a plurality of scan lines, a plurality of data lines, and a plurality of pixels connected to the scan lines and to the data lines. The power supply may supply a first pixel voltage and a second pixel voltage to the pixels. The display driver may control the display panel. The display panel may display a first image in a first frame frequency during a first driving mode, and display a second image in a second frame frequency that is lower than the first frame frequency during a second driving mode, according to a control by the display driver.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: July 21, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jin Jeon
  • Patent number: 10715138
    Abstract: An open drain driver circuit includes an output terminal, an input terminal, a first transistor, a second transistor, and a third transistor. The first transistor includes a first terminal coupled to the output terminal, and a second terminal coupled to a reference voltage source. The second transistor includes a first terminal coupled to a third terminal of the first transistor, a second terminal coupled to a power supply rail, and a third terminal coupled to the reference voltage source. The third transistor includes a first terminal coupled to the input terminal, a second terminal coupled to the reference voltage source, and a third terminal coupled to the third terminal of the first transistor.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: July 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Junfeng Jiang
  • Patent number: 10715134
    Abstract: A power module which includes a power semiconductor chip that includes an IGBT and a freewheeling diode formed in the same chip, and the power module includes a drive circuit that is connected to the power semiconductor chip and drives the IGBT on/off. The power module is configured by packaging the power semiconductor chip and the drive circuit, and is characterized by further including a capacitor and a switch element disposed in series between the emitter of the IGBT and the ground of the drive circuit. The switch element connects the emitter and the ground in the case where the drive circuit has the IGBT perform a turn off switching operation.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: July 14, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shigeki Sato
  • Patent number: 10715129
    Abstract: A switching element driving device includes a main on switch that is connected to gates of a first and second IGBTs and that, when brought into a conductive state, turns on the first and second IGBTs, diodes each disposed between the main on switch and one of the gates of the first and second IGBTs, the diodes having a forward direction from the main on switch to the gates of the first and second IGBTs, an on sub-switch that is connected to the gate of the second IGBT and that, when brought into the conductive state, turns on the second IGBT, and a control circuit that controls the conductive state and a non-conductive state of the main on switch and the on sub-switch.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: July 14, 2020
    Assignee: DENSO CORPORATION
    Inventor: Akifumi Araragi
  • Patent number: 10715057
    Abstract: The invention relates to a method for operating a current converter, in particular of an electric machine, in which, for the or for each semiconductor switch of the current converter, a control signal (P?) for setting a switch-off speed (Anew) is generated, wherein an electric intermediate circuit voltage (Udc) of an intermediate circuit is measured and compared to a voltage threshold value (Uthresh), wherein an operating temperature (TB) of the respective semiconductor switch is measured and compared to a temperature threshold value (Tthresh), wherein a load current (Ic) switched by means of the respective semiconductor switch is measured and compared to a current threshold value (Ithresh), and wherein the control signal (P?) for setting the switch-off speed (Anew) is generated on the basis of the comparisons.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: July 14, 2020
    Assignee: VALEO SIEMENS EAUTOMOTIVE GERMANY GMBH
    Inventors: Qiong Gu, Holger Hoffmann, Thomas Slavik
  • Patent number: 10704988
    Abstract: A measurement system includes a signal bus, an electronic control unit, and an emulated sensor. The electronic control unit is coupled to the signal bus. The sensor with emulated line adaptation is also coupled to the signal bus. The emulated sensor is configured to adapt current consumption according to a selected impedance and a selected frequency range.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: July 7, 2020
    Assignee: Infineon Technologies AG
    Inventor: Dirk Hammerschmidt
  • Patent number: 10707867
    Abstract: A driver includes an open drain output transistor, a capacitor, a first current source, and first and second transistors. Upon assertion of a transmit signal to turn on the first transistor, a controller asserts a second control signal to turn on the second transistor responsive to a voltage of the capacitor being less than a threshold voltage of the open drain output transistor to thereby increase the gate voltage for the open drain output transistor at a first time rate. The controller deasserts the second control signal to turn off the second transistor responsive to the capacitor voltage exceeding the threshold voltage. Responsive to the capacitor's voltage exceeding the threshold, the first current source charges the capacitor to further increase the gate voltage at a second time rate that is smaller than the first time rate.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: July 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Deep Banerjee, Lokesh Kumar Gupta, Somshubhra Paul
  • Patent number: 10700684
    Abstract: A level translator translates signals between first and second voltage domains. An output buffer thereof includes a plurality of PFETs coupled in parallel between a second domain's output supply voltage and an output signal and a plurality of NFETs coupled in parallel between the output signal and the ground rail. Each gate of the plurality of PFETs is coupled to a respective first resistor; the first resistors are coupled in series and receive a first gate control signal. Each gate of the plurality of NFETs is coupled to a respective second resistor; the second resistors are coupled in series and receive a second gate control signal. A first booster NFET is coupled between the output supply voltage and the output signal and a second booster NFET is coupled between the output signal and the ground rail. The booster NFETs receive control signals that operate in the first voltage domain.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: June 30, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Amar Kanteti, Ankur Kumar Singh
  • Patent number: 10700681
    Abstract: Power electronics circuitry includes a pair of parallel switching elements. Each of the switching elements includes two power terminals, two control terminals, and an additional terminal. Corresponding ones of the two power terminals from each of the pair are connected via respective first and second power paths. Corresponding ones of the two control terminals from each of the pair are connected via respective first and second control paths. The additional terminals are connected via an additional path. The circuitry also includes a gate driver tapping the first and second control paths, and a magnet surrounding the additional terminals to couple inductance of the additional path.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: June 30, 2020
    Assignee: Ford Global Technologies, LLC
    Inventors: Fan Xu, Lihua Chen
  • Patent number: 10700652
    Abstract: Some aspects of the disclosure provide for a circuit. In an example, the circuit includes an amplifier, a first transistor network, a second transistor network, a first resistor, a second resistor, and a third resistor. The amplifier has first and second inputs and first, second, third, and fourth outputs. The first transistor network is coupled to the first output of the amplifier and the second output of the amplifier. The second transistor network is coupled to the third output of the amplifier and the fourth output of the amplifier. The first resistor is coupled between the first transistor network and the second transistor network. The second resistor is coupled between the first transistor network and the first input of the amplifier. The third resistor is coupled between the second transistor network and the second input of the amplifier.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: June 30, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vikram Sharma, Gokul Koraganji
  • Patent number: 10687399
    Abstract: Provided is a constant current drive circuit that can improve accuracy of a stop timing of quick charge and prevent an overshoot, an insufficient quick charge, and the like from occurring. The constant current drive circuit includes a resistor R5 connected between the output side of the gm amplifier 6 and the input side of the transistor M1. The comparator 9 serving as a charge stopping circuit includes a voltage Vof, and stops charging by the quick charge circuit 8 based on a comparison result of the voltage Vof and the voltage Vs2 generated in the resistor R5.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: June 16, 2020
    Assignee: NEW JAPAN RADIO CO., LTD.
    Inventors: Kazuyuki Miyajima, Mitsuhiro Enomoto
  • Patent number: 10680602
    Abstract: A control device for driving a bipolar switchable power semiconductor component is designed to apply an electrical voltage to a gate terminal of the power semiconductor component and to reduce the electrical voltage for turning off the power semiconductor component from a first voltage value to a second voltage value. The control device is designed, for turning off the power semiconductor component, firstly to reduce the electrical voltage from the first voltage value to a desaturation value and then to reduce the electrical voltage from the desaturation value to the second voltage value. The desaturation value is greater than a pinch-off voltage of the power semiconductor component.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: June 9, 2020
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Jürgen Böhmer, Rüdiger Kleffel, Eberhard Ulrich Krafft, Andreas Nagel, Jan Weigel
  • Patent number: 10680614
    Abstract: The present document describes a level-shifter circuit and method to transmit data from a high-voltage domain to a low-voltage domain. The level-shifter circuit has a first current path with a first current control unit to set a first current based on a high-voltage data signal in the high-voltage domain; and a second current path with a second current control unit to set a second current based on the high-voltage data signal. Furthermore, the circuit has an isolation unit to transfer the first current and the second current from the high-voltage domain to the low-voltage domain; and a current comparator unit to compare the first current with the second current to provide a low-voltage data signal in the low-voltage domain, which corresponds to the high-voltage data signal.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: June 9, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Horst Knoedgen, Nebojsa Jelaca, Christoph N. Nagl
  • Patent number: 10680601
    Abstract: A controller circuit for controlling an insulated-gate bipolar transistor (IGBT) is configured to, in response to an IGBT turn off switching event, switch out a first switching element to prevent a pull-up signal from flowing to a gate of the IGBT, switch in a second switching element to create a channel to permit a first pull-down signal to flow to the gate of the IGBT, and switch in a third switching element to create a channel to permit a second pull-down signal to flow to the gate of the IGBT. In response to determining a collector to emitter voltage at the IGBT does not satisfy a threshold, the controller circuit is configured to switch out the third switching element to prevent the second pull-down signal from flowing to the gate of the IGBT.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: June 9, 2020
    Assignee: Infineon Technologies AG
    Inventor: Asantha Kempitiya
  • Patent number: 10680604
    Abstract: A turn-off circuit for a semiconductor switch includes an element having a variable resistance coupled to a control input of the semiconductor switch, a circuit for generating a control-input reference signal, and a control circuit coupled to adjust a resistance of the element having a variable resistance in response to the control-input reference signal in a closed control loop in order to turn off the semiconductor switch.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: June 9, 2020
    Assignee: Power Integrations, Inc.
    Inventor: Jan Thalheim
  • Patent number: 10671214
    Abstract: A global coarse baseline correction charge injection circuit comprises: an output capacitor, a slew rate control circuit, a current generator, a first current mirror, and a second current mirror. The output capacitor is configured to store a global coarse baseline correction charge. The slew rate control circuit is configured to receive a modulated voltage, a positive input current, and a negative input current as inputs, and provide a proportional-to-supply-voltage slew-rate controlled voltage as an output voltage to charge the output capacitor. The current generator is configured to receive a supply voltage as an input and provide a proportional-to-supply-voltage (PTSV) current as an output. The first current mirror is configured to mirror the PTSV current to the slew rate control circuit as the positive input current. The second current mirror is configured to mirror the PTSV current to the slew rate control circuit as the negative input current.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: June 2, 2020
    Assignee: Synaptics Incorporated
    Inventors: Wenwei Yang, Chunbo Liu
  • Patent number: 10673436
    Abstract: A device includes a failsafe circuit having a supply node configured to couple to a supply voltage source, a pad node configured to couple to an input/output (I/O) pin, and a bulk node configured to couple to a bulk of a transistor coupled to the I/O pin. The failsafe circuit is configured to assert a failsafe indicator signal when the supply node voltage falls below the pad node voltage by a threshold voltage, and couple the higher of the supply node voltage and the pad node voltage to the bulk node. The device also includes a pull-down stack coupled to the failsafe circuit and to a ground node, and a sub-circuit configured to turn off the pull-down stack in response to the supply node discharging to the threshold voltage below the pad node voltage.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: June 2, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bharat Gajanan Hegde, Devraj Matharampallil Rajagopal, Srikanth Srinivasan
  • Patent number: 10673391
    Abstract: An operational amplifier circuit is provided. The operational amplifier circuit includes a differential input stage circuit and a loading stage circuit. The differential input stage circuit includes an input circuit, a voltage maintaining circuit, and a current source. The input circuit includes a first input transistor and a second input transistor, for receiving a first and a second input signals, respectively. The voltage maintaining circuit includes a first branch circuit and a second branch circuit. The first branch circuit is coupled to the first input transistor for receiving the first input signal, and the second branch circuit is coupled to the second input transistor for receiving the second input signal. The current source is coupled to the first input transistor and the second input transistor. The loading stage circuit is coupled to the voltage maintaining circuit.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: June 2, 2020
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Chih-Wen Lu, Chih-Hsien Chou, Po-Yu Tseng, Jhih-Siou Cheng
  • Patent number: 10666257
    Abstract: A wide-voltage range, failsafe output interface module including a low-voltage, drain extended MOSFETs has been proposed to prevent the flow of reverse current during a failsafe operation while ensuring the MOSFETs are not subject to voltage over their voltage tolerance levels, improving reliability of an output interface module without resorting to more costly transistors with thicker films.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: May 26, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srikanth Srinivasan, Devraj Rajagopal
  • Patent number: 10656188
    Abstract: A load detection circuit includes a variable current source circuit having a first input connected to a power supply, a second input, and a first output connected to an output load; a switched capacitor circuit having a third input connected to an external voltage reference signal, a fourth input connected to the first output of the variable current source, a fifth input connected to ground, a sixth input, and a second output; a comparator having a seventh input connected to the second output of the switched capacitor circuit, an eighth input connected to the first output of the variable current source, and a third output; an edge detector having a ninth input connected to the third output of the comparator, and a fourth output; and a digital controller having a fifth output connected to the variable current source and a sixth output connected to the switched capacitor circuit.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: May 19, 2020
    Assignee: Vidatronic Inc.
    Inventors: Sameh Ahmed Assem Ibrahim, Faisal Abdellatif Elseddeek Hussien, Mohamed Mostafa Saber Aboudina, Mohamed Ahmed Mohamed El-Nozahi
  • Patent number: 10659027
    Abstract: In circuitry to capture differences between magnitudes of first and second comparator input signals in capture operations defined by a clock signal, first and second nodes are connectable to a tail node receiving a cock-signal-independent bias current along first and second paths. During each capture operation, switching circuitry controls connections between the tall node and the first and second nodes based on the input signals to divide the bias current between the first and second paths depending on the input signal magnitude difference. The switching circuitry comprises first and second transistors arranged such that conductivity of connections between the tail node and the first and second nodes Is controlled by the magnitudes of the input signals, and third and fourth non-clocked transistors controlled by a clock-signal independent gate bias signal.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: May 19, 2020
    Assignee: SOCIONEXT INC.
    Inventors: Uwe Zillman, Guido Dröge
  • Patent number: 10658020
    Abstract: A strobe signal generation circuit includes a trigger circuit configured to generate a pull-up signal and a pull-down signal according to a clock signal; a first main driver configured to generate a differential data strobe signal in response to receiving the pull-up signal and the pull-down signal; and a second main driver configured to generate an other differential data strobe signal in response to receiving the pull-up signal and the pull-down signal from among the at least one pull-down signal through opposite terminals than the first main driver received the pull-up signal and the pull-down signal.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: May 19, 2020
    Assignee: SK hynix Inc.
    Inventors: Seung Wook Oh, Hyun Seung Kim
  • Patent number: 10651845
    Abstract: An electronic circuit is provided, including, on one same substrate, an inverter branch formed by high side and low side transistors, and the drivers of the high side and the low side transistors. The drivers include logic gates configured to receive one same PWM input signal and to generate two alternated command signals sent to the high side and the low side transistors. An inverter system is also provided, including the electronic circuit and laser optocouplers configured to electrically insulate the electronic circuit of a controller delivering a pulse width modulation (PWM) input signal and a main supply electrically supplying the drivers.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: May 12, 2020
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Julien Buckley, Rene Escoffier
  • Patent number: 10651691
    Abstract: Radiofrequency energy that is captured by a radiofrequency power harvester is stored in a storage capacitance. One or more user circuits are supplied with energy stored in the storage capacitance. The harvester operates in alternated charge and burst phases with captured radiofrequency energy stored in the storage capacitance in the charge phases and supplied to the user circuits in the burst phases to perform user circuit tasks. In response to detection of completion of the user circuit tasks in a burst phase, the harvester causes operation to shift to the next charge phase.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: May 12, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventors: Roberto Larosa, Giulio Zoppi