Abstract: A display device excellent in downsizing, reduction in power consumption, or layout flexibility of an arithmetic device is provided. The display device includes a pixel circuit, a driver circuit, and a functional circuit. The driver circuit has a function of outputting an image signal for performing display in the pixel circuit. The functional circuit includes a CPU including a CPU core including a flip-flop electrically connected to a backup circuit. The display device includes a first layer and a second layer. The first layer includes the driver circuit and the CPU. The second layer includes the pixel circuit and the backup circuit. The first layer includes a semiconductor layer including silicon in a channel formation region. The second layer includes a semiconductor layer including a metal oxide in a channel formation region. The CPU has a function of correcting the image signal in accordance with the amount of current flowing through the pixel circuit.

Abstract: An illustrative optical measurement system includes a light source configured to emit a light pulse directed at a target. The optical measurement system further includes a control circuit configured to drive the light source with a current pulse comprising a non-linear rise, and a decline from a maximum output to zero having a duration within a threshold percentage of a total pulse duration of the current pulse.

Abstract: A switchable termination resistance circuit for a transceiver physical layer interface.

Abstract: A clamp circuit comprises an output transistor and a replica transistor coupled as a current minor pair, wherein the replica transistor is scaled in size to the output transistor by a size ratio; a first current source configured to set a current in the replica transistor, wherein the output current is set at a clamped output current value that is a sum of current of the first current source and a scaled value of the current of the first current source determined according to the size ratio; and a register circuit, wherein a register value stored in the register circuit sets the clamped output current value.

Abstract: A plasma processing apparatus for cleaning a peripheral portion of a substrate by plasma and comprising a depressurizable processing container accommodating a substrate is disclosed. The processing container includes a substrate support for supporting a substrate and including a central electrode facing a central portion of the supported substrate supported by the substrate support; a lower ring electrode formed in a ring shape to face a lower surface of a peripheral portion of the substrate supported by the substrate support; and an upper ring electrode disposed to face an upper surface of the peripheral portion of the substrate supported by the substrate support. The central electrode is grounded, a radio frequency (RF) power is supplied to each of the upper and lower ring electrodes, and the RF power is supplied to at least one of the upper and lower ring electrodes via a phase adjuster configured to adjust the phase of the RF power.

Abstract: Provided is a driving apparatus including a temperature detection circuit configured to output a temperature detection signal corresponding to a temperature of a switching device, a current detection circuit configured to sample, at a timing during an ON period of the switching device, a current detection signal corresponding to a current that flows in the switching device, and a driving circuit configured to adjust, according to the temperature detection signal and the current detection signal, a driving current to be supplied to a control terminal of the switching device. When the current detection signals are the same, the driving circuit may decrease the driving current according to the temperature detection signal indicating a lower temperature of the switching device. When the temperature detection signals are the same, the driving circuit may decrease the driving current according to the current detection signal indicating a smaller current regarding the main current.

Abstract: An adaptive line driver circuit configured to transmit a signal over a wired link includes a delay-locked loop (DLL) circuit, which includes a phase detector (PD) circuit, charge pump (CP) circuit, and voltage-controlled delay line (VCDL) circuit operatively coupled together. The delay-locked loop circuit provides pre-emphasis and feed-forward equalization of the signal. The delay locked loop circuit also provides a user-configurable parameter including at least one of pre-data tap amplitude, data tap amplitude, post-data tap amplitude, pre-data tap duration, post-data tap duration, pre-data tap quantity, and post-data tap quantity. The adaptive line driver circuit further includes a source-series terminated (SST) driver circuit operatively coupled to the delay-locked loop circuit.

Abstract: The present application provides a level shift circuit, an integrated circuit, and an electronic device. The level shift circuit comprises: an input module, configured to output a first control signal according to a first power supply voltage signal, first and second input voltages, inverted voltages of the first and second input voltages that received; a control voltage generation module, configured to receive the first control signal, and generate a plurality of node voltages according to the first control signal and a second power supply voltage signal; and output control modules, configured to generate first to fourth output signals according to the node voltages and the first power supply voltage signal, or generate fifth to eighth output signals according to the second power supply voltage signal and the node voltages.

Abstract: A driver for driving a switched-mode power supply is presented. The driver receives a set of input signals. Each input signal is configured for changing a state of an associated power switch from a first state to a second state. The driver generates an output signal to change the state of the associated power switch from the first state to the second state. When the first state is an on state and the second state is an off state, the driver asserts the output signal to change the state of the associated power switch to perform an on-off transition. When the first state is the off state and the second state is the on state, the driver delays the assertion of the output signal to perform an off-on transition by a predetermined delay time, so that the off-on transition is delayed until all intended on-off transitions have occurred.

Abstract: A control circuit controls a switching element including a gate and a source corresponding to the gate. The control circuit includes an inductor, a circuit element, and a resistor. The inductor is connected between the gate and the source of the switching element. The circuit element is connected in series to the inductor between the gate and the source. The circuit element allows an electric current to flow therethrough in response to generation of electromotive force in the inductor. The resistor is connected in parallel to the inductor and the circuit element between the gate and the source.

Abstract: Embodiments provide an input buffer circuit and a semiconductor memory, a compensation subcircuit is provided between an input terminal of the input buffer circuit and a first terminal of a load subcircuit, a current of an output terminal of the input buffer circuit is increased, and voltage variation of the input terminal can be transmitted to the output terminal in time, such that the output terminal can timely receive the voltage variation of the input terminal, thereby avoiding distortion of an output signal, solving a problem of signal attenuation for the input buffer circuit, improving sensitivity of the input buffer circuit, and preventing negative effects from being caused to transmission of commands inside a system.

Abstract: A power stage includes: a first transformer; a second transformer; a third transformer; a GaN (gallium nitride) enhancement mode power transistor configured to conduct a load current when driven by a gate current derived from energy transferred by the first transformer; a GaN depletion mode transistor configured to turn off the GaN enhancement mode power transistor absent a threshold voltage applied across a gate and a source of the GaN depletion mode transistor; a voltage clamping device or circuit configured to turn off the GaN depletion mode transistor when reverse biased by a bias current derived from energy transferred by the second transformer; and a GaN enhancement mode transistor configured to turn on the GaN depletion mode transistor when driven by a gate current derived from energy transferred by the third transformer.

Abstract: A multi-level pulser circuit comprises a set of first input pins for receiving respective positive voltage signals at different voltage levels, a set of second input pins for receiving respective negative voltage signals at different voltage levels, and a reference input pin configured to receive a reference voltage signal intermediate the positive voltage signals and the negative voltage signals. The circuit comprises an output pin configured to supply a pulsed output signal. The circuit further comprises control circuitry configured to selectively couple the output pin to one of the first input pins, the second input pins and the reference input pin to generate the pulsed output signal at the output pin.

Abstract: An apparatus includes an apparatus input to receive a voltage input, an apparatus output to drive an output metal oxide semiconductor field effect transistor (MOSFET) at least partially based upon the voltage input, a current source circuit to provide a current source to the apparatus output when the voltage input rises above a first threshold and before the voltage input rises above a second threshold, a voltage clamp circuit to provide a clamped output voltage to the apparatus output when the voltage input rises above the second threshold, and a current sink circuit to provide a current sink to the apparatus output when the voltage input falls below the second threshold and before the voltage input reaches the first threshold.

Abstract: A light-emitting control shift register includes an input circuit, a pulse width adjustment circuit, a pull-up circuit, a pull-down control circuit and a pull-down circuit. The input circuit is configured to output a signal of a first signal input terminal. The pulse width adjustment circuit is configured to transmit the signal output from the input circuit to a pull-up node, and is further configured to output a signal of a second clock signal terminal to the pull-up node. The pull-up circuit is configured to output a voltage of a first voltage terminal to a signal output terminal. The pull-down control circuit is configured to output the voltage of the first voltage terminal, and is further configured to output a voltage of a second voltage terminal. The pull-down circuit is configured to pull down a voltage of the signal output terminal to the voltage of the second voltage terminal.

Abstract: A control circuit is provided for a field-effect transistor with a floating source node. The control circuit includes: a charge storage device electrically connected between a gate of the field-effect transistor and a DC power supply; a gate control circuit electrically connected between the charge storage device and the gate of the field-effect transistor; and a charge control circuit electrically connected between the DC power supply and the charge storage device. The gate control circuit is configured to receive a gate control signal and operates to turn on the field-effect transistor during on time of the gate control signal and turn off the field-effect transistor during off time of the gate control signal. The charge control circuit is also configured to receive the gate control signal and operates to charge the charge storage device with power from the DC power supply during off time of the gate control signal.

Abstract: A power converter including a transformer, a resonant circuit including the transformer and a resonant capacitor having a characteristic resonant frequency and period, and output circuitry connected to the transformer for delivering a rectified output voltage to a load. Primary switches drive the resonant circuit, a switch controller operates the primary switches in a series of converter operating cycles which include power transfer intervals of adjustable duration during which a resonant current at the characteristic resonant frequency flows through a winding of the transformer. The operating cycles may also include energy recycling intervals of variable duration for charging and discharging capacitances within the converter.

Abstract: A process includes coupling a push-pull driver of a first bus device to a plurality of communication lines that are associated with a first bus to allow the first bus device to access the first bus using push-pull signaling. The process includes sharing a set of communication lines with the second bus. The sharing includes coupling an open drain driver of a second bus device to the set of communication lines to allow the second bus device to access the second bus using open drain signaling. The sharing includes using the set of communication lines in first time periods in which the first bus device accesses the first bus and using the set of communication lines in second time periods other than the first time periods in which the second bus device accesses the second bus. The sharing includes isolating a push-pull driver of the first bus device from the set of communication lines responsive to the second time periods.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes p pixel unit groups, and each of the p pixel unit groups includes q rows of pixel units, both p and q being integers greater than or equal to 2. Pixel units in a same group are simultaneously supplied with a gate scan signal by a same shift register, and pixel units in a same group and in a same column are supplied with data voltage signals through different data lines, respectively.

Abstract: This application relates to methods and apparatus for multichannel drivers for driving transducers in different channels. A multichannel driver has a plurality of output stages configured such that two output nodes can be modulated between selected switching voltages with a controlled duty cycle to generate a differential output signal across a respective transducer, each output stage being operable with different switching voltages in different modes of operation. A first set of two or more of the output stages are arranged to receive a voltage output by a capacitive voltage generator to use as a switching voltage. A controller is configured to control the mode of operation and duty-cycle of each of the output stages based on a respective input signal and also based on operation of the other output stages of the first set.

Abstract: A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.

Abstract: A gate driving circuit includes: a pull-up control circuit configured to control a voltage of a pull-up control node in response to a pull-up control signal; a pull-down control circuit configured to control a voltage of a pull-down control node in response to the voltage of the pull-up control node; a carry output circuit configured to output a carry signal in response to the voltage of the pull-up control node and the voltage of the pull-down control node; and a gate output circuit configured to output a plurality of gate signals having different timings in response to the voltage of the pull-up control node and the voltage of the pull-down control node, wherein a width of the carry signal is greater than a width of each of the gate signals.

Abstract: A semiconductor device according to the present disclosure includes: a first output terminal and a second output terminal; a first driver that has a first positive terminal coupled to the first output terminal and a first negative terminal coupled to the second output terminal, and outputs a differential signal corresponding to a first signal from the first positive terminal and the first negative terminal; and a second driver that has a second positive terminal coupled to the second output terminal and a second negative terminal coupled to the first output terminal, and outputs a differential signal corresponding to the first signal from the second positive terminal and the second negative terminal.

Abstract: A gate driving circuit, a display panel, and a display device are disclosed. The gate driving circuit includes a plurality of gate driving units. At least one gate driving unit includes a second transistor configured to transmit a first voltage signal to a second node of the gate driving unit of the current stage according to a potential of a first node of the gate driving unit in a previous stage before transmitting a pre-charge signal to the first node of the gate driving unit in the current stage. Both the display panel and the display device include gate driving circuits.

Abstract: A system for driving a plurality of high side NMOS power switches includes a charge pump to generate a boot voltage across a charge pump capacitor and a plurality of high side drivers. Each high side driver includes a PMOS switch to turn on the high side NMOS power switch and an NMOS switch to turn off the high side NMOS power switch. A first inverter chain coupled between the boot voltage and the input voltage generates a first control signal to control the PMOS switch and a second inverter chain coupled between an internal boot voltage and the floating switch node generates a second control signal to control the NMOS switch. The boot voltage can be equal to the input voltage plus a regulator voltage and is substantially independent of a voltage at the floating switch node and the internal boot voltage can be equal to a voltage at the floating switch node plus a regulator voltage.

Abstract: The present application discloses a display device and electronic device. The display device is configured by sequentially configuring the corresponding first bias current, second bias current, and third bias in a start period, a sustain period, and an end period. The current value of the first bias current is greater than the current value of the second bias current, and/or the current value of the third bias current is greater than the current value of the second bias current, which improves the display quality and reduces display power consumption.

Abstract: An electronic circuit that recognizes a disconnected state from an outside during disconnection of a power supply line is provided. For this purpose, an electronic circuit includes: a load provided between a power supply line and an output terminal in the electronic circuit; a transistor provided between the load and the output terminal; a current generation circuit that generates current using a power supply voltage at a power supply line in the electronic circuit; and a control circuit that controls the transistor using a control voltage that changes according to the current generated by the current generation circuit.

Abstract: A circuit arrangement is provided where the arrangement of a feedback resistor between a first branch and a second branch enables that a voltage is provided at an output terminal in an efficient way, this means with a high settling speed and a low current consumption. The feedback resistor is arranged between a reference node and the output terminal, where the reference node is connected to a current mirror. The circuit arrangement can be employed as a gate driver. Furthermore, a driver block and a method of driving a circuit arrangement are provided.

Abstract: A feed-forward equalizer (FFE) and a voltage-mode signal transmitter using the same are provided. The FFE includes an output, a plurality of tap drivers, and a control circuit. Each tap driver includes a cell driver. The control circuit includes a FFE control loop and an impedance control loop. The FFE control loop includes a first replica circuit corresponding to a part of the cell drivers. The FFE control loop generates at least one first reference voltage according to the first replica circuit. The impedance control loop includes a second replica circuit corresponding to the cell drivers in the tap drivers. The impedance control loop generates at least one second reference voltage according to the first reference voltage and the second replica circuit. The tap drivers are controlled by the first and second reference voltages to adjust respective output impedance thereof.

Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

Abstract: A gate driver includes a plurality of active stages and a plurality of dummy stages. The active stage is configured to output a plurality of gate signals to a display region. The dummy stage is c connected to respective active stages and configured to output a plurality of dummy carry signals to the respective active stages. The active stage is configured to output the plurality of gate signals and a plurality of active carry signals. The plurality of dummy stages are configured to output the plurality of dummy carry signals, respectively, and not to output any gate signal.

Abstract: A semiconductor device includes an input terminal, an output terminal, and a plurality of transistors. The transistors are coupled through serial coupling. The transistors include a first transistor and a second transistor. The first transistor has a first end and a second end. The second transistor has a third end, a fourth end, a first gate, and a first body. The third end is coupled to the second end. The semiconductor device further includes a third transistor and a first diode. The third transistor and the first diode are serially coupled between the first body and the first end. The third transistor includes a second gate coupled to the first gate.

Abstract: A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

Abstract: An adaptive clamp circuit includes a clamp circuit and a clamp control circuit. The clamp circuit includes a first transistor, a second transistor, and a variable resistor. The first transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal is coupled to a switching terminal. The second current terminal is coupled to a ground terminal. The second transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal of the second transistor is coupled to the control terminal of the first transistor. The second current terminal of the second transistor is coupled to the switching terminal. The variable resistor is coupled between the control terminal of the second transistor and the ground terminal. The clamp control circuit is coupled between the switching terminal and the variable resistor.

Abstract: A power electronics device has a first power semiconductor switch and a driver circuit and enables a supply of electrical voltage to a driver circuit. An auxiliary circuit arrangement has a supply capacitor, an auxiliary capacitor, a normally off auxiliary semiconductor switch, a diode and a bootstrap diode. The auxiliary semiconductor switch is connected to a reference potential connection of the first power semiconductor switch via a connection point, starting from the connection point, a series connection of the diode, a second connection point and the auxiliary capacitor is arranged in parallel with the auxiliary semiconductor switch. When the auxiliary semiconductor switch is in the off state, the auxiliary capacitor is charged by the flow of current through the first power semiconductor switch.

Abstract: A driving current includes a first and second push-pull circuits which each includes a first and second output terminals and a first to fourth transistors. The first to fourth transistors are series connected. At least one of control terminals of the first and second transistors of the first push-pull circuit and at least one of control terminals of the third and fourth transistors of the second push-pull circuit receive a positive input signal. At least one of control terminals of the third and fourth transistors of the first push-pull circuit and at least one of control terminals of the first and second transistors of the second push-pull circuit receive a negative input signal. The first output terminals output a pair of first signals. The second output terminals output a pair of second signals.

Abstract: The disclosure relates to a shift register, a driving method thereof, a gate drive circuit, and a display device. An output pulse width can be reduced by 1/(n+1) to (n?1)/(n+1) clock cycle by setting a pulse width modulation module (104), where n is the number of clock signal terminals in one-to-one correspondence with the enable signal terminals, and the pulse width reduced by 1/(n+1) to (n?1)/(n+1) clock cycle needs to be output several times under the condition that the light emitting duration of pixels is unchanged. In this way, the refresh rate is increased, and thus the flicker phenomenon in the process of low gray-scale brightness adjustment is less detectable to the human eyes.

Abstract: Embodiments of the invention provide IGBT circuit modules with increased efficiencies. These efficiencies can be realized in a number of ways. In some embodiments, the gate resistance and/or voltage can be minimized. In some embodiments, the IGBT circuit module can be switched using an isolated receiver such as a fiber optic receiver. In some embodiments, a single driver can drive a single IGBT. And in some embodiments, a current bypass circuit can be included. Various other embodiments of the invention are disclosed.

Abstract: A scan driver includes: a first transistor having a first electrode coupled to an output scan line, a second electrode coupled to a first power line, and a gate electrode coupled to a first node; a second transistor having a first electrode coupled to a first clock line, a second electrode coupled to the output scan line, and a gate electrode coupled to a second node; a third transistor having a first electrode coupled to the first node, a second electrode coupled to a first input scan line, and a gate electrode coupled to a second clock line; and a fourth transistor having a first electrode coupled to the second node and a second electrode and a gate electrode, which are coupled to a second input scan line, wherein the first input scan line and the second input scan line are different from each other.

Abstract: Devices and methods are provided for controlling dead-time of a direct current to direct current (DC-DC) converter. A control circuit includes a first transistor having a source/drain terminal coupled to an output voltage of the DC-DC converter configured to provide current based on the output voltage. The control circuit also includes a digital up/down counter having an output terminal electrically coupled to an input terminal of a delay cell of the DC-DC converter. A current sensing circuit of the control circuit is electrically coupled to an input terminal of the digital up/down counter configured to receive the current and drive the digital up/down counter based on the current.

Abstract: An apparatus to insure safe behavior in an inverter system. In one embodiment, the apparatus includes a first high side gate driver, a first low side gate driver, a microcontroller configured to control the first high side and low side gate drivers. A voltage regulator provides a supply voltage to the microcontroller. A first pair of high side voltage regulators provide a first pair of high side supply voltages to the first high side gate driver. A first pair of low side voltage regulators provide a first pair of low side supply voltages to the first low side gate driver.

Abstract: Disclosed is a method and a control circuit. The method includes operating a buffer circuit in a first operating mode or a second operating mode. Operating the buffer circuit in the first operating mode includes buffering, by a first capacitor of the buffer circuit, power provided by a power source and received by a load. Operating the buffer circuit in the second operating mode includes connecting a second capacitor in series with the first capacitor to form a capacitor series circuit, supplying power to the load by the capacitor series circuit, and regulating a first voltage across the capacitor series circuit. Regulating the first voltage includes transferring charge from the first capacitor to the second capacitor.

Abstract: A semiconductor device includes an on-die resistor circuit comprising an on-die resistor, a calibration circuit configured to perform a calibration operation on the on-die resistor, and a calibration control circuit configured to control the calibration operation of the calibration circuit. The calibration circuit includes a current generating circuit configured to supply a calibration current to the on-die resistor and a comparing circuit configured to compare the magnitude of a first input signal that is generated by the calibration current and the on-die resistor with a magnitude of a second input signal that is generated by the calibration current and an external resistor.

Abstract: Various implementations described herein are directed to a device having an input-output pad configured to receive and supply an input-output pad voltage. The device may include gate tracking circuitry that receives a first voltage, receives a second voltage different than the first voltage, receives node voltages and provides a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage and the node voltages. The device may include output circuitry that receives the first tracking voltage and the second tracking voltage from the gate tracking circuitry and provides the input-output pad voltage to the input-output pad based on the first tracking voltage and the second tracking voltage.

Abstract: The invention relates to a transmitter for transmitting a process variable to a programmable logic controller. In a current mode a 4-20 milliamp current is fed into a burden and in a voltage mode 0-10 Volt signals are generated. The transmitter includes a process value input, a current stage, a voltage stage and a U/I output for the current or the voltage signal, and a U/I control input for switching between the two modes. The transmitter is configured to feed a current which is dependent on the voltage across the burden into the current stage via a resistor and thus to compensate for a current loss at the voltage stage which is dependent on the voltage across the burden.

Abstract: The invention relates to a switch system (1) comprising a power line (2) for supplying a charge from a voltage source (+Vbat), said power line having a main switch (Q1) comprising a first main terminal (D) and a second main terminal (S), between which a main current (Ip) is intended to pass, and a control terminal (G) for selectively placing the main switch (Q1) in a closed, open or semi-closed state, the main switch (Q1) in its semi-closed state being equivalent to a variable resistor controlled by the control terminal and connected between the first and the second main terminal, characterized in that the switch system (1) further comprises a current-limiting device (3) designed to, when the main current (Ip) exceeds a maximum current threshold, decrease a control current (Ig) entering the control terminal (G), so as to cause the main switch (Q1) to transition from the closed state to the semi-closed state, so as to limit the main current.

Abstract: Power converting devices (100) for power tools. One embodiment provides a power converter device (100) including a power source (200), a power converter (210) coupled to the power source (200), and an electronic processor (220) coupled to the power converter (210) to control the operation of the power converter (210). The power converter (210) is configured to receive an input power in one form or at a first voltage from the power source and convert the input power to an output power in another form or at a second voltage. The power converter (210) includes at least one wide bandgap field effect transistor controlled by the electronic processor (220) to convert the input power to output power.

Abstract: A gate drive device drives a gate of each of two semiconductor switching elements constituting upper and lower arms of a half bridge circuit. The gate drive device detects a peak value of an element voltage that is a voltage of a main terminal of one of the two semiconductor switching elements, as one semiconductor switching element, or a change rate of the element voltage during a change period in which the element voltage changes. The gate drive device determines whether an energization to the one semiconductor switching element during the change period is a forward energization in which a current flows in a forward direction or a reverse energization in which the current flows in a reverse direction.

Abstract: The present invention relates to a method for recharging an energy store (102) used to drive a power semiconductor switch (100), wherein the energy store (102) and the power semiconductor switch (100) are at the same potential, wherein a switching state of the power semiconductor switch (100) is effected by a controller (204, 712), wherein the controller (204) assigns a respective potential value to the energy store (102) at a respective switching state (202) and wherein, by driving at least one charging switch (112, 114, 122, 132, 142, 152), charging of the energy store (102) is activated as soon as the potential value of the energy store (102) corresponds to a ground potential of a supply voltage (106, 216).

Abstract: There are an amplifier circuit which includes a first current source that is connected to a power supply line to which a first electric potential is supplied, a differential input circuit that is connected between the first current source and a first node and configured to receive a differential input signal, a second current source that is connected between a power supply line to which a second electric potential is supplied and the first node, and a load circuit that is connected between a power supply line to which the first electric potential is supplied and a second node, and an inductor circuit is further connected between the first node and the second node. Thereby, the amplifier circuit achieves both lower voltage and linearity.