Abstract: Disclosed is a control circuit for controlling a controllable power semiconductor switch, and to a power semiconductor module. The control circuit comprises at least two circuit sets, each having a power driver. The power driver of each of the circuit sets is provided with power via impedance components having an impedance other than zero.

Abstract: A half bridge is described with at least one transistor having a channel that is capable in a first mode of operation of blocking a substantial voltage in at least one direction, in a second mode of operation of conducting substantial current in one direction through the channel and in a third mode of operation of conducting substantial current in an opposite direction through the channel. The half bridge can have two circuits with such a transistor.

Abstract: The transceiver features a fast de-excitation circuit, by means of which the transceiver can be very quickly de-energized or de-excited after sending of signals. The fast de-excitation circuit can be realized in the simplest case as a controllable switch with series-connected resistor. The transceiver is thus ready to receive signals again very fast, i.e. in the range of a few oscillation periods. With bidirectional data communication between transceiver and transponder the danger of malfunctions is avoided or at least reduced to a minimum level.

Abstract: An apparatus for monitoring current for a motor drive including at least high-side and low-side switching transistors includes a driver circuit for driving a gate of the low-side switching transistor. First circuitry measures a drain to source voltage across the low-side switching transistor and generates a voltage output responsive thereto. Second circuitry has a first state of operation that samples the voltage output of the first circuitry when the low-side switching transistor is turned on and has a second state of operation to sample the voltage output of the first circuitry when the low-side switching transistor is turned off. The second circuitry further generates a monitored output current responsive to the sampled voltage output.

Abstract: An H bridge circuit includes a gate driver circuit coupled to a gate of an NMOS device. The output of the gate driver circuit is at a voltage from 0.1V to 0.4V during a dead time of the H bridge circuit. The gate voltage of the NMOS device is biased at 0.1˜0.4V to overcome the problems of minority carrier injection and power dissipation as compared with VG=0 in a conventional H bridge circuit.

Abstract: A differential drive circuit includes at least a first or second drive system. The first drive system has first and second field effect transistors, first and second resistors, and first and second circuits controlling the source voltages of the first and second field effect transistors to equal first and second drive target voltages, the first and second field effect transistors having sources connected to a power potential via the first and second resistors, respectively. The second drive system has third and fourth field effect transistors, third and fourth resistors, and third and fourth circuits controlling the source voltages of the third and fourth field effect transistors to equal third and fourth drive target voltages, the third and fourth field effect transistors having sources connected to a reference potential via the third and fourth resistors, respectively. A common-mode voltage is driven to form a constant differential signal across a load resistance.

Abstract: One embodiment of the invention includes a driver circuit. The driver circuit comprises an output transistor that is biased to provide an output signal in response to an input signal. The driver circuit also comprises at least one programmable variable resistor configured to provide a bias magnitude of the output transistor that sets a power of the driver circuit to be commensurate with a data-rate of the input signal.

Abstract: An H-bridge circuit includes a lower-arm field-effect transistor and a current supplying element that turns on when the drain of the lower-arm field-effect transistor is negatively biased due to regenerative current. When turned on, the current supplying element conducts current from the source to the drain of the lower-arm field-effect transistor, in parallel with a parasitic diode inherent in the lower-arm field effect transistor. The current supplying element competes with other parasitic elements that conduct current from peripheral circuitry to the drain of the lower-arm field-effect transistor, thereby reducing the amount of such current drawn through the peripheral circuitry and lessening the impact of the regenerative current on the peripheral circuits.

Abstract: A non-inverting AC/DC input buffer combines the desirable characteristics of an alternating current (AC) input buffer including low delay, high speed, and high input voltage swing range with the desirable characteristics of a direct current (DC) input buffer including stability, reliability, and ‘automatic’ high and low data setup. The AC/DC buffer includes logic to help prevent the DC input buffer from interfering with the AC input buffer until the DC input buffer has completed its operations on a transitioning input. The DC buffer is configured to enable the AC buffer to process low input voltage swings such as, for example, voltage swings less than the difference in power supply voltages.

Abstract: An electronic device for delivering DC power includes a load, a power end, an upper gate switch including a first end coupled to the power, a second end, and a third end, for conducting connection between the first and third ends according to the signal level of the second end, a lower gate switch including a first end coupled to the third end of the upper gate switch, a second end, and a third end coupled to ground, for conducting connection between the first and third ends according to the signal level of the second end, an inductor, and a switch control unit, coupled to the second end of the upper gate switch and the second end of the lower gate switch, for switching the upper gate switch between an ON state and an OFF state, and switching the lower gate switch between an ON state and a semi-ON state.

Abstract: A load-driving circuit supplies electric current to a load, such as a resistor of an airbag squib. The load-driving circuit includes high side and low side current control circuits, both connected in series. Each current control circuit is composed of a driving transistor, a resistor and a current mirror circuit for controlling operation of the driving transistor. The components in the load-driving circuit are positioned in an integrated circuit chip to generate different temperature gradients among the components. For example, the low side resistor is positioned close to the high side driving transistor, so that the low side resistor is heated by the high side driving transistor controlled under a constant current control. As the low side resistor is heated, the high side driving transistor is switched from the constant current control to a full-on control. In this manner, controls of both driving transistors are automatically switched thereby to avoid overheating of one of the driving transistors.

Abstract: Conventional diode rectifiers usually suffer from a higher conduction loss. The present invention discloses a gate-controlled rectifier, which comprises a line voltage polarity detection circuit, a constant voltage source, a driving circuit and a gate-controlled transistor. The line voltage polarity detection circuit detects the polarity of the line voltage and controls the driving circuit to turn on or turn off the gate-controlled transistor. The gate-controlled transistor may be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with a gate, a source and a drain or an Insulated Gate Bipolar Transistor (IGBT) with a gate, an emitter and a collector. The constant voltage source is provided or induced by external circuits and referred to the source of the MOSFET or the emitter of the IGBT. Thanks to a lower conduction loss, this gate-controlled rectifier can be applied to rectification circuits to increase the rectification efficiency.

Abstract: Phase-coherent differential structures contain a phase-coherent transformer having two pairs of phase-coherent coupled differential inductors.

Abstract: A receiver circuit capable of controlling setup/hold time includes a first phase transmission unit configured to generate a first output signal by detecting input data according to plural detection levels while being synchronized with a first clock signal, and controlling setup/hold time of the first output signal based on a level of a first offset voltage, a level converter configured to control a voltage level of the first output signal according to a first code, and a second phase transmission unit configured to receive an output signal of the level converter for as a second offset voltage while being synchronized with a second clock signal, to generate a second output signal by detecting the input data according to the detection levels, and to control setup/hold time of the second output signal.

Abstract: Current regulators and related method for regulating a current through a load. The current regulator may include, for example, a first circuit configured to determine an amount of current that flows through the load; and a second circuit configured to cause a voltage to be applied across the load, the voltage having a duty cycle that depends on the amount of the current flowing through the load.

Abstract: A driving circuit of a semiconductor optical amplifier type gate switch constituting a matrix optical switch is provided with an operation amplifier into which a driving signal is input and from which a current corresponding to the driving signal is output, an inductance element provided at an output terminal of the operation amplifier, and a circuit composed of a diode element and a resistor element connected in parallel and provided between the inductance element and the semiconductor optical amplifier.

Abstract: In accordance with an aspect of the present invention, an external FET driving circuit includes a driving portion, a drain-to-gate clamp portion and a current feedback portion. The driving portion provides a driving signal to the external FET. The drain-to-gate clamp portion protects the external FET from flyback current, when the external FET is quickly turned OFF. The current feedback portion controls the driving signal provided by the driver.

Abstract: A gate driver for a power MOSFET in, for example, a DC-DC converter switches the MOSFET between a fully-on condition and a low-current condition instead of switching the MOSFET between fully-on and fully-off conditions. The amount of charge that must be transferred to charge and discharge the gate of the MOSFET is thereby reduced, and the efficiency of the MOSFET is improved. A feedback circuit may be used to assure that the magnitude of current in the power MOSFET in its low-current condition is correct. Alternatively, a trimming process may be used to correct the magnitude of the voltage supplied by the gate driver to the gate of the power MOSFET in the low-current condition.

Abstract: A drive control apparatus controls a drive of an inductive load having a current flowing therethrough. The drive control apparatus includes a drive control device for controlling a variation of the current flowing through the inductive load within a certain period by Pulse Width Modulation control so as to come close to a reference current value, and a reference value control device for controlling a fluctuation period of the reference current value and making the fluctuation period of the reference current value longer than that of the current flowing through the inductive load by the Pulse Width Modulation control.

Abstract: A gate drive circuit for a wide bandgap semiconductor junction gated transistor includes a gate current limit resistor. The gate current limit resistor is coupled to a gate input of the wide bandgap semiconductor junction gated transistor when in use and limits a gate current provided to the gate input of the junction gated transistor. An AC-coupled charging capacitor is also included in the gate drive circuit. The AC-coupled charging capacitor is coupled to the gate input of the wide bandgap semiconductor junction gated transistor when in use and is positioned parallel to the gate current limit resistor. A diode is coupled to the gate current limit resistor and the AC-coupled charging capacitor on one end and an output of a gate drive chip on the other end When in use, the diode lowers a gate voltage output from the gate drive chip applied to the gate input of the wide bandgap semiconductor junction gated transistor through the gate current limit resistor.

Abstract: A full bridge that produces an alternating output signal can be driven by operating switching elements of the full bridge in each period in a switching sequence that determines the order of the activation and deactivation of the switching elements. The switching elements are switched in at least two different switching sequences, a first switching sequence is repeated n times before a second switching sequence is carried out, with n>1, or the switching elements are switched in at least three different switching sequences.

Abstract: A driver chip for driving an inductive load and a module having a driver chip are provided. The driver chip contains a first transistor for coupling a first potential to a first output and a second transistor for coupling a second potential to the first output. A first protection circuit reduces an increased voltage between a control terminal and a load junction terminal of the first transistor. The driver chip has a first state in which the second transistor is turned off and the first transistor can switch a passive inductive load connected to the output. In a second state, the first transistor and the second transistor can switch an external power transistor connected to the first output. A second output is connected to a load junction terminal of the external power transistor. A second protection circuit reduces an increased voltage between the first and second outputs.

Abstract: An output CMOS buffer includes MOS enhancement transistors and has a second complementary pair of natural or low threshold transistors, connected respectively in parallel to transistors of opposite type of conductivity of the complementary pair of enhancement MOS transistors of the final buffer stage. The gate terminals of the pair of natural or low threshold transistors are controlled by respective inverters, each supplied through a slew rate limiter of the slope of the driving current and are respectively connected between the positive supply node of the output buffer and a negative (below ground potential) node and between the common ground node of the output buffer and a positive supply node. The negative voltage and the positive voltage on the nodes are at least equal to the absolute value of the threshold voltage of the natural or low threshold transistors.

Abstract: An output stage may include an input terminal receiving an input signal, an output terminal coupled to an external load, and a pre-buffer coupled to the input terminal and including an enable terminal receiving a general enable signal and a first output terminal for supplying a first control signal. The output stage may also include an output buffer including a first final transistor inserted between the supply terminal and the output terminal, and a control terminal coupled to the first output terminal of the pre-buffer for receiving the first control signal, and a first tracking circuit between the supply terminal and the first output terminal of the pre-buffer. The first tracking circuit may include a first capacitor between the supply terminal and a first intermediate node coupled to the first output terminal of the pre-buffer by a switch activated by a first activation signal during a transient of the first final transistor thereby reconstructing a noise of the first reference voltage.

Abstract: Power savings are achieved for digital data transport over short distances by using the characteristics of resonant LC circuits. Economy of circuit elements is achieved by enabling a single pair of resonant circuits to drive large numbers of digital data lines or nodes in parallel. This maximizes power efficiency and minimizes area and cost. Resistance is minimized by insuring that all switches in the current path are fully “ON” whenever significant current is flowing through them. All other parasitic resistances in the circuits, consisting primarily of parasitic interconnect resistances, are minimized. This enables the data transmission circuits to achieve maximum Q or quality factor, which minimizes power dissipation.

Abstract: Methods and apparatus to provide dynamically biased write drivers for hard disk drive applications are described. According to one example, a hard disk drive write system includes a drive signal generator to receive data to be written to a hard disk drive platter and to generate drive signals including a boost signal. A drive circuit is configured to receive the drive signals and to generate currents for output to the transmission line based thereon, wherein the currents include a boost current. A variable bias circuit is configured to detect the boost signal generated by the drive signal generator and to vary a bias signal provided to the impedance matching circuit based on the detection of the boost signal. In such an example arrangement, the impedance matching circuit matches impedances between the drive circuit and the transmission line in response to the bias signal provided by the variable bias circuit.

Abstract: A driving device of a capacitive load includes a modulator that executes pulse modulation on a drive waveform signal. An inductor performs low-pass filtering on the modulated drive waveform signal and outputs the low-pass filtered signal as a drive signal towards a load capacitor as the capacitive load. A load selection control circuit selects a load capacitor and a dummy load capacitor to be connected to the inductor so that a sum of the capacitances of the selected load capacitor and dummy load capacitor is kept within a predetermined range. A feedback circuit executes a filtering process on the drive signal so that a frequency characteristic of a passing band of the drive signal becomes substantially flat. The resulting signal is provided to the modulator as a feedback signal. The modulator executes the pulse modulation on a difference value between the drive waveform signal and the feedback signal.

Abstract: The invention relates to a method for the digital transmission of an analogue measuring signal (M), comprising the following steps: comparing momentary values of a triangular signal (D) with a value of the measuring signal (M) for generating a binary measurement pulse (PM); comparing momentary values of the triangular signal (D) with a predeterminable first reference variable (R1) for generating a binary reference pulse (PR) that corresponds to the measurement pulse (PM) and transmitting the measurement pulse (PM) and reference pulse (PR) at a constant phase.

Abstract: A buffer circuit is described for buffering signals between a circuit element and a load. The buffer includes a main transistor and a cascode transistor, as well as a distribution line for transferring signals over a distance between the circuit element and the load. The buffer is arranged in a remote cascode topology such that the cascode transistor is located substantially adjacent to the load and remote from the main transistor. The distribution line transfers signals over the distance from the main transistor to the cascode transistor. This remote cascode topology makes it possible to significantly reduce the power consumption of the buffer—as compared to conventional buffers—while maintaining the maximum bandwidth possible.

Abstract: An integrated circuit device for switching electrical loads that have an inductive component comprises at least one switching channel that includes a power stage with a power MOS transistor and a driver circuit for driving the gate of the power MOS transistor, the switching stage being configurable for use in either of a High Side configuration and a Low Side configuration.

Abstract: A desaturation circuit for an IGBT is disclosed. In one embodiment, flooding of the component with charge carriers is reduced before the IGBT is turned off.

Abstract: A method for controlling a vertical type MOSFET in a bridge circuit is provided to reduce diode power loss and improve a reverse recovery characteristic. The method includes controlling a forward voltage of a built-in diode of the vertical type MOSFET to be a first forward voltage by setting a gate voltage of the vertical MOSFET to a first gate voltage, so that the vertical type MOSFET is switched into a first off mode; and controlling the forward voltage of the built-in diode of the vertical type MOSFET to be a second forward voltage by setting the gate voltage of the vertical MOSFET to a second gate voltage, so that the vertical type MOSFET is switched into a second off mode.

Abstract: A circuit having a first circuit portion configured to receive a pulse-width modulated first signal and a second signal, and configured to generate third and fourth signals each responsive to the first and second signals; a second circuit portion configured to receive the third and fourth signals and to generate a fifth signal responsive to both the third and fourth signals; and a third circuit portion configured to control an on/off state of a first switch in response to the fifth signal, wherein the second signal is present at a load path terminal of the first switch. Also, various related methods.

Abstract: A switching control circuit of synchronous rectification type that is capable of reducing dead time is obtained. Upon detection that an output potential rises above VDD-Va, a first sensor outputs an H signal to a first input terminal of a first NOR circuit, and the first NOR circuit outputs an L signal to a second input terminal of a second NOR circuit, and the second NOR circuit outputs an H signal to a first gate driving circuit. A PMOS is thereby turned on. Upon detection that the output potential falls below GND+Vb, a second sensor outputs an L signal to a first input terminal of a first NAND circuit, and the first NAND circuit outputs an H signal to a second input terminal of a second NAND circuit, and the second NAND circuit outputs an L signal to a second gate driving circuit. An NMOS is thereby turned on.

Abstract: A high voltage reception terminal is formed in a semiconductor integrated circuit without increasing the number of manufacturing processes and the manufacturing cost. A transfer gate configured from a NMOS, which is the high withstand voltage transistor, and a pull-up resistor are formed. An input terminal of the transfer gate is connected to the high voltage reception terminal and an output terminal of the transfer gate is connected to a CMOS inverter through an input resistor. One end of the pull-up resistor is connected to the output terminal of the transfer gate and the other end of the pull-up resistor receives source voltage VDD (5V). The transfer gate lowers the inputted high voltage VX (VX>VDD) to VDD-Vt1?. The pull-up resistor biases the voltage at the output terminal of the transfer gate to VDD and boosts the voltage at the output terminal that has been lowered by the transfer gate to about VDD.

Abstract: An H-bridge circuit includes a lower-arm field-effect transistor and a current supplying element that turns on when the drain of the lower-arm field-effect transistor is negatively biased due to regenerative current. When turned on, the current supplying element conducts current from the source to the drain of the lower-arm field-effect transistor, in parallel with a parasitic diode inherent in the lower-arm field effect transistor. The current supplying element competes with other parasitic elements that conduct current from peripheral circuitry to the drain of the lower-arm field-effect transistor, thereby reducing the amount of such current drawn through the peripheral circuitry and lessening the impact of the regenerative current on the peripheral circuits.

Abstract: In the case of an electronic circuit, comprising a drive unit, which generates at least one drive signal, two or more power semiconductor switches each having a first and a second main terminal, which power semiconductor switches can be switched synchronously by the drive signal, the first and the second main terminals of the power semiconductor switches in each case being electrically connected in parallel among one another, for each of the power semiconductor switches a first and a second electrically conductive connection for connection to the drive unit, a uniform dynamic current division between the power semiconductor switches is achieved according to the invention by virtue of the fact that a first inductance is provided in each of the first electrically conductive connections, and a second inductance is provided in each of the second electrically conductive connections, the first inductance being coupled to the second inductance for each of the power semiconductor switches.

Abstract: An integrated circuit (100) includes a current mode write driver (105). The write driver (105) includes a switching control circuit (110) including (i) a DC current control circuit (111) operable to directly convert a received ECL differential signal into first, second, third and fourth DC output currents (a, b, c, and d) and (ii) a boost current control circuit (112) operable to directly convert a received level shifted version of the ECL differential voltage signal and a delayed version of the ECL differential voltage signal into first, second, third and fourth boost output currents (a1, b1, c1, and d1). An H-bridge circuit (120) includes an output stage (125) including first and second current sourcing control nodes (126, 127) and first and second current sinking control nodes (128, 129). A first output node (131) is between the first sourcing and first sinking nodes (126, 128) and second output node between the second sourcing and the second sinking nodes (127, 129).

Abstract: A semiconductor device is provided with a plurality of semiconductor chips and at least one transmission coil (108) for transmitting signals by using inductor coupling between the semiconductor chips. A plurality of transmission coils are connected in series.

Abstract: A drive circuit in power electronic systems comprising a half-bridge circuit of two power switches, a first so-called TOP switch and a second so-called BOT switch, which are arranged in a series circuit. The drive circuit has a BOT level shifter for transmitting an input signal from a drive logic to a BOT driver. The BOT level shifter is formed as an arrangement of an UP and a DOWN level shifter branch and a signal evaluation circuit connected downstream thereof. In the inventive method for transmitting the input signal, the signal evaluation circuit transfers an output signal to the BOT driver at least one of the UP and DOWN level shifter branches outputs a signal to the respectively assigned input of the signal evaluation circuit.

Abstract: An improved capacitor coupled floating gate drive circuit is revealed that provides an effective drive mechanism for a floating or high side switch without the use of level shifting circuits or magnetic coupling. The capacitor coupled floating gate drive circuit is an improvement over prior art capacitor coupled floating gate drive circuits in that the new circuit uses a positive current feedback mechanism to reject slowly changing voltage variations that cause unintentional switch state changes in prior art capacitor coupled floating gate drive circuits.

Abstract: A circuit system and method are provided to modify a hard disk writer/driver pre-amplifier electronic circuit to synchronize current boosting control signals. The circuit system obtains a single boosting control signal from a single source. Component boosting control signals, a positive and a negative boosting control signal are indirectly generated via processing through two independent intermediate circuits. The two boosting control signals are pulse shaped signals via intermediate circuits which generate the corresponding first and second intermediate output signals in a manner that the two intermediate output signals are made compatible with one another and particularly synchronize to be later combined by some manner of combiner circuit without the generation of unwanted components in the output signal.

Abstract: A method drives a transistor half-bridge. The method includes measuring a delay time between an edge of an input signal and an corresponding edge of a phase signal, and saving the delay time as a saved delay time value. The phase signal is the output of the transistor half-bridge. In the method, the following steps are repeated until the saved delay time value differs from the delay time by more than a given threshold: decrementing the delay-value of a programmable delay circuit and the saved delay time value by a given decrement, the programmable delay circuit coupled to a control terminal of a first transistor of the half-bridge, and measuring the delay time between an edge of the input signal and an corresponding edge of the phase signal.

Abstract: A switching drive circuit for soft switching is disclosed. It includes an input circuit to receive an input signal. A first delay circuit generates a first delay time in response to the enable of the input signal. A second delay circuit generates a second delay time in response to the disable of the input signal. A switching signal generator generates switching signals. The pulse width of the high-side switching signal is generated in proportion to the pulse width of the input signal. The high-side switching signal enabled after the first delay time once the input signal is enabled. The low-side switching signal disabled in response to the enable of the input signal. The low-side switching signal is enabled after the second delay time once the high-side switching signal is disabled.

Abstract: In one embodiment a drive circuit includes two comparators which are adapted to sense kickback voltage generated in an inductive load and conduct two field-effect transistors connected to ground in a very short period of time so as to quickly reduce the kickback voltage to a minimum value. In another embodiment only one comparator is provided.

Abstract: The circuit for fixing the peak current of an inductor includes an operating current, a ramp-type boost converter and a comparator. The magnitude of the operating current is proportional to that of the voltage source of the inductor. The ramp-type boost converter is connected to the operating current. One input end of the comparator is connected to a reference voltage, and the other end is connected to the output of the ramp-type boost converter. The output of the comparator is connected to the gate of a power transistor, which controls the turn-on time of the inductor.

Abstract: One embodiment of the invention includes a power driver system. The power driver system comprises a power transistor that is activated to provide power to a load and a switching circuit configured to control the power transistor based on a control signal. The power driver system further comprises a control circuit configured to detect a flyback current from the load upon deactivation of the power transistor and to cause the switching circuit to steer the flyback current from a first flyback current path to a second flyback current path in response to detecting the flyback current path. The second flyback current path can have an impedance that is greater than the first flyback current path.

Abstract: A power semiconductor device has first and second power switching elements connected in series, with flywheel diodes, and first and second driver circuits connected to gates of the first and second power switching semiconductor elements. Further, a second diode is connected to a line to be connected to a terminal of at least one of the first and second driver circuits in forward direction such that a current does not flow in the line from the terminal through the second diode. For example, the second diode is connected between a power source terminal of the driver circuit and a controlled power source. In another example, the second diode is connected between an input terminal of the driver circuit and a device for supplying a control signal to the input terminal.

Abstract: In an inductive load driving system, it is configured to comprise a first switching element that is inserted in a position between the external power supply and the inductive load, a second switching element that is inserted in a position between the inductive load and the ground, a return current circuit including a first branch path which diverges at a location between the first switching element and the inductive load to be connected to the ground, that returns counter electromotive current to the ground when the second switching element is turned on, and a counter electromotive current reduction circuit including a second branch path which diverges at a location between the inductive load and the second switching element to be connected to the external power supply, that reduces the counter electromotive current to the external power supply when the first and second switching elements are turned off.

Abstract: A low differential output voltage circuit having a voltage generator and a differential output unit is provided. The voltage generator includes a first PMOS transistor, a first amplifier circuit, a unit gain stage, a first NMOS transistor, a second NMOS transistor. The differential output unit includes a first controlled current source, a second controlled current source, a common voltage circuit, a first switch, a second switch, a third switch, and a fourth switch. Due to the voltage generator directly provides a common mode voltage to the differential output unit, and the first amplifier circuit and the unit gain stage could overcome a channel modulation effect of MOS transistors and enhance the driving ability of the common mode voltage respectively. Thus, a response time of the invention is decreased, and an output current of the differential output unit is in a proportion to the reference current received by the voltage generator.