Abstract: A frequency divider and a method for frequency division are disclosed that can achieve a balanced duty cycle when performing a frequency division with an odd division ratio, independently of an input frequency.

Abstract: A frequency converting circuit that outputs an output signal obtained by mixing a first input signal and a second input signal, has: a first input terminal to which the first input signal is input; a second input terminal to which the second input signal is input; an output terminal from which the output signal is output; a frequency converting element that has a first input part connected to the first input terminal and an output part connected to the output terminal, restricts the signal input to the first input part according to a signal input to a second input part and outputs the restricted signal to the output part; and a pulse controlling circuit that receives the second input signal via the second input terminal and outputs a pulse signal obtained by restricting the pulses of the second input signal to the second input part of the frequency converting element.

Abstract: A pulse width modulation (PWM) frequency converter converts an input PWM signal to an output PWM signal having a different frequency while maintaining a substantially equal duty ratio. The PWM frequency converter samples the input PWM signal for a PWM cycle using a sampling clock. A filter module filters the resulting set of one or more PWM parameters to compensate for noise introduced by potential clock mismatch, clock jitter, ambient variations, and other non-deterministic issues, thereby generating filtered PWM parameters. The sampling employed by the filter module compares a difference between the one or more current PWM parameters and previous (or historical) PWM parameters from an earlier sampled PWM cycle to a predetermined change threshold in determining a filtered set of one or more PWM parameters. The filtered set of one or more PWM parameters then is used to generate one or more corresponding PWM cycles of the output signal.

Abstract: A delta-sigma modulator is used to generate a dithered clock. The dithered clock is provided as a switching signal to a charge pump to create an output voltage having a reduced noise spectrum. The charge pump may be a regulated charge pump, an unregulated charge pump, a buck charge pump, a boost charge pump, a single phase charge pump, a multi-phase charge pump, or a combination thereof.

Abstract: A device and method for regulating the output of a power circuit is provided, which in one embodiment includes a pulsewidth modulation (PWM) circuit that produces pulses each having a period of at least a minimum duration, a comparator circuit that produces a control signal, a timer initiated at the output of each pulse and operable to expire no later than expiration of twice the minimum pulsewidth duration, and wherein the PWM circuit is operable to reduce the frequency of outputted pulses in response to receiving the control signal having a first state at expiration of the first timer initiated at the output of a first pulse.

Abstract: A spread spectrum clock generator includes a triangular wave generator, a digital wave modulator, a sigma delta modulator, and a selector. The triangular wave generator transforms one of the input clock signals into an original triangular wave signal, in which the input clock signals have the same frequency and phases different from each other. The digital wave modulator adjusts the waveform of the original triangular wave signal to generate an adjusted triangular wave signal and a first square wave signal according to an inputted control signal. The sigma delta modulator, electrically connected to the digital wave modulator, accumulates magnitude values of the adjusted triangular wave signal to generate a second square wave signal. The selector selects one of the input clock signals as an output clock signal based on voltage levels of the first square wave signal and the second square wave signal.

Abstract: In one embodiment of the invention, a method for convolution of signals is disclosed including generating four phased half duty cycle clocks each being out of phase by a multiple of ninety degrees from the others; coupling the four phased half duty cycle clocks into a four phase half duty cycle mixer; and switching switches in the four phase half duty cycle mixer in response to the four phased half duty cycle clocks to convolve a differential input signal with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port.

Abstract: A voltage droop monitoring and correcting circuit for a microprocessor includes: a monitor circuit configured to monitor voltage droops of the microprocessor and perform a temporary clock-skipping technique to compensate for the voltage droops. A method for monitoring and correcting voltage droops of a microprocessor includes: monitoring voltage droops of the microprocessor; and performing a temporary clock-skipping technique to compensate for the voltage droops. A computer system includes memory; a processor operatively connected to the memory; and computer-readable instructions stored in the memory for causing the processor to: monitor voltage droops of the microprocessor; and perform a temporary clock-skipping technique to compensate for the voltage droops.

Abstract: Aspects of the disclosure provide a clock gate circuit for generating a clock signal. The clock gate circuit can include a multiplexer configured to receive a first logic signal at a first data input, a second logic signal at a second data input, and a reference clock signal at a selector input, and to output the clock signal having a logic state selected from one of the first logic signal or the second logic signal based on transitions of the reference clock signal. Further, the clock gate circuit can include a logic module coupled to the multiplexer and configured to output the first logic signal and the second logic signal based on an enable signal and the output of the multiplexer.

Abstract: A band converted signal generator includes a low range characteristic application section (16) as a component emphasis means emphasizing only one or more specific frequency components selected from among frequency components of an input signal; and a low pass filter (17) as a component extraction means extracting a signal component of a desired frequency band from an output signal supplied from the low range characteristic application section (16). A band extender (1000) includes the above-mentioned band converted signal generator, and an adder (15) adding the input signal, a certain frequency band of which is suppressed, and a signal including at least one component generated within the certain frequency band which is suppressed.

Abstract: An oscillation frequency control circuit configured to control a frequency of a second clock signal of an oscillation circuit generating and outputting the second clock signal having a frequency in response to an input control signal is disclosed. The oscillation frequency control circuit includes a frequency difference detection circuit unit configured to detect a difference between a frequency of a predetermined first clock signal input externally and the frequency of the second clock signal, and generate and output a signal indicating a result of the detection; and a frequency control circuit unit configured to control the frequency of the second clock signal so that the frequency of the second clock signal continually changes back and forth between a predetermined lower limit value and a predetermined upper limit value in response to the output signal from the frequency difference detection circuit.

Abstract: A constant voltage boost power supply according to an aspect of the invention includes a voltage-controlled variable frequency oscillator that produces and supplies a clock signal and changes an oscillating frequency of the supplied clock signal according to an input control voltage; a charge pump into which the clock signal is fed, the charge pump performing a pumping operation in synchronization with the clock signal to boost an input voltage and supply an output voltage in which the input voltage is boosted; a voltage dividing circuit that divides the output voltage of the charge pump to supply a monitor voltage; and a differential amplifier into which the monitor voltage and a reference voltage are fed, the differential amplifier amplifying a potential difference between the monitor voltage and the reference voltage to supply the control voltage.

Abstract: A frequency synthesizer includes first and second frequency dividers for receiving and frequency-dividing a signal generated by a voltage-controlled oscillator, a frequency mixer for mixing output signals of the first and second frequency dividers, and a third frequency divider for receiving and frequency-dividing a signal having one frequency of two frequencies that are output by the frequency mixer. The first, second third and frequency dividers and the frequency mixer are provided in a feedback loop within a PLL circuit between the voltage-controlled oscillator and the phase comparator. The phase comparator has a first input terminal to which a signal to which a signal that is output by the third frequency divider is input and a second input terminal to which a reference clock signal that is output by a reference signal generator is input. A loop filter supplies the voltage-controlled oscillator with a voltage that is based upon result of the phase comparison by a phase comparator.

Abstract: A pulse width modulation (PWM) frequency converter converts an input PWM signal to an output PWM signal having a different frequency while maintaining a substantially equal duty ratio. The PWM frequency converter samples the input PWM signal for a PWM cycle using a sampling clock. A filter module filters the resulting set of one or more PWM parameters to compensate for noise introduced by potential clock mismatch, clock jitter, ambient variations, and other non-deterministic issues, thereby generating filtered PWM parameters. The sampling employed by the filter module compares a difference between the one or more current PWM parameters and previous (or historical) PWM parameters from an earlier sampled PWM cycle to a predetermined change threshold in determining a filtered set of one or more PWM parameters. The filtered set of one or more PWM parameters then is used to generate one or more corresponding PWM cycles of the output signal.

Abstract: Disclosed is an SSC controller that exercises control to supply a control signal to a phase interpolator which receives an input clock signal and varies the phase of an output clock signal in accordance with the control signal, and to frequency-modulate the output clock signal. In an SSC controller, a counting operation control circuit outputs a counting operation control signal that controls count enable and disable. A p-counter receives a frequency-divided clock signal from a frequency divider and counts the signal when the counting operation control signal from the counting operation control circuit indicates count enable. Upon counting up to a predetermined first value, the counting operation control circuit generates a first output signal and sets its count value to zero. When the counting operation control signal indicates count disable, the p-counter stops counting.

Abstract: A signal frequency change circuit is presented. The signal frequency change circuit includes a delay line, a detector, a controller, a multiplexer, and an output unit. The delay line delays a clock signal by a first delay time corresponding to a delay control signal to generate a delay signal and delays the clock signal by a second delay time shorter than a first delay time to generate a pre-frequency change clock signal. The detector generates a phase locked completion signal. The controller sequentially shifts the delay control signal and a multiplexing control signal. The multiplexer selects and outputs one of the pre-frequency change clock signals. The output unit generates a frequency change clock signal.

Abstract: A digitally controlled frequency generator includes an oscillator module for generating a first clock signal having an oscillating frequency, a programmable control module operable so as to generate a control signal corresponding to a desired frequency, and a direct digital frequency synthesizer coupled to the oscillator module and the programmable control module for receiving the first clock signal and the control signal therefrom, and for generating a second clock signal having the desired frequency based on the first clock signal from the oscillator module and the control signal from the programmable control module.

Abstract: A method of saving power in a digital circuit driven by a clock running at a rate R, comprising reducing said rate R to a lower rate R? during periods when said digital circuit is operating at a capacity less than its maximum capacity, and wherein the change from rate R to rate R? is carried out as a smooth transition.

Abstract: A signal frequency change circuit is presented. The signal frequency change circuit includes a delay line, a detector, a controller, a multiplexer, and an output unit. The delay line delays a clock signal by a first delay time corresponding to a delay control signal to generate a delay signal and delays the clock signal by a second delay time shorter than a first delay time to generate a pre-frequency change clock signal. The detector generates a phase locked completion signal. The controller sequentially shifts the delay control signal and a multiplexing control signal. The multiplexer selects and outputs one of the pre-frequency change clock signals. The output unit generates a frequency change clock signal.

Abstract: A frequency divider including at least one frequency divider cell having an adjustable circuit configuration which may be selected adaptively according to properties of an oscillator signal to be frequency-divided in the frequency divider. Accordingly, the circuit configuration of the frequency divider may be changed on the fly during the operation.

Abstract: The present invention relates to an apparatus for frequency conversion, comprising: an analog-to-digital (A/D) converter, receiving and sampling an input signal according to a sampling frequency for producing a first digital signal, and the sampling frequency and the frequency of the input signal having a correspondence; a sign conversion circuit, used for receiving the first digital signal, and performing a sign conversion on the first digital signal and producing a second digital signal; a first switching module, used for selecting one of the first digital signal and the second digital signal as an output signal according to the sampling frequency; a filter, coupled to the first switching module, used for filtering the output signal from the first switching module, and producing a filter signal; and a second switching module, coupled to the filter, used for outputting the filter signal to a first output path or a second output path alternately according to the sampling frequency.

Abstract: A polyphase numerically controlled oscillator is disclosed. An input signal is received at a phase accumulator. The phase accumulator provides a phase to a phase interpolator. The phase interpolator then provides a plurality of output phases. The plurality of output phases are provided to a plurality of phase to amplitude converters. Each of said plurality of phase to amplitude converters process one of said plurality of output phases.

Abstract: An apparatus and method for converting an input frequency signal to an output frequency signal is able to detect and lock onto the phase and frequency of the input signal by using a fractional-N divider phase-locked loop configuration, in which a frequency division signal is generated having an on time that is independent of the division ratio of a fractional-N divider.

Abstract: An apparatus and a method are disclosed wherein a clock generator component converts a received clock signal into a plurality of internal clock signals which are skewed in time, a phase difference component computes phase differences at subsequent clock phases of a received phase signal, an intermediate averaging component receives each phase difference signals and outputs their average, a threshold detection component detects steady phase changes and activates a preamble detect signal which is used to clock an output filter that smoothes the output from the intermediate averaging component. The output is a frequency correction signal that is used by a wireless receiver to correct its reception process. The disclosed invention merges the frequency correction process more quickly and accurately, is less likely to trigger on noise and has a lower packet error rate than conventional systems.

Abstract: A high speed divider circuit is disclosed. The circuit contains a plurality of latches and buffers. The maximum input clock frequency of the divider circuit is increased over that implemented with only latches connected in a ring by feed forwarding the output of an early switching latch to the output of a later switching latch through buffers. The feed forward signal aids the later switching latch to complete the next state transition. By choosing the appropriate ratio of the buffer tail current to the latch tail current, the divider circuit can be made into a dynamic divider circuit.

Abstract: In an integrated circuit with at least two separate timing circuits, for example both a serializer and a deserializer, a trim value correction factor is developed and applied at the testing of the chip. The correction trim value brings the VCO frequency of the serializer into specifications, but the trim value may also be used to alter the delay between a received clock and data in the deserializer. Since both the serializer and the deserializer were made with the same process, the received clock delay may be corrected by substantially the same correction factor as that applied to the VCO. Illustratively the trim values may be stored on the IC.

Abstract: A frequency-hopping pulse-width modulator is disclosed, which facilitates a switching regulator to use smaller-size inductive and capacitive elements, to have an improved power efficiency at light load, as well as predictable spectrum at different load levels. The improved modulator automatically determines the switching frequency of a switching regulator according to the load current delivered by the switching regulator from a number of pre-defined frequencies, which are all multiples of a fundamental frequency. By designing the maximum switching frequency of frequency-hopping pulse-width modulator in the MHz range, a switching regulator is able to use smaller-size inductive and capacitive elements. Light-load efficiency of the switching regulator with the frequency-hopping pulse-width modulator is also greatly improved as switching frequency of such switching regulator is reduced with decreased load current.

Abstract: Methods and apparatus nullify an intrinsic jitter component in a digital clock recovery circuit induced by a time base frequency difference between an incoming data signal and a local synchronization clock for the digital clock recovery circuit. The techniques disclosed herein permit a recovered clock signal to be digitally filtered and applied to the digital clock recovery circuit clock synthesis unit (CSU) as a synchronization reference clock signal, which advantageously eliminates a time base frequency difference to reduce that jitter component and also reduces an intrinsic jitter component associated with jitter already present in the incoming data signal. In one embodiment, a state machine uses a filtered version of a recovered clock signal as a reference when the frequency of the filtered version of the recovered clock signal is relatively close to the frequency of the CSU reference clock signal.

Abstract: A design structure for a circuit for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler is provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop ensures the duty cycle lock. The VCO is modified to have an additional control port to adjust the duty cycle. Thus, the VCO has one control port for performing frequency adjustment and one control port for duty cycle adjustment. As a result, both the duty cycle and the frequency may be controlled using the VCO of the PLL circuit of the illustrative embodiments so as to achieve any desired duty cycle output without requiring a VCO pre-scaler circuit or duty cycle correction circuit.

Abstract: A Pseudo Random Bit Sequence (PRBS) generator is provided with components to enable operation at very high microwave frequencies with inexpensive components. The PRBS generator initially replaces the D flip-flops of a conventional PRBS generator with delay lines connected in a similar manner. Further, an exclusive OR (EXOR) gate used in a conventional device is replaced in one embodiment by a mixer and amplifier. In another embodiment, the EXOR gate is replaced by a Gilbert Cell. In some embodiments, complementary outputs of an EXOR gate are connected to separate delay lines to reduce components needed for the PRBS generator.

Abstract: A spread spectrum clock generator is provided which improves the spread spectrum effect with little increasing the circuit cost by modifying the shape of a triangular wave used for frequency modulation by a simple method. The output signal of the modulation waveform generating circuit has such a modulation waveform as indicated by solid lines in FIG. 2A. The modulation waveform is input to a VCO (voltage-controlled oscillator). In response to the modulation waveform, the oscillation frequency of the VCO is modulated, and the output clock that varies its frequency as illustrated in FIG. 2B is obtained. The frequency transition of the output clock involves such temporal variations as indicated by solid lines in FIG. 2C.

Abstract: A clock modulation circuit includes a modulation block that receives a fixed clock generated from a reference clock and buffers the fixed clock so as to generate a modulated clock. A correction unit is provided in the modulation block to correct the duty ratio of the modulated clock.

Abstract: A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected.

Abstract: An oscillator includes a first circuit that asynchronously generates an oscillating signal in response to a second circuit of the oscillator acknowledging each cycle of the oscillating signal.

Abstract: A charge pump clock circuit for a memory device generates pump clock signals at an adaptive rate. Clock edges are generated at a minimum of TD seconds apart so long as address transitions do not exceed a pre-determined limit. However, if address changes are occurring more frequently than this limit, i.e., 1/(2*TD), then clock edges will be generated at a rate that is proportional to the rate of address changes, where TD is approximately half of the address period. Two logic rules are implemented in hardware or equivalent software to make the clock signal adjustments.

Abstract: Disclosed is a spread spectrum clock generator comprising a phase interpolator, which receives a clock signal from a clock input terminal and a control signal (an up signal and/or down signal), for adjusting the phase of an output clock signal in accordance with said control signal and outputting the resultant clock signal, and a control circuit receiving and counting the clock signal that enters from the clock input terminal and outputting said control signal (up signal or down signal), which is for varying the phase of the output clock signal based upon the result of the count, to the phase interpolator. The phase of the output clock signal from the phase interpolator varies with time and the output clock signal is frequency-modulated within a prescribed frequency range.

Abstract: A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected.

Abstract: Embodiments of the present invention include first and second pulse trains input to a switch in synchronization. The first and second pulse trains may have a repeating high and low values at first and second frequencies, respectively, and the first pulse train may transition from the low to the high value with a first edge sharpness. The second pulse train input may have a lower than the first frequency. The switch may use a selection signal in synchronization with the first pulse train to select an output from the first or second pulse train to create an output pulse train appropriate to transition fault test an integrated circuit. The switch may switch from the second pulse train to the first pulse train and substantially maintain the first edge sharpness of the first pulse train during a low value of both the first and second pulse trains.

Abstract: A frequency conversion apparatus has a high-frequency amplifier for amplifying an input high-frequency signal, a mixer for mixing the output signal of the high-frequency amplifier with a local oscillation signal, a filter for restricting the band of the output signal of the mixer to permit passage of only components within a predetermined band, and a variable filter provided between the high-frequency amplifier and the mixer and having a controllable cut-off frequency. With this configuration, it is possible to reduce back talk at low cost without inviting variation of input return loss characteristics.

Abstract: A system and method of shifting a clock frequency of an integrated circuit device from a first frequency to a second frequency, including alternating between the first frequency and the second frequency according to a dithering pattern, the alternating occurring for a predetermined number of cycles; and setting the clock frequency to the second frequency after the predetermined number of cycles.

Abstract: Systems, methodologies, media, and other embodiments associated with making a frequency change through frequency synthesis and digital selection of out-of-phase synthesized signals are described. One exemplary system embodiment includes a locked loop logic (e.g., phase locked, delay locked) that may receive a reference clock signal, process the reference clock signal into signals with different phases, and make those signals available to a selection logic. The exemplary system may also include a state logic that stores frequency divisors that facilitate selecting and tracking output signals provided by the selection logic. The exemplary system may also include a phase logic that stores output signal phase data associated with computing, describing, and/or selecting an output signal.

Abstract: A clock generating circuit includes a delay circuit which has input terminals and which delays a signal input from each of the input terminals by a different delay time, and outputs the delayed signal from at least one output terminal, a selective circuit which receives an input clock signal and selectively outputs the clock signal to one of the input terminals of the delay circuit, and a control circuit which switches selective operations of the selective circuit. A modulated clock signal in which the period of the clock signal is increased or decreased is output from the at least one output terminal of the delay circuit such that the control circuit sequentially switches the selective operations of the selective circuit.

Abstract: In a method for generating a scanning clock signal (S) for scanning an analog signal (Ua) for an analog-to-digital converter (20) operating according to the sigma-delta method, a variable period (T; T*) of the power supply system (PL) is ascertained in time units of a system clock signal (C), and the scanning clock signal (S) is generated by distributing a constant number K of pulses over the ascertained period (T; T*), so that the frequency of the scanning clock signal (S) is an integer multiple of the frequency of the power supply system (PL). The method is essentially able to be carried out by an accumulator unit (4) connected to a counter (3) and makes possible the advantage that during the analog-to-digital conversion a mains hum contained in the analog signal (Ua) is suppressed.

Abstract: A circuit for changing clocks includes a clock generating circuit which generates an output clock signal by controlling a frequency of an original clock signal, and a control circuit which controls the clock generating circuit in response to an operation mode change signal indicative of a change from a first operation mode to a second operation mode of an external circuit operating based on the output clock signal, thereby changing the output clock signal from a first frequency corresponding to the first operation mode to an intervening frequency and then from the intervening frequency to a second frequency corresponding to the second operation mode, the intervening frequency having a frequency between the first frequency and the third frequency.

Abstract: In a circuit for converting an input signal Data1 of high frequency to an output signal Data4 of low frequency, a signal of the frequency band (for example, 10 GHz to 2.5 GHz) which can be processed only with a bipolar ECL circuit is processed with a bipolar ECL circuit. After the frequency of signal up to the maximum frequency which can be processed with a CMOS circuit is lowered, the signal is inputted to the CMOS circuit via a level conversion circuit in order to lower the frequency (for example, 2.5 GHz to 1.25 GHz). Thereby, power consumption of the semiconductor integrated circuit device, particularly the device including the Bi-CMOS circuit can be lowered while high-seed processing characteristic in the signal process of the circuit is maintained.

Abstract: A micro-controller adjustably provides a scanning frequency for operating a driver for an ultrasonic device. The frequency is adjusted within a defined range until an acknowledgement signal is provided to the micro-controller to lock a currently selected frequency as the operating frequency. An indicator indicates when a frequency has been selected outside of the defined range. The device is preferably implemented as a complex programmable logic device (CPLD).

Abstract: A device generating a pulse signal includes at least one first register which stores waveform data therein, a pulse signal generation unit which generates a pulse signal in accordance with the waveform data of the first register, a control unit which is connected to a bus, and is controlled by control signals supplied from the bus, and a signal line which is separate from and independent of the bus, and is connected to the control unit, wherein the control unit updates the waveform data of the first register in response to a signal that is externally supplied through the signal line.

Abstract: A signal generator generates an output signal with a programmable duty cycle and includes a first buffer which generates in response to an input signal an intermediate signal having a selected edge with a voltage slope selected to vary a length of a selected phase of the output signal. A second buffer having a selected input voltage threshold generates the output signal in response to the intermediate signal.

Abstract: In a circuit for converting an input signal Data1 of high frequency to an output signal Data4 of low frequency, a signal of the frequency band (for example, 10 GHz to 2.5 GHz) which can be processed only with a bipolar ECL circuit is processed with a bipolar ECL circuit. After the frequency of signal up to the maximum frequency which can be processed with a CMOS circuit is lowered, the signal is inputted to the CMOS circuit via a level conversion circuit in order to lower the frequency (for example, 2.5 GHz to 1.25 GHz). Thereby, power consumption of the semiconductor integrated circuit device, particularly the device including the Bi-CMOS circuit can be lowered while high-seed processing characteristic in the signal process of the circuit is maintained.

Abstract: A clock signal is supplied from a clock oscillator to a gate circuit. In a period in which a reset signal is at the “H” level, the clock signal is supplied to an internal circuit. When the reset signal becomes at the “L” level, a control is performed by a gate control circuit so as to stop the supply of the clock signal. Consequently, even when a delay signal in the internal circuit becomes longer than one cycle of the clock signal, occurrence of an erroneous operation can be prevented.