Abstract: Radio frequency (RF) mixer circuits having a complementary frequency multiplier module that requires no balun to multiply a lower frequency base oscillator signal to a higher frequency local oscillator (LO) signal, and which has a significantly reduced IC area compared to balun-based frequency multipliers. In one embodiment, the complementary frequency multiplier module includes a complementary pair of FETs controlled by an applied base oscillator signal. The complementary FETs are coupled to a common-gate FET amplifier and alternate becoming conductive in response to the base oscillator signal. The alternating switching of the complementary FETs in response to the opposing phases of the base oscillator signal cause the common-gate FET amplifier to output a higher frequency local oscillator (LO) signal. The LO signal is coupled to the LO input of a mixer or mixer core of a type suitable for use in conjunction with a frequency multiplier.

Abstract: Described are apparatus and methods for low power frequency clock generation and distribution. A device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (FS)(FS/N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential FS/N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.

Abstract: A first logic gate has a first input coupled to a first circuit input or a second circuit input, a second input selectively coupled to a third circuit input or a fourth circuit input, and a first output. The first output has a signal with a duty cycle that is a function of a phase difference between a first signal on the first input and a second signal on the second input. A second logic gate has a third input coupled to the third circuit input or the fourth circuit input, a fourth input coupled to the second circuit input or the fourth circuit input, and a second output. The second output has a signal with a duty cycle that is a function of a phase difference between a third signal on the third input and a fourth signal on the fourth input.

Abstract: An input module of an industrial control apparatus receives a digital signal from an external source, outputs a binary signal as an internal signal, and determines a level of the digital signal based on the internal signal. The input module determines that the digital signal has a low level when a low level of the internal signal continues for a certain time period, determines that the digital signal has a high level when the internal signal switches from the low level to a high level and then switches to the low level again, and determines an occurrence of a fixing failure when the internal signal switches from the low level to the high level and then fails to switch to the low level again.

Abstract: In an embodiment, a circuit for tripling frequency is configured to receive an input voltage (Vin) having a sinusoidal shape and a base frequency. The circuit has a first and a second transistor pair that are cross-coupled, and a trans-characteristics f(Vin) approximating a polynomial nominal trans-characteristic given by f ? ( V in ) = ( 3 A ? V in - 4 A 3 ? V in 3 ) ? g m where A represents an amplitude of the input voltage and gm is a transconductance of transistors of the first and second transistor pairs.

Abstract: An example one-shot circuit includes: circuitry including a set-reset (SR) latch to produce an output pulse of controlled duration in response to an input signal rising edge, where the SR latch includes a first circuit input and a second circuit input; a circuit path to provide a signal to the first circuit input; and a delay element connected to the circuit path and to the second circuit input.

Abstract: In accordance with an embodiment, a method includes: receiving, by an adjustable frequency doubling circuit, a first clock signal having a first clock frequency; using the adjustable frequency doubling circuit, generating a second clock signal having a second clock frequency that is twice the first clock frequency; measuring a duty cycle parameter of the second clock signal, where the duty cycle parameter is dependent on a duty cycle of the first clock signal or a duty cycle of the second clock signal; and using the adjustable frequency doubling circuit, adjusting the duty cycle of the first clock signal or the second clock signal based on the measuring.

Abstract: The present document discloses a circuitry for delaying a digital input signal. In particular, the circuitry may comprise a delay cell circuit and a reciprocal current digital-to-analog converter (DAC). The delay cell circuit may be coupled to the reciprocal current DAC. More particularly, the reciprocal current DAC may be configured to output a charge current to the delay cell circuit according to a value of a control input provided to the reciprocal current DAC. The charge current output by the reciprocal current DAC may be inversely proportional to the value of the control input, wherein the delay depends on the charge current.

Abstract: The present invention relates to a digital clock generation apparatus. The digital clock generation apparatus is directed to providing a digital clock generation apparatus in which hardware is simple, duty cycles are easily controlled, and various duty cycles and various frequency clocks (n× clocks) are provided as compared to a 1× single-phase clock generation apparatus or a 1× multi-phase clock generation apparatus based on the conventional programmable delay element chain.

Abstract: A duty cycle measurement circuit obtains differential duty cycle measurements corresponding to the duty cycle of a signal at two or more different locations along a propagation path. The differential duty cycle measurements may include measurements of an input duty cycle and measurements of an output duty cycle. The duty cycle measurements may be acquired by use of duty-cycle-to-voltage converter circuitry. The duty cycle measurements may be used to determine a measure of the duty cycle deterioration of the propagation path, and an adjustment factor to compensate for the measured duty cycle deterioration.

Abstract: Described herein is an apparatus for the recovery of asynchronous data into a fixed clock domain. A phase-locked loop (PLL) of the known art is replaced by a modified quadrature resolver, and the output from the resolver re-creates the selected frequency component of the input asynchronous data. The zero-crossings of this re-created data clock are used to sample the input data stream. One advantage of this technique is that it operates as a state machine on a single clock, and no analog components such as phase detectors or VCOs are needed. In another embodiment, the samples from the input data stream are changed from pulses to Gaussians, allowing for conversion of the sample rate from one clock domain to another.

Abstract: A time multiplexing circuit applied to a DC-DC converting system including first to third NOR gates, first and second inverters, first and second D-type flip-flops, a NAND gate, an OR gate and an AND gate. The first NOR gate and second NOR gate receive the first and second pulse-width modulation signals respectively and output a boost state request signal and a buck-boost state request signal respectively. The first D-type flip-flop outputs a first time multiplex output signal and a first reverse time multiplex output signal. The second D-type flip-flop outputs a second time multiplex output signal and a second reverse time multiplex output signal. The third NOR gate outputs another first time multiplex output signal. The NAND gate outputs another second time multiplex output signal. The OR gate outputs a first reverse output signal. The AND gate outputs a second reverse output signal.

Abstract: A computing system comprises one or more core processors coupled to a communication network among the cores via a switch in each core and switching circuitry to forward data among cores and switches. Features include a programmable classification processor for directing packets, techniques for managing virtual functions on an IO accelerator card, packet scheduling techniques, multi-processor communication using shared FIFOs, programmable duty cycle adjustment and delay adjustment circuits, a new class of instructions that use a ready bit, and cache coherence and memory ordering techniques.

Abstract: The present technology relates to a phase locked loop and a control method therefor, which are capable of achieving low power consumption and good phase noise while suppressing the growth of circuit area.

Abstract: Electrical circuits and associated methods relate to duty cycle correction having a voltage controlled delay line VCDL controlled by an analog voltage and a digital command signal to generate a VCDLout signal. In an illustrative example, the analog voltage may be generated by an analog circuit, the analog circuit may include a reference voltage, a low-pass filter, an amplifier and a loop filter. In an illustrative example, the analog circuit may be controlled by an analog command signal. The analog command signal may be programmable applied on the analog circuit to produce the analog voltage. The digital command signal may be programmable to select desired delay band in the VCDL. The analog voltage and the digital command signal may be applied to the VCDL together to obtain a desired duty cycle.

Abstract: An integrated frequency quadruplet consists of a pair of balanced frequency doublers that are driven in phase quadrature using a hybrid coupler. This approach results, effectively, in a “unilateral” multiplier that presents a match to the input-driving source, irrespective of the impedance of the doubler stages. The present invention applies this architecture to implement an integrated frequency quadruplet with output frequency of 160 GHz using quasi vertical GaAs varactors fabricated on thin silicon support membranes. The quadruplet has a balanced circuit architecture that addresses degradation issues often arising from impedance mis-matches between multiplier stages. A unique quasi-vertical diode process is used to implement the quadruplet, resulting in an integrated drop-in chip module that incorporates 18 varactors, matching networks and beamleads for mounting. The chip is tailored to fit a multiplier waveguide housing resulting in high reproducibility and consistency in manufacture and performance.

Abstract: A quadrature clock divider circuit includes a divide-by-2 circuit having at least one undivided clock input, and generates at least one quadrature clock component and at least one inverted quadrature clock component, each having a 50% duty cycle. A resync circuit has as inputs the at least one undivided clock input, and the uninverted and inverted quadrature clock components. The resync circuit uses the uninverted and inverted quadrature clock components as selectors to generate, from the undivided clock input signals, at least one second quadrature clock component on a first signal path and at least one second inverted quadrature clock component on a second signal path. The first and second signal paths have a first portion in common, and each of the at least one second quadrature clock component and the at least one second inverted quadrature clock component has a second duty cycle percentage other than 50%.

Abstract: A circuit having a first Gilbert cell mixer of a first type configured to receive phases of first and second signals and output a first current pair to a first node and a second node; a first Gilbert cell mixer of a second type configured to receive output a second current pair to the first node and the second node; a second Gilbert cell mixer of the first type configured to receive phases of the first and second signals and output a third current pair to the first node and the second node; a second Gilbert cell mixer of the second type configured to output a fourth current pair to the first node and the second node; a cross-coupling inverter pair configured to cross couple the first node and the second node; and a load placed across the first node and the second node and configured to resonate at a frequency approximately equal to either a sum of a frequency of the first signal and a frequency of the second signal or a difference of the frequency of the first signal and the frequency of the second signal.

Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

Abstract: A clock generator and method operate by receiving an input clock; cascading a first inverter, a second inverter, a third inverter, and a fourth inverter in a ring topology to output a first phase, a second phase, a third phase, and a fourth phase of an interim clock; enabling the second inverter and the fourth inverter during a first phase of the input clock and enforcing a complementary relation between the second phase and the fourth phase of the interim clock by using a fifth inverter and a sixth inverter configured in a cross-coupling topology; enabling the first inverter and the third inverter during a second phase of the input clock and enforcing a complementary relation between the first phase and the third phase of the interim clock by using a seventh inverter and an eighth inverter configured in a cross-coupling topology.

Abstract: A signal generator generates an output signal according to an oscillating signal. The signal generator has a plurality of edge sampling circuits and an edge combining circuit. Each of the edge sampling circuits receives the oscillating signal, samples the oscillating signal to obtain at least one of a rising edge and a falling edge in one cycle of the oscillating signal, and outputs a sampled signal using the at least one of the rising edge and the falling edge. The edge combining circuit combines a plurality of sampled signals generated by the edge sampling circuits, respectively, to generate the output signal.

Abstract: In some embodiments, a phase locked loop includes a voltage-controlled oscillator whose output is fed back to a first input of a phase comparator via a fractional divider controlled by a delta-sigma modulator. The method of doubling the frequency of the initial reference signal of the phase locked loop involves generating, from the initial reference signal and the output signal furnished by the voltage-controlled oscillator, a secondary reference signal having edges of a first type synchronized with each of the rising and falling edges of the initial reference signal and edges of a second type between the edges of the first type, and a furnishing of the secondary reference signal at a second input of the phase comparator operating on the edges of the first type.

Abstract: An oscillation circuit includes: an oscillator configured to generate N phase clocks (where N is an integer of 2 or more) including a first phase clock to Nth phase clock whose phases are shifted by 360°/N at regular intervals; a pulse generating part configured to receive a plurality of the N phase clocks and generate a plurality of intermediate pulses each having a duty ratio of 25%; and a clock synthesizing part configured to synthesize the plurality of intermediate pulses to generate a single phase output clock or multi-phase output clocks, the single phase output clock and the multi-phase output clocks having a frequency that is twice an oscillation frequency of the oscillator.

Abstract: An electronic system includes a plurality of function modules, each of the plurality of function modules operates according to one of a plurality of clock signals; and a clock management module, for generating the plurality of clock signals according to a plurality of performances requirements of the plurality of function modules.

Abstract: An apparatus includes a phase detector coupled to an output of a frequency multiplier. A digital loop filter is coupled to the phase detector, and a duty cycle correction circuit is coupled to the digital loop filter.

Abstract: A semiconductor device may be provided. The semiconductor device may include an input information signal generation circuit and a command generation circuit. The input information signal generation circuit may be configured to latch a command in synchronization with a point of time that a division clock signal is inputted. The command generation circuit may be configured to shift a phase of the latched command in synchronization with a multiplication clock signal to shift the command.

Abstract: The present invention solves a problem that the phases of clocks obtained by frequency-dividing PLL clocks output from local PLL circuits cannot be made the same in a plurality of data transfer blocks. A local PLL circuit outputs a PLL clock obtained by multiplying a common external clock. A frequency divider outputs a feedback clock obtained by frequency-dividing the PLL clock to the local PLL circuit. An FIFO buffer temporarily holds data input from the outside. The FIFO buffer outputs the held data on the basis of a frequency-divided PLL clock. A clock generator generates a frequency-divided PLL clock obtained by frequency-dividing the PLL clock. The clock generator controls the phase of the frequency-divided PLL clock on the basis of a common start signal.

Abstract: A transformer-less DFM device comprising: an input receiving signals that are an integer multiple of an input signal; an edge detector that provides a quantized or a state output comparing an the input signal to a feedback signal; a statemachine that has counters and decimation circuits to provide a digitized output to a DAC that tunes delays between the input/output signals; a DLL for generating delay signals from the input signal that form an input to an edge combiner wherein the edge combiner takes different phases from the DLL to generate a multiplied output signal; a first DAC that takes the signal from the statemachine and provide a control to a supply circuit of the DLL to adjust a delay through a supply voltage; a second DAC that takes a signal from the statemachine and provides control to a backgate circuit of the DLL to adjust the delay.

Abstract: A regenerative frequency divider comprising an in-phase mixer circuit and a phase-shifted mixer circuit. At least one switching device of the in-phase mixer circuit is of a smaller scale than a corresponding switching device of the transconductance component of the in-phase mixer circuit. In some examples, at least one switching device within an input switching stage of the regenerative frequency divider forming part of the phase-shifted mixer circuit is of a smaller scale than a respective corresponding switching device within the input switching stage forming part of the in-phase mixer circuit. In some further examples, all switching devices within the phase-shifted mixer circuit are of a small scale than respective corresponding switching devices within the in-phase mixer circuit.

Abstract: Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.

Abstract: Disclosed herein are an apparatus for controlling a solenoid valve and a control method thereof. The apparatus for controlling the solenoid valve, which controls the solenoid valve including a solenoid coil, includes a switching part configured to switch a current supplied to the solenoid coil; a pre-driver configured to output a driving signal for driving the switching part; and a microcontroller unit (MCU) configured to control the pre-driver so that a frequency of the driving signal output from the pre-driver to the switching part is randomly varied.

Abstract: The invention relates to a device for protecting at least one active component of an electronic module, able to receive a microwave electromagnetic signal as input and to provide a microwave electromagnetic signal to said at least one active component. This device includes a delay module able to apply a predetermined delay time to the microwave electromagnetic input signal, connected in parallel with a switch-triggering device able to compare a power level of the microwave electromagnetic input signal to a power threshold and to command switching by a switch connected at the output of the delay module, an output of said switch providing the microwave electromagnetic signal to said at least one active component, the predetermined delay time being such that the switching is done before the arrival of the microwave electromagnetic output signal from the delay module.

Abstract: Wideband polar receivers and method of operation are described. A phase-modulated input signal is received at a polar receiver that includes an injection-locked oscillator. The injection-locked oscillator includes a plurality of injection points. Based on the frequency of the input signal, a particular Nth harmonic is selected, and the input signal is injected at the set of injection points corresponding to the selected Nth harmonic. The injection-locked oscillator generates an oscillator output signal, and the phase of the input signal is determined from the phase of the oscillator output signal. In some embodiments, the oscillator output signal is frequency-multiplied by N, mixed with the input signal, and filtered for use in amplitude detection. The input signal is decoded based on the phase and amplitude information.

Abstract: A duty cycle detector may include a rising clock detection unit enabled in response to a first control signal; a falling clock detection unit enabled in response to a second control signal with a different activation timing from the first control signal; and a comparison unit configured to compare an output signal of the rising clock detection unit to an output signal of the falling clock detection unit in response to a comparison enable signal, and output a duty cycle detection signal.

Abstract: A frequency multiplication circuit includes a delay circuit that has a clock signal having a period input thereto and delays the signal by a time, an exclusive OR circuit that has the clock signal and a signal from the delay circuit input thereto and outputs a signal serving as an exclusive OR between the clock signal and the signal from the delay circuit, and a signal correction circuit that has a signal from the exclusive OR circuit input thereto and corrects the input signal to output the resultant. The length of the time is a length other than n×T/4 (n is an integer). The signal correction circuit attenuates a signal having a second frequency based on T/2, rather than a signal having a first frequency based on the time ?.

Abstract: Methods for frequency multiplying include receiving a signal having an input frequency at a frequency multiplier comprising a pair of transistors; and selecting a harmonic in the signal by connecting the transistors to a common impedance through a respective collector impedance, wherein an output frequency at the harmonic between the collector impedances and the common impedance is an even integer multiple of an input frequency.

Abstract: In an embodiment, an electronic device includes an integrated circuit (IC) having a plurality of power domains, a first regulator coupled to a given power domain, a second regulator coupled to the given power domain, and a switching circuit coupled between the first and second regulators and configured to control an amount of current drawn by the power domain from the first and/or second regulators. In another embodiment, a method includes controlling an impedance of a switching circuit to change an amount of current, the switching circuit coupled to a given power domain of an IC configured to operate in a first mode followed by a second mode, where the switching circuit is coupled to a first regulator configured to provide more power to the IC than a second regulator, and a transition period includes turning off the first regulator and turning on the second regulator.

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus outputs a sinusoidal signal according to a first clock frequency, generates, a first digital signal having a 25% duty cycle based on the sinusoidal signal, generates a second digital signal having a 25% duty cycle based on the sinusoidal signal, combines the first digital signal and the second digital signal to generate a combined digital signal having a 50% duty cycle and a second clock frequency that is double the first clock frequency, and doubles the second clock frequency of the combined digital signal to generate an output signal having a third clock frequency that is quadruple the first clock frequency. The apparatus further generates a first control voltage and a second control voltage for the first buffer and a third control voltage for the second buffer based on the output signal.

Abstract: Capacitance multiplier circuitry provides an increased equivalent capacitance, and may be implemented using a desirably small footprint. As may be implemented in accordance with one or more embodiments, a capacitor provides a first capacitance across first and second plates, and capacitance multiplier circuitry operates with the capacitor to provide a second equivalent capacitance that is a multiple of the first capacitance. The capacitance multiplier circuitry includes a first circuit path having a first resistor between the first plate and a common terminal, and a second circuit path having a switch and a second resistor between the second plate and the common terminal. An amplifier has differential inputs respectively corresponding to the first and second circuit paths and provides the second equivalent capacitance by controlling operation of the switch based upon the differential inputs and the respective resistances provided by the resistors in the first and second circuit paths.

Abstract: A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.

Abstract: Frequency multipliers include a pair of transistors each connected to a common impedance through a respective collector impedance formed from a transmission line. Each transmission line has a length between about one quarter and about one eighth of a wavelength of an input signal frequency and is tuned to produce a large impedance at a collector of the respective transistor at the input signal frequency. The output frequency between the collector impedances and the common impedance is an even integer multiple of the input frequency.

Abstract: A circuit that regulates electrical current flow through an integrated circuit involves a sequencing circuit connected to a clock signal generator, the sequencing circuit configured to, responsive to receiving a clock signal from the clock signal generator, generate a set of sequencing signals that includes a first switching signal, a second switching signal, and a disable signal. The circuit also involves a switching circuit connected to the sequencing circuit, the switching circuit configured to receive the first switching signal and the second switching signal and a current mirror connected to the switching circuit and the sequencing circuit, the current mirror configured to receive an activation signal from a current control logic circuit and to receive the disable signal.

Abstract: A frequency doubler includes a voltage controlled oscillator outputting N (where, N is a natural number) signals having a first period and having different phases, and an XOR circuit receiving the N signals and outputting a signal having a second period that corresponds to a half of the first period, wherein the voltage controlled oscillator includes N nodes that correspond to the N signals and inverter units respectively connecting the N nodes, the N nodes are arranged so that, if a signal that starts from any one start node of the N nodes passes through the same number of the inverter units, it recurs to the corresponding start node, the XOR gate includes a first unit block set including N unit blocks that are connected to the same output node and match the N nodes in a one-to-one manner, and a second unit block set that is substantially the same as the first unit block set, wherein the first and second unit block sets share the output node.

Abstract: A circuit may include a pulse generation circuit configured to receive a first clock signal with a first-clock rate and a first-clock duty cycle. The pulse generation circuit may be configured to generate, based on the first clock signal, a pulse signal with a pulse frequency and with a pulse duty cycle that is smaller than the first-clock duty cycle. The circuit may also include a sub-harmonic injection locking oscillator configured to receive the pulse signal. The sub-harmonic injection locking oscillator may be configured to output, based on the pulse signal, a second clock signal with a second-clock rate that is greater than the first-clock rate and greater than the pulse frequency.

Abstract: Apparatuses and methods for mitigating uneven circuit degradation of delay circuits are disclosed. In an example method, an imbalance in transistor threshold voltages is detected between a transistor of a first delay circuit and a transistor of a second delay circuit that is series coupled to the first delay circuit, and a clock level of an input clock signal to the first delay circuit is switched responsive to detecting the imbalance.

Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Abstract: A method includes providing a first local oscillator signal having a first duty cycle to a first mixer unit and providing a second local oscillator signal having a second duty cycle to a second mixer unit. At least one of the first duty cycle or the second duty cycle is greater than fifty percent. A frequency of the first local oscillator signal approximately equals a frequency of the second local oscillator signal. The method may also include generating a modulated output signal based on an output signal of the first mixer unit and based on an output signal of the second mixer unit.

Abstract: Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an input clock signal and for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal, the input clock signal having a non-50% duty cycle and a first period; and a second logic unit to compute a falling edge of the output clock signal according to the detected rising edge of the input clock signal, the falling edge of the output clock signal being near half of the first period.

Abstract: A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.

Abstract: A frequency tripler device is disclosed. The frequency tripler device includes a first graphene based field effect transistor (FET) of a first dopant type, having a gate, a drain, and a source, and a second graphene based FET of a second dopant type, having a gate, a drain, and a source, the gate of the first FET coupled to the gate of the second FET and coupled to an input signal having an alternating current (AC) signal of a first frequency, the combination of the first and second FETs generates an output signal with a dominant AC signal of a frequency of about three times the first frequency.