Frequency Multiplication Patents (Class 327/116)
  • Patent number: 10545905
    Abstract: A computing system comprises one or more core processors coupled to a communication network among the cores via a switch in each core and switching circuitry to forward data among cores and switches. Features include a programmable classification processor for directing packets, techniques for managing virtual functions on an IO accelerator card, packet scheduling techniques, multi-processor communication using shared FIFOs, programmable duty cycle adjustment and delay adjustment circuits, a new class of instructions that use a ready bit, and cache coherence and memory ordering techniques.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: January 28, 2020
    Assignee: Mellanox Technologies Ltd.
    Inventors: Andrew Carlson, Shane Bell
  • Patent number: 10523219
    Abstract: The present technology relates to a phase locked loop and a control method therefor, which are capable of achieving low power consumption and good phase noise while suppressing the growth of circuit area.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: December 31, 2019
    Assignee: SONY CORPORATION
    Inventors: Masahisa Tamura, Shunsuke Sakazume, Takeshi Matsubara, Ken Yamamoto
  • Patent number: 10498318
    Abstract: Electrical circuits and associated methods relate to duty cycle correction having a voltage controlled delay line VCDL controlled by an analog voltage and a digital command signal to generate a VCDLout signal. In an illustrative example, the analog voltage may be generated by an analog circuit, the analog circuit may include a reference voltage, a low-pass filter, an amplifier and a loop filter. In an illustrative example, the analog circuit may be controlled by an analog command signal. The analog command signal may be programmable applied on the analog circuit to produce the analog voltage. The digital command signal may be programmable to select desired delay band in the VCDL. The analog voltage and the digital command signal may be applied to the VCDL together to obtain a desired duty cycle.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 3, 2019
    Assignee: XILINX, INC.
    Inventors: Jaewook Shin, Didem Z. Turker Melek, Parag Upadhyaya
  • Patent number: 10425040
    Abstract: An integrated frequency quadruplet consists of a pair of balanced frequency doublers that are driven in phase quadrature using a hybrid coupler. This approach results, effectively, in a “unilateral” multiplier that presents a match to the input-driving source, irrespective of the impedance of the doubler stages. The present invention applies this architecture to implement an integrated frequency quadruplet with output frequency of 160 GHz using quasi vertical GaAs varactors fabricated on thin silicon support membranes. The quadruplet has a balanced circuit architecture that addresses degradation issues often arising from impedance mis-matches between multiplier stages. A unique quasi-vertical diode process is used to implement the quadruplet, resulting in an integrated drop-in chip module that incorporates 18 varactors, matching networks and beamleads for mounting. The chip is tailored to fit a multiplier waveguide housing resulting in high reproducibility and consistency in manufacture and performance.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: September 24, 2019
    Assignee: UNIVERSITY OF VIRGINIA PATENT FOUNDATION
    Inventors: Naser Alijabbari, Robert M. Weikle, II, Matthew Bauwens
  • Patent number: 10367487
    Abstract: A quadrature clock divider circuit includes a divide-by-2 circuit having at least one undivided clock input, and generates at least one quadrature clock component and at least one inverted quadrature clock component, each having a 50% duty cycle. A resync circuit has as inputs the at least one undivided clock input, and the uninverted and inverted quadrature clock components. The resync circuit uses the uninverted and inverted quadrature clock components as selectors to generate, from the undivided clock input signals, at least one second quadrature clock component on a first signal path and at least one second inverted quadrature clock component on a second signal path. The first and second signal paths have a first portion in common, and each of the at least one second quadrature clock component and the at least one second inverted quadrature clock component has a second duty cycle percentage other than 50%.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: July 30, 2019
    Assignee: Marvell International Ltd.
    Inventor: Ramen Dutta
  • Patent number: 10250189
    Abstract: A circuit having a first Gilbert cell mixer of a first type configured to receive phases of first and second signals and output a first current pair to a first node and a second node; a first Gilbert cell mixer of a second type configured to receive output a second current pair to the first node and the second node; a second Gilbert cell mixer of the first type configured to receive phases of the first and second signals and output a third current pair to the first node and the second node; a second Gilbert cell mixer of the second type configured to output a fourth current pair to the first node and the second node; a cross-coupling inverter pair configured to cross couple the first node and the second node; and a load placed across the first node and the second node and configured to resonate at a frequency approximately equal to either a sum of a frequency of the first signal and a frequency of the second signal or a difference of the frequency of the first signal and the frequency of the second signal.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: April 2, 2019
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10205458
    Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: February 12, 2019
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Brian S. Leibowitz, Masum Hossain
  • Patent number: 10148257
    Abstract: A clock generator and method operate by receiving an input clock; cascading a first inverter, a second inverter, a third inverter, and a fourth inverter in a ring topology to output a first phase, a second phase, a third phase, and a fourth phase of an interim clock; enabling the second inverter and the fourth inverter during a first phase of the input clock and enforcing a complementary relation between the second phase and the fourth phase of the interim clock by using a fifth inverter and a sixth inverter configured in a cross-coupling topology; enabling the first inverter and the third inverter during a second phase of the input clock and enforcing a complementary relation between the first phase and the third phase of the interim clock by using a seventh inverter and an eighth inverter configured in a cross-coupling topology.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: December 4, 2018
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10141921
    Abstract: A signal generator generates an output signal according to an oscillating signal. The signal generator has a plurality of edge sampling circuits and an edge combining circuit. Each of the edge sampling circuits receives the oscillating signal, samples the oscillating signal to obtain at least one of a rising edge and a falling edge in one cycle of the oscillating signal, and outputs a sampled signal using the at least one of the rising edge and the falling edge. The edge combining circuit combines a plurality of sampled signals generated by the edge sampling circuits, respectively, to generate the output signal.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: November 27, 2018
    Assignee: MEDIATEK INC.
    Inventors: Pang-Ning Chen, Yu-Li Hsueh
  • Patent number: 10135451
    Abstract: In some embodiments, a phase locked loop includes a voltage-controlled oscillator whose output is fed back to a first input of a phase comparator via a fractional divider controlled by a delta-sigma modulator. The method of doubling the frequency of the initial reference signal of the phase locked loop involves generating, from the initial reference signal and the output signal furnished by the voltage-controlled oscillator, a secondary reference signal having edges of a first type synchronized with each of the rising and falling edges of the initial reference signal and edges of a second type between the edges of the first type, and a furnishing of the secondary reference signal at a second input of the phase comparator operating on the edges of the first type.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: November 20, 2018
    Assignee: STMicroelectronics SA
    Inventors: Marc Houdebine, Sebastien Dedieu
  • Patent number: 10050611
    Abstract: An oscillation circuit includes: an oscillator configured to generate N phase clocks (where N is an integer of 2 or more) including a first phase clock to Nth phase clock whose phases are shifted by 360°/N at regular intervals; a pulse generating part configured to receive a plurality of the N phase clocks and generate a plurality of intermediate pulses each having a duty ratio of 25%; and a clock synthesizing part configured to synthesize the plurality of intermediate pulses to generate a single phase output clock or multi-phase output clocks, the single phase output clock and the multi-phase output clocks having a frequency that is twice an oscillation frequency of the oscillator.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: August 14, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Shinichi Saito
  • Patent number: 9996138
    Abstract: An electronic system includes a plurality of function modules, each of the plurality of function modules operates according to one of a plurality of clock signals; and a clock management module, for generating the plurality of clock signals according to a plurality of performances requirements of the plurality of function modules.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: June 12, 2018
    Assignee: MEDIATEK INC.
    Inventors: Ying-Ting Yang, Chiuan-Shian Chen
  • Patent number: 9985618
    Abstract: An apparatus includes a phase detector coupled to an output of a frequency multiplier. A digital loop filter is coupled to the phase detector, and a duty cycle correction circuit is coupled to the digital loop filter.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: May 29, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Dongmin Park, Jong Min Park, Lai Kan Leung
  • Patent number: 9858972
    Abstract: A semiconductor device may be provided. The semiconductor device may include an input information signal generation circuit and a command generation circuit. The input information signal generation circuit may be configured to latch a command in synchronization with a point of time that a division clock signal is inputted. The command generation circuit may be configured to shift a phase of the latched command in synchronization with a multiplication clock signal to shift the command.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: January 2, 2018
    Assignee: SK hynix Inc.
    Inventors: Kyung Whan Kim, Dong Uk Lee
  • Patent number: 9829912
    Abstract: The present invention solves a problem that the phases of clocks obtained by frequency-dividing PLL clocks output from local PLL circuits cannot be made the same in a plurality of data transfer blocks. A local PLL circuit outputs a PLL clock obtained by multiplying a common external clock. A frequency divider outputs a feedback clock obtained by frequency-dividing the PLL clock to the local PLL circuit. An FIFO buffer temporarily holds data input from the outside. The FIFO buffer outputs the held data on the basis of a frequency-divided PLL clock. A clock generator generates a frequency-divided PLL clock obtained by frequency-dividing the PLL clock. The clock generator controls the phase of the frequency-divided PLL clock on the basis of a common start signal.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: November 28, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasutake Manabe
  • Patent number: 9806701
    Abstract: A transformer-less DFM device comprising: an input receiving signals that are an integer multiple of an input signal; an edge detector that provides a quantized or a state output comparing an the input signal to a feedback signal; a statemachine that has counters and decimation circuits to provide a digitized output to a DAC that tunes delays between the input/output signals; a DLL for generating delay signals from the input signal that form an input to an edge combiner wherein the edge combiner takes different phases from the DLL to generate a multiplied output signal; a first DAC that takes the signal from the statemachine and provide a control to a supply circuit of the DLL to adjust a delay through a supply voltage; a second DAC that takes a signal from the statemachine and provides control to a backgate circuit of the DLL to adjust the delay.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: October 31, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Abdellatif Bellaouar, Arul Balasubramaniyan
  • Patent number: 9768728
    Abstract: A regenerative frequency divider comprising an in-phase mixer circuit and a phase-shifted mixer circuit. At least one switching device of the in-phase mixer circuit is of a smaller scale than a corresponding switching device of the transconductance component of the in-phase mixer circuit. In some examples, at least one switching device within an input switching stage of the regenerative frequency divider forming part of the phase-shifted mixer circuit is of a smaller scale than a respective corresponding switching device within the input switching stage forming part of the in-phase mixer circuit. In some further examples, all switching devices within the phase-shifted mixer circuit are of a small scale than respective corresponding switching devices within the in-phase mixer circuit.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: September 19, 2017
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Christophe C. Beghein, Jonathan Richard Strange
  • Patent number: 9735792
    Abstract: Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: August 15, 2017
    Assignee: RAMBUS INC.
    Inventors: Jared L. Zerbe, Masum Hossain
  • Patent number: 9697971
    Abstract: Disclosed herein are an apparatus for controlling a solenoid valve and a control method thereof. The apparatus for controlling the solenoid valve, which controls the solenoid valve including a solenoid coil, includes a switching part configured to switch a current supplied to the solenoid coil; a pre-driver configured to output a driving signal for driving the switching part; and a microcontroller unit (MCU) configured to control the pre-driver so that a frequency of the driving signal output from the pre-driver to the switching part is randomly varied.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: July 4, 2017
    Assignee: MANDO CORPORATION
    Inventor: Soo-Hyun Ko
  • Patent number: 9685941
    Abstract: The invention relates to a device for protecting at least one active component of an electronic module, able to receive a microwave electromagnetic signal as input and to provide a microwave electromagnetic signal to said at least one active component. This device includes a delay module able to apply a predetermined delay time to the microwave electromagnetic input signal, connected in parallel with a switch-triggering device able to compare a power level of the microwave electromagnetic input signal to a power threshold and to command switching by a switch connected at the output of the delay module, an output of said switch providing the microwave electromagnetic signal to said at least one active component, the predetermined delay time being such that the switching is done before the arrival of the microwave electromagnetic output signal from the delay module.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: June 20, 2017
    Assignee: THALES
    Inventors: Jean-Francois Fourmont, Joel Bernard Francois Herault, Emile Jean Pouderous
  • Patent number: 9673828
    Abstract: Wideband polar receivers and method of operation are described. A phase-modulated input signal is received at a polar receiver that includes an injection-locked oscillator. The injection-locked oscillator includes a plurality of injection points. Based on the frequency of the input signal, a particular Nth harmonic is selected, and the input signal is injected at the set of injection points corresponding to the selected Nth harmonic. The injection-locked oscillator generates an oscillator output signal, and the phase of the input signal is determined from the phase of the oscillator output signal. In some embodiments, the oscillator output signal is frequency-multiplied by N, mixed with the input signal, and filtered for use in amplitude detection. The input signal is decoded based on the phase and amplitude information.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: June 6, 2017
    Assignee: INNOPHASE, INC.
    Inventors: Yang Xu, Sara Munoz Hermoso, Roc Berenguer Perez
  • Patent number: 9660629
    Abstract: A duty cycle detector may include a rising clock detection unit enabled in response to a first control signal; a falling clock detection unit enabled in response to a second control signal with a different activation timing from the first control signal; and a comparison unit configured to compare an output signal of the rising clock detection unit to an output signal of the falling clock detection unit in response to a comparison enable signal, and output a duty cycle detection signal.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: May 23, 2017
    Assignee: SK hynix Inc.
    Inventors: Da In Im, Young Suk Seo
  • Patent number: 9571072
    Abstract: A frequency multiplication circuit includes a delay circuit that has a clock signal having a period input thereto and delays the signal by a time, an exclusive OR circuit that has the clock signal and a signal from the delay circuit input thereto and outputs a signal serving as an exclusive OR between the clock signal and the signal from the delay circuit, and a signal correction circuit that has a signal from the exclusive OR circuit input thereto and corrects the input signal to output the resultant. The length of the time is a length other than n×T/4 (n is an integer). The signal correction circuit attenuates a signal having a second frequency based on T/2, rather than a signal having a first frequency based on the time ?.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: February 14, 2017
    Assignee: Seiko Epson Corporation
    Inventors: Masataka Nomura, Akira Nakada
  • Patent number: 9515638
    Abstract: Methods for frequency multiplying include receiving a signal having an input frequency at a frequency multiplier comprising a pair of transistors; and selecting a harmonic in the signal by connecting the transistors to a common impedance through a respective collector impedance, wherein an output frequency at the harmonic between the collector impedances and the common impedance is an even integer multiple of an input frequency.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: December 6, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wooram Lee, Alberto Valdes Garcia
  • Patent number: 9509305
    Abstract: In an embodiment, an electronic device includes an integrated circuit (IC) having a plurality of power domains, a first regulator coupled to a given power domain, a second regulator coupled to the given power domain, and a switching circuit coupled between the first and second regulators and configured to control an amount of current drawn by the power domain from the first and/or second regulators. In another embodiment, a method includes controlling an impedance of a switching circuit to change an amount of current, the switching circuit coupled to a given power domain of an IC configured to operate in a first mode followed by a second mode, where the switching circuit is coupled to a first regulator configured to provide more power to the IC than a second regulator, and a transition period includes turning off the first regulator and turning on the second regulator.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: November 29, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Ivan Carlos Ribeiro Nascimento, Akshat Gupta, Sunny Gupta, Akshay K. Pathak, Adriano Marques Pereira, Garima Sharda, Pedro Barbosa Zanetta
  • Patent number: 9490784
    Abstract: A method, an apparatus, and a computer program product are provided. The apparatus outputs a sinusoidal signal according to a first clock frequency, generates, a first digital signal having a 25% duty cycle based on the sinusoidal signal, generates a second digital signal having a 25% duty cycle based on the sinusoidal signal, combines the first digital signal and the second digital signal to generate a combined digital signal having a 50% duty cycle and a second clock frequency that is double the first clock frequency, and doubles the second clock frequency of the combined digital signal to generate an output signal having a third clock frequency that is quadruple the first clock frequency. The apparatus further generates a first control voltage and a second control voltage for the first buffer and a third control voltage for the second buffer based on the output signal.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: November 8, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Mohammad Bagher Vahid Far, Alireza Khalili, Yashar Rajavi, Amirpouya Kavousian
  • Patent number: 9461622
    Abstract: Capacitance multiplier circuitry provides an increased equivalent capacitance, and may be implemented using a desirably small footprint. As may be implemented in accordance with one or more embodiments, a capacitor provides a first capacitance across first and second plates, and capacitance multiplier circuitry operates with the capacitor to provide a second equivalent capacitance that is a multiple of the first capacitance. The capacitance multiplier circuitry includes a first circuit path having a first resistor between the first plate and a common terminal, and a second circuit path having a switch and a second resistor between the second plate and the common terminal. An amplifier has differential inputs respectively corresponding to the first and second circuit paths and provides the second equivalent capacitance by controlling operation of the switch based upon the differential inputs and the respective resistances provided by the resistors in the first and second circuit paths.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: October 4, 2016
    Assignee: NXP B.V.
    Inventor: Ge Wang
  • Patent number: 9443810
    Abstract: A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: September 13, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: John Jong-Hoon Lee, Young Kyu Song, Uei-Ming Jow, Sangjo Choi, Xiaonan Zhang
  • Patent number: 9419595
    Abstract: Frequency multipliers include a pair of transistors each connected to a common impedance through a respective collector impedance formed from a transmission line. Each transmission line has a length between about one quarter and about one eighth of a wavelength of an input signal frequency and is tuned to produce a large impedance at a collector of the respective transistor at the input signal frequency. The output frequency between the collector impedances and the common impedance is an even integer multiple of the input frequency.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: August 16, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wooram Lee, Alberto Valdes Garcia
  • Patent number: 9405311
    Abstract: A circuit that regulates electrical current flow through an integrated circuit involves a sequencing circuit connected to a clock signal generator, the sequencing circuit configured to, responsive to receiving a clock signal from the clock signal generator, generate a set of sequencing signals that includes a first switching signal, a second switching signal, and a disable signal. The circuit also involves a switching circuit connected to the sequencing circuit, the switching circuit configured to receive the first switching signal and the second switching signal and a current mirror connected to the switching circuit and the sequencing circuit, the current mirror configured to receive an activation signal from a current control logic circuit and to receive the disable signal.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: August 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: David M. Onsongo, David P. Paulsen, Kirk D. Peterson, John E. Sheets, II
  • Patent number: 9397644
    Abstract: A frequency doubler includes a voltage controlled oscillator outputting N (where, N is a natural number) signals having a first period and having different phases, and an XOR circuit receiving the N signals and outputting a signal having a second period that corresponds to a half of the first period, wherein the voltage controlled oscillator includes N nodes that correspond to the N signals and inverter units respectively connecting the N nodes, the N nodes are arranged so that, if a signal that starts from any one start node of the N nodes passes through the same number of the inverter units, it recurs to the corresponding start node, the XOR gate includes a first unit block set including N unit blocks that are connected to the same output node and match the N nodes in a one-to-one manner, and a second unit block set that is substantially the same as the first unit block set, wherein the first and second unit block sets share the output node.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: July 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Seok Kim, Tae-Ik Kim, Ji-Hyun Kim
  • Patent number: 9344071
    Abstract: A circuit may include a pulse generation circuit configured to receive a first clock signal with a first-clock rate and a first-clock duty cycle. The pulse generation circuit may be configured to generate, based on the first clock signal, a pulse signal with a pulse frequency and with a pulse duty cycle that is smaller than the first-clock duty cycle. The circuit may also include a sub-harmonic injection locking oscillator configured to receive the pulse signal. The sub-harmonic injection locking oscillator may be configured to output, based on the pulse signal, a second clock signal with a second-clock rate that is greater than the first-clock rate and greater than the pulse frequency.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: May 17, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Shuo-Chun Kao, Nikola Nedovic
  • Patent number: 9257995
    Abstract: Apparatuses and methods for mitigating uneven circuit degradation of delay circuits are disclosed. In an example method, an imbalance in transistor threshold voltages is detected between a transistor of a first delay circuit and a transistor of a second delay circuit that is series coupled to the first delay circuit, and a clock level of an input clock signal to the first delay circuit is switched responsive to detecting the imbalance.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: February 9, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Scott D. Van De Graaff
  • Patent number: 9236834
    Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: January 12, 2016
    Assignee: RAMBUS INC.
    Inventors: Masum Hossain, Farshid Aryanfar, Mohammad Hekmat, Reza Navid
  • Patent number: 9203385
    Abstract: A method includes providing a first local oscillator signal having a first duty cycle to a first mixer unit and providing a second local oscillator signal having a second duty cycle to a second mixer unit. At least one of the first duty cycle or the second duty cycle is greater than fifty percent. A frequency of the first local oscillator signal approximately equals a frequency of the second local oscillator signal. The method may also include generating a modulated output signal based on an output signal of the first mixer unit and based on an output signal of the second mixer unit.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 1, 2015
    Assignee: Qualcomm Incorporated
    Inventors: Saihua Lin, Roger Brockenbrough
  • Patent number: 9190991
    Abstract: Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an input clock signal and for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal, the input clock signal having a non-50% duty cycle and a first period; and a second logic unit to compute a falling edge of the output clock signal according to the detected rising edge of the input clock signal, the falling edge of the output clock signal being near half of the first period.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: November 17, 2015
    Assignee: Intel Corporation
    Inventors: Mark Neidengard, Vaughn Grossnickle, Nasser Kurd, Jeffrey Krieger
  • Patent number: 9166585
    Abstract: A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: October 20, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Amit Roy, Zhihong Cheng, Amit Kumar Dey, Vijay Tayal, Chetan Verma
  • Patent number: 9041440
    Abstract: A frequency tripler device is disclosed. The frequency tripler device includes a first graphene based field effect transistor (FET) of a first dopant type, having a gate, a drain, and a source, and a second graphene based FET of a second dopant type, having a gate, a drain, and a source, the gate of the first FET coupled to the gate of the second FET and coupled to an input signal having an alternating current (AC) signal of a first frequency, the combination of the first and second FETs generates an output signal with a dominant AC signal of a frequency of about three times the first frequency.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: May 26, 2015
    Assignee: Purdue Research Foundation
    Inventors: Joerg Appenzeller, Hong-yan Chen
  • Patent number: 9018987
    Abstract: A phase locked loop includes a voltage controlled oscillator and a frequency divider or frequency multiplier. The voltage controlled oscillator and the frequency divider/multiplier are coupled together in a stacked configuration. A drive current is supplied to the voltage controlled oscillator. The drive current passes from the voltage controlled oscillator to the frequency divider/multiplier, thereby driving the frequency divider/multiplier with the same drive current that was supplied to the voltage controlled oscillator.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics International N.V.
    Inventor: Abhirup Lahiri
  • Patent number: 8981822
    Abstract: Described is an apparatus comprising a plurality of logic units arranged in a ring, wherein an output terminal of each logic unit from the plurality of logic units is coupled to an input terminal of a next logic unit from the plurality of logic units, wherein the plurality of logic units includes a first multiple input logic unit having input nodes coupled to at least two output terminals of logic units from the plurality of logic units; and a plurality of latch units coupled to the output terminals of the plurality of logic units.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 17, 2015
    Assignee: Intel Corporation
    Inventor: Shenggao Li
  • Patent number: 8977519
    Abstract: A spectrum analyzer for measuring an RF signal over a selected frequency span configured to use multiple Intermediate Frequencies (IFs) for residual, spurious and image signal reduction. The spectrum analyzer has both a primary IF path and a secondary IF path configured to provide band pass filtering of the IF signals. A master clock synthesizer is configured to reduce residual noise by providing from a single Voltage Controlled Oscillator, a master clock signal and a Local Oscillator (LO) signal. The spectrum analyzer has a microcontroller configured to change the frequency of the master clock signal and the LO signal if the center frequency of the selected span is sufficiently close to a known spurious signal.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: March 10, 2015
    Assignee: Test Equipment Plus, Inc
    Inventor: Justin Crooks
  • Patent number: 8963602
    Abstract: A pulse generator is disclosed. The pulse generator can include an ac source for providing an ac signal. A pulsed switch can be connected to an ac output of the ac source that is adapted or configured to generate a pulsed output from the ac signal and a non-linear frequency multiplier adapted or configured to shorten the pulses of the pulsed output. The pulsed switch can include a mixer.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: February 24, 2015
    Assignee: The University Court of the University of St. Andrews
    Inventors: David Robert Bolton, Graham Smith
  • Patent number: 8941420
    Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: January 27, 2015
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Brian S. Leibowitz, Masum Hossain
  • Patent number: 8933731
    Abstract: An adder circuit includes first through fourth two-bit adder modules, and first through third result mux blocks for receiving and adding first and second binary values to generate a final sum. A multiplier circuit that multiplies a multiplier and a multiplicand includes a multiplexer, an encoder connected to the multiplexer, a shifter connected to the encoder, and an accumulator connected to the encoder for receiving the multiplier and multiplicand and generating a multiplication product.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: January 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rohit Goyal, Amit Kumar Dey, Naman Gupta
  • Patent number: 8933732
    Abstract: Methods for increasing a signal frequency include generating two or more signals having a fundamental mode and one or more harmonics; phase shifting bifurcated components of the two or more signals in transmission lines; and combining the bifurcated components to create an output signal that cancels a fundamental mode, a second harmonic, and a third harmonic in the signals to produce a frequency-multiplied output signal.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Wooram Lee, Alberto Valdes Garcia
  • Patent number: 8922260
    Abstract: A dual-edge triggered variable frequency divider for use in digital frequency synthesis is disclosed. The variable frequency divider utilizes a multiphase clock and a logic unit, including both positive and negative edge triggered unit delay elements connected in parallel. The variable frequency divider generates a clock pulse from a signal source that corresponds to an input value from a logic unit, generates a next input value by the logic unit based on the input value and a frequency control word, and transmits the next input value from the logic unit to the signal source in response to the clock pulse. The multiphase clock is configured to generate the clock signal in response to the falling edge of the first pulse of the clock signal.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: December 30, 2014
    Assignee: MStar Semiconductor, Inc.
    Inventors: Khurram Muhammad, Chih-Ming Hung
  • Publication number: 20140380082
    Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
    Type: Application
    Filed: September 10, 2014
    Publication date: December 25, 2014
    Inventors: Masum Hossain, Farshid Aryanfar, Mohammad Hekmat, Reza Navid
  • Patent number: 8890585
    Abstract: A frequency multiplier and associated method are provided, wherein the frequency multiplier includes a waveform generator and a slicer. The waveform generator generates a waveform in response to an input signal, and the slicer induces transitions in an output signal whenever the waveform crosses each of a plurality of reference levels, such that a frequency of the output signal is a multiple of a frequency of the input signal.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: November 18, 2014
    Assignee: MStar Semiconductor, Inc.
    Inventors: Jian-Yu Ding, Shih-Chieh Yen, Ming-Yu Hsieh, Yao-Chi Wang
  • Patent number: 8884663
    Abstract: Methods, apparatus, and fabrication techniques relating to management of noise arising from capacitance in a clock tree of an integrated circuit. In some embodiments, the methods comprise receiving a signal to adjust a clock having a first rate to a second rate; and ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: November 11, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Steven J. Kommrusch, Zihno Jusufovic
  • Patent number: 8884664
    Abstract: An embodiment of a system for generating a low phase noise sine wave includes a variable signal source for generating a signal a series of octave dividing stages connected with the variable signal source, an input divider connected with the variable signal source, and a second series of octave dividing stages connected with an output of the pre-input frequency divider. Each octave dividing stage generating a successive octave of the generated signal using a frequency divider, a sine look up table, and a low pass filter.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 11, 2014
    Assignee: Anritsu Company
    Inventor: Donald Anthony Bradley