Abstract: A clock circuit includes a first latch, second latch, first trigger circuit and clock trigger circuit. The first latch generates a first latch output signal based on a first control signal, an enable signal and an output clock signal. The second latch is coupled to the first latch, and configured to generate the output clock signal responsive to a second control signal. The first trigger circuit is coupled to the first latch and the second latch, and configured to adjust the output clock signal responsive to at least the first latch output signal or a reset signal. The clock trigger circuit is coupled to the first latch and the first trigger circuit by a first node, is configured to generate the first control signal responsive to an input clock signal, and configured to control the first latch and the first trigger circuit based on at least the first control signal.

Abstract: In some aspects, the disclosure is directed to methods and systems for controlling periodic jitter arising from a phase interpolator (PI). A receiver can receive incoming data. A fractional-N phase-locked loop (PLL) can receive a reference clock. Measurement circuitry can measure a parts per million (PPM) offset between the incoming data and the reference clock, of a PI. The fractional-N PLL can restrict jitter arising from the PI, to frequencies within a predefined bandwidth, by tuning a center frequency of the fractional-N PLL to reduce the PPM offset of the PI.

Abstract: An integrated circuit device includes a plurality of flip flops configured into a scan chain. The plurality of flip flops includes at least flip flop of a first type and at least one flip flop of a second type. A method includes generating a first scan clock signal for loading scan data into at least one flip flop of a first type, generating a second scan clock signal and a third scan clock signal for loading the scan data into at least one flip flop of a second type, and loading a test pattern into a scan chain defined by the at least flip flop of the first type and the at least one flip flop of the second type responsive to the first, second, and third scan clock signals.

Abstract: An electronic latch circuit (100) and a multi-phase signal generator (300) are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first output (X, 106), a second output (Y, 107) and a third output (Z, 108). The electronic latch circuit (100) further comprises an input circuit (101) comprising a first input (A, 102), a second input (B, 103) and a clock signal input (CLK, 104). The electronic latch circuit (100) is configured to change state based on input signals at the inputs (A, B, CLK) of the input circuit (101) and a present state of the output circuit (105). The multi-phase signal generator (300) comprises a plurality N of the electronic latch circuit (100) for generating N phase signals with individual phases. The plurality N of the electronic latch circuit (100) are cascaded with each other.

Abstract: An apparatus includes a fractional divider and a modulator circuit. The fractional divider circuit may be configured to generate a feedback clock signal in response to a selection signal, a divided clock signal and an output clock signal. The modulator circuit may be configured to generate the selection signal in response to the feedback clock signal. The fractional divider may generate four phase clock signals from the divided clock signal. The four phase clock signals may be interleaved by the fractional divider circuit to select one of the four phase clock signals as the feedback clock signal. The fractional divider operates at a divide-by-4 clock speed. The selection signal may be synchronized in response to the divided clock signal to generate the feedback clock signal. The fractional divider circuit may be implemented using CMOS logic.

Abstract: A semiconductor device has a clock signal generation circuit that generates a clock signal, and a processing circuit that operates in accordance with the clock signal. The semiconductor device can also include an external terminal and a power source terminal that is coupled to the processing circuit. The clock signal generation circuit changes the frequency of the clock signal to be generated in accordance with the voltage value of a current consumption signal supplied to the external terminal. Further, the voltage value of the current consumption signal is changed in accordance with current consumption flowing in the power source terminal. The clock signal generation circuit can change the frequency of the clock signal to be generated in accordance with a value of an analog signal supplied to the external terminal.

Abstract: The present invention relates to an electronic latch circuit, a method, and a 4-phase generator. The electronic latch circuit comprises an output circuit comprising an output X, and an output Y. The electronic latch circuit further comprises an input circuit, comprising an input A, an input B, and a clock signal input. The input circuit is connected to the output circuit, and configured to select a state of the output circuit from the group of a first state, a second state, and a third state. The input circuit is further configured to select the first state upon detecting a high state on the input B, a transition on the clock signal input from a low state to a high state, and a low state on the input A, and that the electronic latch circuit is in the second state.

Abstract: Described is an apparatus for clock synchronization. The apparatus comprises a pair of interconnects; a first die including a first phase interpolator having an output coupled to one of the interconnects; and a second die, wherein the pair of interconnects is to couple the first die to the second die.

Abstract: A frequency divider may be provided. The frequency divider may be configured to generate a division signal having a variable cycle according to transition timing information and a division ratio signal.

Abstract: According to one embodiment, a frequency divider circuit includes a 1st flip-flop including a 1st terminal to which a clock signal is input, and including a 2nd terminal to which a 1st signal is input; a 2nd flip-flop including a 1st terminal to which the clock signal is input, and including a 2nd terminal to which a 2nd signal is input, the 2nd signal being output from the 1st flip-flop; a 3rd flip-flop including a 1st terminal to which the clock signal is input, and including a 2nd terminal to which a 3rd signal is input, the 3rd signal being output from the 2nd flip-flop; and an exclusive OR gate including a 1st terminal to which the 4th signal is input, and including a 2nd terminal to which a 5th signal is input, the 5th signal being output from the 2nd flip-flop.

Abstract: Disclosed are a chip performance monitoring system, method and a computer program product, wherein a performance monitor output signal is propagated through an adjacent scan chain to avoid signal degradation incident to across-chip transmission of high frequency signals. Since the clock signal frequency used to control signal propagation through the scan chain will typically be less than twice the performance monitor output signal frequency, frequency sub-sampling with aliasing occurs. To compensate, signal propagation through the scan chain can be controlled during different time periods using different clock signals having different clock signal frequencies and, during these different time periods, different data outputs can be captured at an output node of the scan chain. The data output frequencies of these different data outputs can be measured and the performance monitor output signal frequency can be determined based on the different data output frequencies given the different clock signal frequencies.

Abstract: An example embodiment disclosed herein enables at least one frequency divider chain of a multiphase divider circuit to ensure proper phase relations after multiple frequency divisions. Another example embodiment enables a unique reset sequence to maximize a timing margin for reset signals of the at least one frequency divider chain and, thus, maximizes a bandwidth of the multiphase divider circuit.

Abstract: A master voltage controlled oscillator (VCO) produces an output signal at an operating frequency of at least 100 gigaHertz (GHz). A buffer VCO injection-locked to an output of the master VCO produces an output signal at the operating frequency with a voltage swing greater than 50% of an output voltage swing of the master VCO output signal. The buffer VCO operates without pulling, and can drive a load of at least three times greater than a nominal load. Phase noise in the output of the buffer VCO is as much as ?96 decibels (dB) relative to the carrier (dBc) per Hertz (Hz) at 125 GHz with a 1 megaHertz (MHz) offset.

Abstract: A multi-modulus frequency divider includes a frequency division module, a frequency selection module, and a retiming module. The frequency division module is configured to receive an input signal and perform mufti-mode frequency processing on the input signal, so as to generate and output a plurality of divided signals to the frequency selection module. The frequency selection module is configured to receive the plurality of divided signals from the frequency division module, select a divided signal having a desired frequency from among the plurality of divided signals, and output the selected divided signal to the retiming module. The retiming module is configured to receive the selected divided signal from the frequency selection module, perform a retiming operation on the selected divided signal, and output a retimed selected divided signal.

Abstract: A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up.

Abstract: A latch and a frequency divider are provided. The latch includes: a first logic unit coupled between a power supply and a ground wire, wherein the first logic unit includes a first input terminal and a first output terminal; a second logic unit having a structure symmetrical to that of the first logic unit, wherein the second logic unit includes a second input terminal and a second output terminal; and a first feedforward control unit adapted for cutting off a first current path, wherein the first feedforward control unit includes a first clock signal input terminal adapted for receiving a first clock signal, a third output terminal coupled to the first output terminal, and at least two feedforward control terminals, at least one of which is coupled to the first input terminal or the second input terminal. Power consumption of the latch and the frequency divider can be reduced.

Abstract: A power supply circuit is intended to suppress power consumption when a load is not driven and to shorten a required time to be taken until a boosted voltage to be supplied to a high-side MOS transistor is stabilized when the load is changed from a deactivated state to an activated state. The power supply circuit (power supply circuit 3) supplying power to a load driving circuit (motor driving circuit 2) that drives a load by controlling a high-side MOS transistor M1 on the basis of an input load control signal includes a booster circuit (charge pump 23) configured to boost a voltage of input power and supplies the power of which the voltage is boosted as power for driving the high-side MOS transistor. The booster circuit has power supply capability which varies depending on the load control signal.

Abstract: A frequency divider circuit can achieve multi-modulus operation. The frequency divider includes clocking transistor devices, memory transistor circuits, write transistor devices, and a current source bias. The clocking transistor devices receive a differential input signal having a first frequency at an input of the frequency divider. The memory transistor circuits store signals based on the differential input signal from the clocking transistor devices. The write transistor devices make a divided frequency signal available at an output terminal. The current source bias is coupled to the clocking transistor devices. The current source bias applies a bias current to adapt the frequency divider to a common-mode at the input of the frequency divider.

Abstract: A programming method includes an upper computer, a calculation module, and a first signal conversion module. The calculation module includes a second signal conversion module and a programming interface. The upper computer is configured to convert programming data into first bus signals. When the calculation module is in a normal programming state, the second signal conversion module converts the first bus signals into first clock signals and first data signals to program the calculation module. When the calculation module is in a non-normal programming state, the first signal conversion module converts the first bus signals into second clock signals and second data signals to program the calculation module. A programming method is also provided.

Abstract: An improved counter may implement dynamic frequency measurement while also remaining fully backwards compatible with traditional frequency measurement methods. The counter may operate according to low-frequency, large range, and/or high frequency modes of operation. It may be programmable with a divisor value associated with the large range operating mode, and a measurement time associated with the high frequency mode of operation. The divisor and measurement time settings may be enabled or disabled, and when either setting is disabled, the counter becomes backwards compatible with traditional frequency measurement methods. The counter may also be provided with inputs representative of the desired type of measurement and the minimum and maximum expected values for the signal to be measured. The counter may perform the frequency measurement according to any one or more of the operating modes, and return a measurement result obtained in the operating mode that completes the measurement first.

Abstract: An LED based illumination device is dimmed by controlling an average current supplied to the LED based illumination device. The currently supplied to the LED may be supplied by an LED driver that is in communication with a dimming control engine. The dimming control engine may receive an indication of a desired average current level. The dimming control engine controls the LED driver to periodically switch a current supplied to an LED of the LED based illumination device from a high state to a low state over a switching period, wherein both a duration of the switching period is adjusted and a ratio of a time in the high state to a time in the low state is adjusted as the average current supplied to the LED based illumination device transitions from a first average current level to the desired average current level.

Abstract: Various aspects of an injection-locked oscillator and method for controlling jitter and/or phase noise are disclosed herein. In accordance with an embodiment, an injection-locked oscillator includes one or more circuits that are configured to receive a pair of complementary phase output signals from one or more gain stages of the injection-locked oscillator. The one or more circuits may be configured to receive one or more switching signals. The received pair of complementary phase output signals are shorted by use of the one or more received switching signals. The shorting reduces the phase difference between an input signal and an output signal of the injection-locked oscillator.

Abstract: Extending a microphone interface. One microphone interface extension includes a controller, a parent microphone, and a child microphone. The controller outputs a controller clock signal. The parent microphone receives the controller clock signal and generates a first data signal. The child microphone generates a second data signal and outputs the second data signal to the first parent microphone. The parent microphone receives the second data signal from the child microphone and outputs a combined data signal to the controller based on the first data signal and the second data signal. The parent microphone outputs the combined data signal to the controller on a phase of a microphone clock signal derived from the controller clock signal.

Abstract: A programming system includes an upper computer, a calculation module, and a first signal conversion module. The calculation module includes a second signal conversion module and a programming interface. The upper computer is configured to convert programming data into first bus signals. When the calculation module is in a normal programming state, the second signal conversion module converts the first bus signals into first clock signals and first data signals to program the calculation module. When the calculation module is in a non-normal programming state, the first signal conversion module converts the first bus signals into second clock signals and second data signals to program the calculation module. A programming method is also provided.

Abstract: A voltage-controlled oscillator (VCO), includes a resonator circuit connected to receive an input voltage and having a first output node and a second output node; and at least one cross-coupled switching circuit portion, each cross-coupled switching circuit portion comprising a first transistor having a drain connected to the first output node and a second transistor having a drain connected to the second output node, the first transistor having a gate connected between the drain of the second transistor and the second output node and the second transistor having a gate connected between the drain of the first transistor and the first output node, each of the first and second transistors having a threshold voltage that is determined to be the highest threshold voltage available for the process used to create the VCO.

Abstract: Described is an apparatus for boosting a transition edge of a signal, the apparatus comprises: a logic to provide input data having a Unit Interval (UI); a programmable delay unit to receive the input data and operable to delay the input data by a fraction of the UI to generate a delayed input data; and one or more drivers to drive the input data and the delayed input data to a node.

Abstract: According to an embodiment, an electronic transmission element is provided that has a first input and a first output. The first input is coupled to the first output by means of two first, parallel-connected complementary switches. The first switches each have a control input. The electronic transmission element further has a second input and a second output. The second input is coupled to the second output by means of two second, parallel-connected complementary switches. The second switches each have a control input. The first output is coupled to the control inputs of the second switches and the second output is coupled to the control inputs of the first switches.

Abstract: A synthesizer module arranged to generate a timing signal. The synthesizer module comprises an odd-numbered frequency divider circuit arranged to receive a reference timing signal and to output at least one frequency-divided signal having a frequency equal to 1/M times the frequency of the reference timing signal, where M is an odd-numbered integer. A 90° phase-shift component is arranged to receive the reference timing signal and to output a 90° phase-shifted form of the reference timing signal. A re-timing circuit is arranged to re-time a set of transitions of the frequency-divided signal to be temporally aligned to transitions of the 90° phase-shifted form of the reference timing signal to generate the timing signal comprising the re-timed transitions of the frequency-divided signal.

Abstract: A system and a method generate clock signals using an output divider with modulus steps of half-integers (i.e., the output circuit includes a divider which divides by one or more of 2, 2.5, 3, 3.5, 4 . . . ).

Abstract: Methods and apparatus relating to a low ripple mechanism of mode change in switched capacitor voltage regulators are described. In an embodiment, a mode change of a Switching Capacitor Voltage Regulator (SCVR) is caused based at least in part on a comparison of an output voltage of the SCVR and a reference voltage. The output voltage is sensed based at least in part on a clock signal. Other embodiments are also disclosed and claimed.

Abstract: Disclosed examples include frequency divider circuits, comprising an even number 4 or more differential delay circuits coupled in a cascade ring configuration of a configurable length N, with N?K of the N delay circuits providing an inverted polarity output signal to a succeeding delay circuit in the cascade ring configuration to control an amount of overlap between phase shifted clock signals from the delay circuits.

Abstract: Embodiments of the present invention disclose a frequency divider and a radio communications device. The frequency divider includes a shift register unit and an output frequency synthesizing unit; the shift register unit includes multiple cyclically cascaded basic units; a basic unit at each level includes 2N D flip-flops connected in series and a multiplexer, outputs of the 2N D flip-flops connected in series are separately connected to the multiplexer; an output of the multiplexer is connected to an input of a next-level basic unit; the output frequency synthesizing unit superposes an output signal of the first D flip-flop of the basic unit at each level to generate a frequency division output signal.

Abstract: A divider circuit determines whether an input factor (N) is an even number or an odd number. If N is an even number then the input clock is divided by N/2 to generate an intermediate clock. The intermediate clock is further divided by two to generate a div-by-2 clock, which is provided as the output clock with fifty percent duty cycle. If N is an odd number, the input clock is divided by (N/2?0.5) in a first duration and by (N/2+0.5) in a second duration to generate the intermediate clock, which is then divided by two to generate the div-by-2 clock. A delayed clock is generated from the div-by-2 clock, wherein the delayed clock lags the div-by-2 clock by half cycle duration of the input clock. The div-by-2 clock and the delayed clock are combined to generate the output clock with fifty percent duty cycle.

Abstract: An integrated circuit (IC) that is operable in scan test and functional modes includes scan-in pads, scan-out pads, scan chains, a compressor, a decompressor, a test control register, and a scan controller. The scan controller includes a multiple input shift register (MISR), an inverter, and multiple logic gates. The scan-in and scan-out pads receive scan test data and masking signals, respectively. The decompressor provides decompressed scan test data to the scan chains, which generate functional responses based on the decompressed scan test data. The compressor provides compressed functional responses to the scan controller. The logic gates receive the compressed functional responses and the masking signals from the compressor and the corresponding scan-out pads, respectively, and generate corresponding masked signals. The masking signals mask non-deterministic values in the decompressed functional responses. The MISR receives the masked signals and generates an error free signature.

Abstract: In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.

Abstract: A modulated clock device is provided that includes an update device for updating a phase of the modulated clock device. In one example, the update device includes an update phase multiplexer coupled to an output phase multiplexer of an output clock generator and configured to receive an input clock signal and one or more phases of the input clock signal; an output phase fractional counter coupled to the update phase multiplexer and configured to receive an update clock signal and to generate an output phase; and an update phase device coupled to the output phase fractional counter and to the update phase multiplexer. The output phase fractional counter is further configured to send the output phase to the output phase multiplexer and to the update phase device. The update phase device is configured to generate an update phase and to send the update phase to the update phase multiplexer.

Abstract: A clock generation device generates a clock signal which has a predetermined number of clocks for each predetermined time in such a way that a clock signal (32.768 kHz+? (? is zero or a positive number)) is input and some clocks of the clock signal are masked.

Abstract: According to one embodiment, a random number generating circuit includes first to N-th oscillating circuits (N is a natural number equal to 2 or greater), first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency, first to N-th exclusive OR circuits, (N+1)-th to (2×N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock, an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2×N)-th latch circuits, and an M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency.

Abstract: A semiconductor device containing a terminal, a power supply voltage dropping circuit that generates a constant voltage, a switch circuit to periodically apply a constant voltage to a terminal in response to a first clock, a current-controlled oscillator circuit, and a counter, and in which the power supply voltage dropping circuit supplies a first current to the switch circuit, the current-controlled oscillator circuit generates a second clock whose frequency changes in response to the value of the first current, and the counter counts the number of second clocks within the counting time.

Abstract: A signal generating system for generating an output signal with a 50% duty cycle, comprising: a frequency dividing module, comprising an odd number of level triggering devices, for generating a plurality of frequency divided signals utilizing a frequency dividing ratio equaling to M, wherein the M is an positive integer; and a signal combining module, for combining at least two of the frequency divided signals to generate at least one output combined signal. The signal generating system generates the output signal based on the output combined signal. The frequency dividing module cooperates the signal combining module to provide a frequency dividing ratio equaling to N.5, wherein the N is a positive integer.

Abstract: A method for reducing a frequency error, including: applying a plurality of dither values to a local reference clock over a first time interval; sampling, during the first time interval and using the local reference clock, a first plurality of data values received over an asynchronous link, where the first plurality of data values are transmitted over the asynchronous link based on a remote reference clock; tracking a plurality of errors from sampling the first plurality of data values; and adjusting, based on the plurality of errors, a frequency of the local reference clock to reduce the frequency error between the local reference clock and the remote reference clock.

Abstract: A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.

Abstract: Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.

Abstract: A dynamic rotary traveling wave oscillator circuit includes plurality of multi-output spot-advancing blocks (MOSABs) forming a main-loop and a plurality of multi-input spot-advancing blocks (MISABs) forming a sub-loop. Depending on a desired division ratio, a connection connects blocks on the MOSABs and MISABs to create the desired division ratio.

Abstract: A latch and a frequency divider are provided. The latch includes: a first logic unit coupled between a power supply and a ground wire, wherein the first logic unit comprises a first control terminal, a first input terminal and a first output terminal; a second logic unit having a structure symmetrical to that of the first logic unit, wherein the second logic unit comprises a second control terminal, a second input terminal and a second output terminal; and a feedforward control unit adapted for cutting off a current path in the first logic unit or the second logic unit based on signals inputted into the first input terminal and the second input terminal. Power consumption of the latch can be reduced in both static working condition and dynamic working condition.

Abstract: A fully differential level conversion circuit includes a positive signal branch, a negative signal branch and a coupling branch. The negative signal branch has identical structural features with the positive signal branch, which includes a drive terminal and a load terminal, an external fully differential signal is inputted to the drive terminals of the positive signal branch and the negative signal branch correspondingly. The coupling branch includes a first group of active couplers which forms a dual structure with the drive terminal of the positive signal branch and a second group of active couplers which form another dual structure with the drive terminal of the negative signal branch, both of which are connected between the drive terminals and load terminals. The fully differential level conversion circuit realizes applications in the signal processing process which has low power consumption and high-speed, and improves duty cycle of the output signal.

Abstract: A circuit operating with a switching clock signal and a sampling clock signal can have one or more of its switching and sampling clock signals periodically phase-reversed. The period of phase reversal can be greater than twice the period of the original switching and/or sampling clock signal, and in certain configurations the switching and sampling clock signals can be synchronized. With a selection of phase reversal period (or frequency), aliasing frequency components of the mixed signal from the switching and sampling clock signals can be removed.

Abstract: A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.

Abstract: A circuit includes a ring oscillator that includes a plurality of delay stages coupled in series to generate an output frequency for the ring oscillator. A capacitive array is operatively coupled between a supply rail and a power rail for each of the delay stages to supply power to the delay stages. The capacitive array selectively adjusts the output frequency of the ring oscillator via a capacitive setting of the capacitive array.

Abstract: A semiconductor integrated circuit includes a first generation unit configured to generate a fixed frequency division clock signal (first signal) from an output clock signal of a clock source, a fixed frequency division state monitoring unit configured to monitor the first signal, a second generation unit configured to generate a variable frequency division clock signal (second signal) from the output signal, and a variable frequency division state monitoring unit configured to monitor the second signal. In a case where the frequency of the second signal is returned from a reduced frequency to normal, when the variable frequency division state monitoring unit determines that the second signal becomes high in a next cycle, output of the second signal is stopped, and when the fixed frequency division state monitoring unit determines, after the output is stopped, that the first signal becomes high in a next cycle, the output is resumed.