Abstract: A phase locked loop includes a voltage controlled oscillator and a frequency divider or frequency multiplier. The voltage controlled oscillator and the frequency divider/multiplier are coupled together in a stacked configuration. A drive current is supplied to the voltage controlled oscillator. The drive current passes from the voltage controlled oscillator to the frequency divider/multiplier, thereby driving the frequency divider/multiplier with the same drive current that was supplied to the voltage controlled oscillator.

Abstract: Described is an apparatus comprising a plurality of logic units arranged in a ring, wherein an output terminal of each logic unit from the plurality of logic units is coupled to an input terminal of a next logic unit from the plurality of logic units, wherein the plurality of logic units includes a first multiple input logic unit having input nodes coupled to at least two output terminals of logic units from the plurality of logic units; and a plurality of latch units coupled to the output terminals of the plurality of logic units.

Abstract: A spectrum analyzer for measuring an RF signal over a selected frequency span configured to use multiple Intermediate Frequencies (IFs) for residual, spurious and image signal reduction. The spectrum analyzer has both a primary IF path and a secondary IF path configured to provide band pass filtering of the IF signals. A master clock synthesizer is configured to reduce residual noise by providing from a single Voltage Controlled Oscillator, a master clock signal and a Local Oscillator (LO) signal. The spectrum analyzer has a microcontroller configured to change the frequency of the master clock signal and the LO signal if the center frequency of the selected span is sufficiently close to a known spurious signal.

Abstract: A pulse generator is disclosed. The pulse generator can include an ac source for providing an ac signal. A pulsed switch can be connected to an ac output of the ac source that is adapted or configured to generate a pulsed output from the ac signal and a non-linear frequency multiplier adapted or configured to shorten the pulses of the pulsed output. The pulsed switch can include a mixer.

Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

Abstract: Methods for increasing a signal frequency include generating two or more signals having a fundamental mode and one or more harmonics; phase shifting bifurcated components of the two or more signals in transmission lines; and combining the bifurcated components to create an output signal that cancels a fundamental mode, a second harmonic, and a third harmonic in the signals to produce a frequency-multiplied output signal.

Abstract: An adder circuit includes first through fourth two-bit adder modules, and first through third result mux blocks for receiving and adding first and second binary values to generate a final sum. A multiplier circuit that multiplies a multiplier and a multiplicand includes a multiplexer, an encoder connected to the multiplexer, a shifter connected to the encoder, and an accumulator connected to the encoder for receiving the multiplier and multiplicand and generating a multiplication product.

Abstract: A dual-edge triggered variable frequency divider for use in digital frequency synthesis is disclosed. The variable frequency divider utilizes a multiphase clock and a logic unit, including both positive and negative edge triggered unit delay elements connected in parallel. The variable frequency divider generates a clock pulse from a signal source that corresponds to an input value from a logic unit, generates a next input value by the logic unit based on the input value and a frequency control word, and transmits the next input value from the logic unit to the signal source in response to the clock pulse. The multiphase clock is configured to generate the clock signal in response to the falling edge of the first pulse of the clock signal.

Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Abstract: A frequency multiplier and associated method are provided, wherein the frequency multiplier includes a waveform generator and a slicer. The waveform generator generates a waveform in response to an input signal, and the slicer induces transitions in an output signal whenever the waveform crosses each of a plurality of reference levels, such that a frequency of the output signal is a multiple of a frequency of the input signal.

Abstract: An embodiment of a system for generating a low phase noise sine wave includes a variable signal source for generating a signal a series of octave dividing stages connected with the variable signal source, an input divider connected with the variable signal source, and a second series of octave dividing stages connected with an output of the pre-input frequency divider. Each octave dividing stage generating a successive octave of the generated signal using a frequency divider, a sine look up table, and a low pass filter.

Abstract: Methods, apparatus, and fabrication techniques relating to management of noise arising from capacitance in a clock tree of an integrated circuit. In some embodiments, the methods comprise receiving a signal to adjust a clock having a first rate to a second rate; and ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates.

Abstract: A noise reduction filter is inserted between the source and non-linear transmission line (NLTL) in a frequency multiplier to improve phase noise performance. The noise reduction filter is suitably coupled directly to the input of the NLTL. The noise reduction filter and the output BPF are suitably low complexity filters.

Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Abstract: Described herein is a wireless transceiver and related method that enables ultra low power transmission and reception of wireless communications. In an example embodiment of the wireless transceiver, the wireless transceiver receives a first-reference signal having a first-reference frequency. The wireless transceiver then uses the first-reference signal to injection lock a local oscillator, which provides a set of oscillation signals each having an oscillation frequency that is equal to the first-reference frequency, and each having equally spaced phases. Then the wireless transceiver combines the set of oscillation signals into an output signal having an output frequency that is one of (i) a multiple of the first-reference frequency (in accordance with a transmitter implementation) or (ii) a difference of (a) a second-reference frequency of a second-reference signal and (b) a multiple of the first-reference frequency (in accordance with a receiver implementation).

Abstract: A frequency multiplier system, for outputting a single phase clock of N multiplied frequency after processing an inputted clock, N?2, includes a frequency divider receiving the inputted clock, an interpolator connected with the frequency divider, a phase equalizer connected with the interpolator, and a combinational logic circuit connected with the phase equalizer, wherein the frequency divider outputs an orthogonal clock having a two-phases frequency that is a half of the inputted clock to the interpolator, the interpolator outputs a 2N-phases clock to the phase equalizer, the phase equalizer homogenizes a phase skew of the 2N-phases clock, the combinational logic circuit synthesizes the homogenized 2N-phases clock into a single phase clock of N multiplied frequency. And a method of multiplying frequency is provided. The present invention does not need feedback circuits, and therefore is stable and fast-speed, saves area, and reduces energy consumption.

Abstract: Phase-coherent differential structures contain a phase-coherent transformer having two pairs of phase-coherent coupled differential inductors.

Abstract: A frequency tunable signal source (100) with first (105) and a second (115, 315) oscillators, each of which outputs a signal at a fundamental frequency (f1, f2) and at least one signal at a harmonic frequency (f1?, f2?) and a mixer (120) with first (121) and second (122) input ports and an output port (124), and a control unit (110) which controls switches (S1, S2, S3, S4), by means of which two of said signals (f1, f2, f1?, f2?) are switchably connected to the first input port. The other two signals are switchably to the other input port, with one switch (S1, S2, S3, S4) for each signal (f1, f2, f1?, f2?). There is also comprised a third oscillator (125), with an output signal connected to a third input port (123) of the mixer (120). At least one of the oscillators (105, 115, 315, 125) is a VCO, a Voltage Controlled Oscillator.

Abstract: A frequency multiplier for generating an output signal having a frequency N times the input signal, with N equal to or greater than 3, the frequency multiplier including a phase splitter circuit responsive to the input signal for generating N signals with phase differences, and a mixer circuit responsive to the N signals of the phasor circuit for providing an output signal having a frequency N times the input signal.

Abstract: A multiplier-divider circuit for signal process according to the present invention comprises a digital-to-analog converter, a first counter, a second counter, an oscillation circuit, and a control-logic apparatus. The digital-to-analog converter generates an output signal of the multiplier-divider circuit in accordance with the value of an input signal and a first signal. The first counter generates the first signal in response to a clock signal and the duty cycle of the input signal. The second counter generates a second signal in response to the clock signal and the period of the input signal. The oscillation circuit generates the clock signal in accordance with a third signal. The control-logic apparatus generates the third signal in response to the second signal and a constant. The first signal is correlated to the duty cycle of the input signal. The second signal is correlated to the period of the input signal.

Abstract: An apparatus and method for multiplying frequency of a clock signal are provided, wherein the apparatus provides an initial oscillator signal, compares the initial oscillator signal with a reference signal to generate a first control signal, selectively outputs one of at least one lower threshold value and at least one upper threshold value from a threshold value generation circuit to a clock output circuit according to at least the first control signal, and updates an output clock signal through a digital and logical module processing the comparison of the initial oscillator signal and the selected one of the at least one upper and lower threshold values and the comparison of the initial oscillator signal and a low level signal.

Abstract: A multiplier circuit including; a 90 degrees coupler that divides an input signal into a first input signal and a second input signal of which phase difference of a base wave is 90 degrees; a first transistor that receives the first input signal and outputs a first output signal including at least a doubled wave and a tripled wave of the first input signal; a second transistor that receives the second input signal and outputs a second output signal including at least a doubled wave and a tripled wave of the second input signal; and a combiner that restrains leakage of the first output signal or the second output signal from one of the first transistor and the second transistor to the other, combines the first output signal and the second output signal, and outputs an output signal of the tripled wave.

Abstract: There is provided a mixing circuit in which a rise of the consumption current can be suppressed while decreasing a non-linear component. The mixing circuit includes: an input unit 803 including a grounded-gate MOS transistor M1 with a source into which an input signal is input, and a grounded-source MOS transistor M2 with a gate into which the input signal is input; a frequency converter 802 for converting frequencies of a first current signal output from the grounded-gate MOS transistor M1 and a second current signal output from the grounded-source MOS transistor M2, and for generating a third current signal and a fourth current signal; a load MOS transistor M7, with a gate and a drain connected, for receiving a third current signal; and a load MOS transistor M8, with a gate and a drain connected, for receiving a fourth current signal.

Abstract: An apparatus and method for multiplying frequency of a clock signal are provided, wherein the apparatus provides an initial oscillator signal, compares the initial oscillator signal with a reference signal to generate a first control signal, selectively outputs one of at least one lower threshold value and at least one upper threshold value from a threshold value generation circuit to a clock output circuit according to at least the first control signal, and updates an output clock signal through a digital and logical module processing the comparison of the initial oscillator signal and the selected one of the at least one upper and lower threshold values and the comparison of the initial oscillator signal and a low level signal.

Abstract: According to one embodiment, there is provided a DLL circuit including a delay chain, a plurality of phase comparators, and a controller. The plurality of phase comparators receive the reference clocks individually and receive respectively the clocks from the delay elements in mutually different stages, among the delay elements of the plurality of stages. The controller simultaneously receives comparison results of the plurality of phase comparators, determines the number of stages that generate the clock of which a phase is synchronized with a phase of the reference clock from among the delay elements of the plurality of stages, and selects the number of output stages from among the delay elements of the plurality of stages based on the determined number of stages so that a delay clock having a demanded delay amount with respect to the reference clock is output.

Abstract: In one embodiment of the invention, a method for convolution of signals is disclosed including generating four phased half duty cycle clocks each being out of phase by a multiple of ninety degrees from the others; coupling the four phased half duty cycle clocks into a four phase half duty cycle mixer; and switching switches in the four phase half duty cycle mixer in response to the four phased half duty cycle clocks to convolve a differential input signal with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port.

Abstract: Systems and methods for design and operation of signal generator circuitry with output frequencies greater than the oscillator frequency. Accordingly, in a first method embodiment, a method of producing an output periodic electronic signal comprises accessing four signals having a quadrature phase relationship. First and second pairs of these signals having a one half cycle phase relationship are averaged to produce two signals having an improved duty cycle and a one-quarter cycle phase relationship. The first and second averaged periodic electronic signals are combined in an exclusive OR circuit to produce the output periodic electronic signal at twice the oscillator frequency. Advantageously, the periodic signal may comprise a desirable duty cycle of 50 percent.

Abstract: The invention discloses a mixer circuit (10, 20, 30, 410, 60) comprising a first mixer component (11, 21) with a first (13, 23) and a second (12, 22) input port for a first and a second input signal respectively and an output port (14, 24) for outputting a mixed signal. According to the invention, the mixer circuit (10, 20, 30, 410, 60) also comprises a transformer (15) which connects the first (13, 23) and second (12, 22) input ports of the mixer component (11, 21) inductively via an inverting coupling. In one embodiment, the mixer circuit (30, 410, 60) also comprises inputs for DC-bias of one (13) of the input ports and of the output port (14), as well as an impedance (31) as a filter at the output port.

Abstract: An input unit receives input of a clock signal having a voltage that varies continuously. A supply unit supplies a constant reference voltage. A selector outputs a clock signal having voltage that is changed alternately each time the voltage of the clock signal input from the input unit shifts across the reference voltage supplied from the supply unit. A calculating circuit outputs the exclusive-OR of the clock signal input from the input unit and a clock signal output from the selector.

Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Abstract: According to one embodiment, there is provided a DLL circuit including a delay chain, a plurality of phase comparators, and a controller. The plurality of phase comparators receive the reference clocks individually and receive respectively the clocks from the delay elements in mutually different stages, among the delay elements of the plurality of stages. The controller simultaneously receives comparison results of the plurality of phase comparators, determines the number of stages that generate the clock of which a phase is synchronized with a phase of the reference clock from among the delay elements of the plurality of stages, and selects the number of output stages from among the delay elements of the plurality of stages based on the determined number of stages so that a delay clock having a demanded delay amount with respect to the reference clock is output.

Abstract: A programmable waveform generator, comprising: a controllable waveform generator configured to generate an initial bandwidth signal having an initial frequency bandwidth; a tone generator configured to generate a plurality of tone signals, each tone signal having a different frequency; a first bandwidth-multiplying circuit, including a first mixer having a first input port configured to receive the low-bandwidth signal; a first switch configured to choose one of the plurality of tone signals or a phase shifted version of one of the plurality of tone signals and output the chosen signal as a first chosen tone; a controller configured to control the operation of the bandwidth multiplying block, wherein the first mixer is further configured to receive the first chosen tone at a second input port, wherein the first mixer is further configured to mix the initial bandwidth signal and the first chosen tone to generate a first bandwidth signal at an output port, the first bandwidth signal having a first frequency ban

Abstract: An amplitude-stabilized second-order predistortion circuit includes a main cell having a differential input for receiving a differential input voltage, a differential output for providing a differential output voltage, and a load control input for receiving a load control voltage; a replica cell having a differential input for receiving a differential level of peak input voltage, a differential peak output voltage, and a load control input; and a control circuit coupled to the differential output of the replica cell and driving the load control inputs of the main cell and the replica cell. The main cell and the replica cell are multiplier cells each having a variable load. The control circuit includes a first amplifier for generating a single-ended peak signal and a second amplifier for generating the load control voltage from the difference between the replica cell single-ended peak output signal and a single-ended peak reference signal.

Abstract: In a method of frequency down-converting an input signal to an output signal, a first local oscillator signal is generated as a square wave having a duty cycle of 1/3 or 2/3, and the input signal is mixed with the first oscillator signal to achieve a first down-converted signal, A second local oscillator signal is generated as a modified square wave having the same period time and a duty cycle of 2/3, of which one part has a positive amplitude and another part has a negative amplitude. The input signal is mixed with the second oscillator signal to achieve a second down-converted signal. The first oscillator signal has a delay of 1/4 of the period time to achieve a phase shift of ?/2 between the oscillator signals, and at least one down-converted signal is multiplied by a pre-calculated factor. The resulting down-converted signals are added to achieve the output signal.

Abstract: At very high frequencies, generally above 100 GHz, the performance of traditional radio frequency (RF) circuitry begins to significantly limit performance. An example is the hybrid coupler, which can have a relatively narrow 90° bandwidth in these frequency ranges. Here, however, a branch-line hybrid coupler (which has been integrated into a quadrature downconversion mixer) has been modified. Namely, an adjustable impedance network has been coupled to isolation port (which has traditionally been terminated) to substantially increase the tuning range and expand the bandwidth of the quadrature mixer within these very high frequency ranges.

Abstract: A frequency doubler comprises: a non-overlapping signal generation circuit configured to receive a first signal and a first control signal and generate a first and second non-overlapping signals, each of the first and second non-overlapping signals has a frequency of the first signal, an average of a duty cycle of the first non-overlapping signal and a duty cycle of the second non-overlapping signal is determined by the first control signal; a combination circuit configured to receive and combine the two non-overlapping signals to generate a frequency-doubled signal.

Abstract: A frequency doubler receiving an in-phase oscillating signal and an inverse oscillating signal and generating an output signal oscillating at a multiplied frequency, accordingly. The frequency doubler has a first transistor, a second transistor, a first inductor and a second inductor. A first terminal of the first transistor and a first terminal of the second transistor are at a common voltage. The frequency doubler receives the in-phase oscillating signal and the inverse oscillating signal via control terminals of the first and second transistors. The first and second inductors couple a second terminal of the first transistor and a second terminal of the second transistor to an output terminal of the frequency doubler, respectively. The first and second inductors may be separate inductance devices or, in another case, be implemented by a symmetric inductor.

Abstract: The present invention relates to an apparatus for frequency conversion, comprising: an analog-to-digital (A/D) converter, receiving and sampling an input signal according to a sampling frequency for producing a first digital signal, and the sampling frequency and the frequency of the input signal having a correspondence; a sign conversion circuit, used for receiving the first digital signal, and performing a sign conversion on the first digital signal and producing a second digital signal; a first switching module, used for selecting one of the first digital signal and the second digital signal as an output signal according to the sampling frequency; a filter, coupled to the first switching module, used for filtering the output signal from the first switching module, and producing a filter signal; and a second switching module, coupled to the filter, used for outputting the filter signal to a first output path or a second output path alternately according to the sampling frequency.

Abstract: A clock converting circuit (1) receives and then converts m-phase clocks of a frequency f having a phase difference of 1/(f×m) to n-phase clocks of the frequency f having a phase difference of 1/(f×n). A single-phase clock generating circuit (2) receives the n-phase clocks of the frequency f having a phase difference equivalent time of 1/(f×n) to generate single-phase clocks in synchronism with the rising or falling edges of the n-phase clocks. Since the frequency of the m-phase clocks inputted to the clock converting circuit (1) is ‘f’, if a desired frequency of the single-phase clocks is decided, then ‘n’ can be obtained from the equation: the frequency of the single-phase clocks is equal to (f×n). This value of ‘n’ is set to the clock converting circuit (1), thereby obtaining the n-phase clocks of the frequency f from the m-phase clocks of the frequency f to provide single-phase clocks of a desired frequency.

Abstract: The present invention provides a method for identifying a specific number of communicating points having relatively smallest accumulated path values from a plurality of transmitting points for a receiving point in a communication system. The method includes steps of: (a) defining a first coordination of each of the plurality of transmitting points and the receiving point on a complex plane; (b) transferring the first coordination of the receiving point to a second coordination thereof, in which the second coordination of the receiving point is near an origin of the complex plane; and (c) identifying the specific number of transmitting points having relatively smallest accumulated path values based on the second coordination of the receiving point.

Abstract: Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate.

Abstract: Techniques for generating quadrature signals from a local oscillator signal, wherein the generated quadrature signals have a frequency half of the local oscillator frequency. In an exemplary embodiment, two oscillators, e.g., injection locked oscillators, are provided, each oscillator having a load, a cross-coupled transistor pair, an integrating capacitor, and current injection transistors. A differential pair is coupled to the leads of each of the integrating capacitors, and the drains of the differential pair are coupled to the outputs of the other oscillator to help increase the slew rate of the output voltages of the other oscillator. The inputs to the differential pair may be first amplified to improve the gain of the differential pair. In another exemplary embodiment, the power consumption of the differential pair may be reduced by operating them in a discontinuous mode, e.g., by coupling the source voltages of the differential pair to corresponding delayed versions of the drain voltages.

Abstract: A frequency divider and a method for frequency division are disclosed that can achieve a balanced duty cycle when performing a frequency division with an odd division ratio, independently of an input frequency.

Abstract: A resistive frequency mixing apparatus includes a first frequency mixer having a source follower FET, and a second frequency mixer having a common source FET. The resistive frequency mixing apparatus perform a frequency mixing of an RF depending on an LO signal to generate a down-converted IF signal when the RF signal is applied to the source follower FET and the LO signal is applied to the common source FET. Further, the resistive frequency mixing apparatus performs a frequency mixing of an IF signal depending on an LO signal through the use of the source follower FET to produce an up-converted RF signal when the IF signal is applied to the common source FET and the LO signal is applied to the common source FET.

Abstract: A signal generator for generating an output signal with a frequency that is a multiple of a frequency of a reference signal, the signal generator including an oscillator configured to generate the output signal in dependence on the reference signal and a control signal and a control circuit configured to generate the control signal to comprise a series of pulses in which one or more of the pulses is offset in phase relative to the reference signal, the control circuit thereby being capable of controlling the frequency and/or phase of the output signal.

Abstract: A frequency multiplier system, for outputting a single phase clock of N multiplied frequency after processing an inputted clock, N?2, includes a frequency divider receiving the inputted clock, an interpolator connected with the frequency divider, a phase equalizer connected with the interpolator, and a combinational logic circuit connected with the phase equalizer, wherein the frequency divider outputs an orthogonal clock having a two-phases frequency that is a half of the inputted clock to the interpolator, the interpolator outputs a 2N-phases clock to the phase equalizer, the phase equalizer homogenizes a phase skew of the 2N-phases clock, the combinational logic circuit synthesizes the homogenized 2N-phases clock into a single phase clock of N multiplied frequency. And a method of multiplying frequency is provided. The present invention does not need feedback circuits, and therefore is stable and fast-speed , saves area, and reduces energy consumption.

Abstract: A programmable digital clock signal frequency divider module has a module clock input, module clock output, a scaling factor input, two programming inputs, and a tertiary input. A primary divider module with a primary divider module output and a clock input are coupled to the module clock input. A secondary divider module includes a multiplexer and a divide by two latch with a latch clock input coupled to the primary divider module output. In operation, logic values applied to the scaling factor input, and the programming inputs, result in the primary divider module processing a first sequence of cycles of a primary digital clock signal into a first base clock signal and processing a subsequent second sequence of cycles into a second base clock signal. The first base clock signal and the second base clock signal provide a sequence of clock pulses to the secondary divider module.

Abstract: Systems and methods for design and operation of signal generator circuitry with output frequencies greater than the oscillator frequency. Accordingly, in a first method embodiment, a method of producing an output periodic electronic signal comprises accessing four signals having a quadrature phase relationship. First and second pairs of these signals having a one half cycle phase relationship are averaged to produce two signals having an improved duty cycle and a one-quarter cycle phase relationship. The first and second averaged periodic electronic signals are combined in an exclusive OR circuit to produce the output periodic electronic signal at twice the oscillator frequency. Advantageously, the periodic signal may comprise a desirable duty cycle of 50 percent.

Abstract: Aspects of a method and system for generation of signals up to extremely high frequency using a delay block are provided. In this regard, a first signal may be delayed, via at least a portion of a plurality of delay elements and via a variable capacitance, to generate a second signal that is 90° out of phase relative to the first signal. Additionally, the first signal and second signal may be mixed to generate a third signal, wherein a frequency of the third signal is twice a frequency of said first signal. The portion of the delay elements utilized for delaying the signal may be controlled via one or more switching elements. In this regard, one of the plurality of delay elements may be selected to output the second signal. Moreover, the portion of the delay elements utilized for delaying the signal may be programmably controlled.

Abstract: Systems and methods for design and operation of signal generator circuitry with output frequencies greater than the oscillator frequency. Accordingly, in a first method embodiment, a method of producing an output periodic electronic signal comprises accessing four signals having a quadrature phase relationship. First and second pairs of these signals having a one half cycle phase relationship are averaged to produce two signals having an improved duty cycle and a one-quarter cycle phase relationship. The first and second averaged periodic electronic signals are combined in an exclusive OR circuit to produce the output periodic electronic signal at twice the oscillator frequency. Advantageously, the periodic signal may comprise a desirable duty cycle of 50 percent.