Abstract: A mixer is disclosed that includes first and second transconductance modules that, in one embodiment, includes MOSFETs configured to receive a plurality of signals that are to be mixed and a selectively coupled auxiliary current source to inject an auxiliary current into the second transconductance module approximately at or near a zero-crossing point in order to reduce flicker noise and other noise introduced into an output signal during switching. Accordingly, as a first transconductance module approaches a zero-crossing, auxiliary current is injected to reduce the current produced therefrom thereby reducing flicker noise. In a differential mixer, the amount of current produced from a transistor pair to which the signal cycle is being switched is also reduced thereby reducing noise from the transistor pair that is turning on for the next portion of a signal cycle.

Abstract: A clock multiplier circuit which generates a multiple clock having a stable frequency from a reference clock without using analog devices. The clock multiplier circuit includes ring oscillator which oscillates at a higher frequency than that of the multiple clock; a reference clock counter for counting the sampling output of the reference clock by the output clock of the ring oscillator to obtain a count value of the half cycle of the reference clock; and a multiple clock counter which, in case the value obtained by dividing the count value of the half cycle of the obtained reference clock by the multiplication factor externally given is defined as a multiple count value, inverts the multiple clock output each time it counts the multiple count value by the output clock of the ring oscillator.

Abstract: An integrated clock doubler and polarity control circuit are described. The circuit provides high speed response between an input signal and an output signal, achieving clock doubling by passing the input signal through a delay circuit and using the output of the delay circuit to select between two paths for inverting or not inverting the input signal to produce the output signal. In one embodiment, the inverting path is a CMOS inverter with input terminal receiving the input signal, output terminal providing the output signal, and power terminals controlled by the delay circuit.

Abstract: To generate an output signal (11) the frequency of which is twice the frequency of an input signal (1, 2), a delayed signal (3, 4) which is delayed relative to the input signal (1, 2) by a quarter of the latter's cycle period is generated and the output signal (11) is then generated as the difference between the rectified input signal (1, 2) and the rectified delayed signal (3, 4). The input signal (1, 2) and the delayed signal (3, 4) are advantageously rectified by using differential signals each comprising a positive component signal (1, 3) and a negative component signal (2, 4). A respective one of two transistors connected in parallel is driven by a positive component signal (1, 3) and a negative component signal (2, 4) in such a way that a positive half-wave causes the relevant transistor (5-8) to conduct and the relevant transistor (5-8) blocks in a negative half-wave.

Abstract: A frequency multiplier circuit is provided that does not rely on filtering to remove unwanted harmonics and spurious content. In one implementation, a frequency doubler comprises a first rectifier doubler stage adapted to receive a first input signal having a first frequency and output a first rectified signal having multiple harmonics; a second rectifier doubler stage adapted to receive a second input signal having the first frequency and offset in phase from the first input signal and to output a second rectified signal, which has the multiple harmonics and is offset in phase from the first rectified signal; and a differential amplifier stage adapted to sum the first and second rectified signals to produce an output signal including a desired output harmonic having a frequency that is double the first frequency. The summing results in the substantial cancellation of unwanted output harmonics in the output signal.

Abstract: A passive harmonic switch mixer is shown that is immune to self mixing of the local oscillator greatly reducing leakage noise, pulling noise, and flicker noise when used in a direct conversion receiver or direct conversion transmitter circuit. The passive harmonic switch mixermixes an input signal received on an input port with an in-phase oscillator signal and a quadrature-phase oscillator signal and outputs an output signal on an output port. Because the quadrature-phase oscillator signal is the in-phase oscillator signal phase shifted by 90 Å°, the passive harmonic switch mixer operates with a local oscillator running at half the frequency of the carrier frequency of an RF signal. Additionally, because the passive harmonic switch mixer has no active components, the DC current passing through each switch device is reduced and the associated flicker noise of the mixer is also greatly reduced.

Abstract: A signal generator device which includes a generator input (51a, 51b) for receiving input signals; a frequency multiplication section (7) including: at least two frequency multiplication inputs (551-555) communicatively connected to the generator input (51a, 51b), for receiving each at least one phase shifted signal having a phase difference with respect to the other phase shifted signal; pulse generator sections (741-745) connected to at least one of said frequency multiplication inputs for generating an output signal if said phase shifted signals has a transition from a first state to a second state. The signal generator device further includes at least one generator output (72) connected to at least one of said at least one pulse generator sections for transmitting said output signal.

Abstract: The present invention provides a method and apparatus which provides a signal with an output frequency higher than an input frequency. A phase generator generates multiple phase signals from the input signal with each phase signal having the same frequency as the input signal but being out of phase with the input signal by multiples of a set time interval. These phase signals are transmitted to a multiplexer. The multiplexer output is determined by a select word generated by an accumulator from a stored value. The accumulator is clocked by the multiplexer output and the accumulator adds a control word with a set value to the stored value in the accumulator. This addition is accomplished at every cycle of the multiplexer output. By judiciously choosing control word and the time interval between phases, frequencies higher that the input frequency can be generated at the multiplexer output.

Abstract: A clock frequency multiplier design is provided. The clock frequency multiplier includes an input stage arranged to receive an input clock signal, a first clock cycle generator stage operatively connected to the input stage and arranged to generate a low pulse on a first signal dependent on a low phase of the input clock signal, a second clock cycle generator stage operatively connected to the input stage and arranged to generate a low pulse on a second signal dependent on a high phase of the input clock signal, and an output stage operatively connected to the first clock cycle generator stage and the second clock cycle generator stage and arranged to output a high pulse on an output clock signal for every low pulse on the first signal and the second signal.

Abstract: A sinusoidal signal multiplier circuit produces an output sinusoidal signal substantially without any DC component. This sinusoidal signal multiplier circuit includes a first multiplication cell receiving a first sinusoidal signal at a first input and a second sinusoidal signal at a second input. The first multiplication cell delivers a first output signal. The sinusoidal signal multiplier circuit also includes a second multiplication cell, identical to the first multiplication cell, that receives the second sinusoidal signal at its first input and the first sinusoidal signal at its second input, and delivers a second output signal. The sinusoidal signal multiplier circuit also includes an adder circuit to add the first output signal and the second output signal to provide from the sinusoidal signal multiplier circuit an output signal substantially without any DC component.

Abstract: Providing a clock multiplier circuit which generates a multiple clock having a stable frequency from a reference clock without using analog devices

Abstract: A clock multiplier circuit is receives an input signal and generates a clock output signal. The clock multiplier circuit generates a number of pulses to be used as the clock output signal, wherein the pulses have a pulsewidth that is independent of the number of pulses generated and independent of the frequency of a clock control signal used for masking. The clock multiplier circuit includes an oscillator, a storage device for synchronization of the masking signal to the pulses and a logic circuit to generate the clock output signal. The clock multiplier circuit causes a number of unmasked pulses to be output as the output clock signal in response to the clock control signal, while other pulses are masked.

Abstract: A digital clock rate multiplier for multiplying the clock rate of an input signal to produce a multiplied output signal having a higher clock rate than the input signal. The digital clock rate multiplier includes a digital delay signal generator for developing first and second delay signals based on the input signal and a delayed version of the input signal, and a clock circuit for producing the multiplied output signal based at least partially on the first and second delay signals. The multiplied output signal may be used in high speed integrated circuits.

Abstract: According to some embodiments, a circuit provides a first set of one or more flip-flops to receive a low-swing differential clock, and a second set of one or more flip-flops to receive the low-swing differential clock. One of the one or more flip-flops of the first set is to generate a first CMOS-level sampling pulse for each cycle of the low-swing differential clock, and wherein one of the one or more flip-flops of the second set is to generate a second CMOS-level sampling pulse for each cycle of the low-swing differential clock.

Abstract: Frequency multiplying circuitry includes a couple of integrator circuits. The one integrator circuit charges a capacitor with a larger time constant via a resistor when an input clock signal is in its high level and then discharges it with a smaller time constant when the clock signal is in its low level. The other integrator circuit charges and discharges its capacitor in the opposite manner to the one integrator circuit as to the level of the clock signal. An output circuit compares the output voltages of both integrator circuits with a reference voltage and raises the level of its output signal when either one of the output voltages drops below the reference voltage. The duty ratio of the circuitry is therefore little susceptible to the frequency of the input signal and power supply voltage.

Abstract: Circuitry for a phase locked loop (PLL) includes a reference signal input and a frequency doubler. The output of the frequency doubler is a second reference signal having a frequency that is approximately twice that of the initial reference signal, and which is fed into the PLL. The frequency doubler includes a first delay circuit having an input coupled to the input of the frequency doubler; and an XOR circuit having a first input coupled to an output of the delay circuit and a second input coupled to the input of the frequency doubler. The frequency doubler can include one or more additional delay circuits in series after the first delay circuit, the output of which is provided to a multiplexer. The multiplexer includes a selection signal input for selecting an output from at least one of the delay circuits to be provided to the XOR circuit. The frequency doubler allows the PLL to have a smaller feedback divider ratio and a higher loop gain for reducing jitter.

Abstract: In one embodiment, a clock multiplier circuit is coupled to receive an input signal and is configured to generate an output clock signal. The clock multiplier circuit is configured to generate a number of pulses on the output clock signal responsive to an edge of the input signal, wherein the pulses have a width that is independent of the number of pulses generated and independent of the frequency of the input signal. The number of pulses is selectable. In another embodiment, the clock multiplier circuit includes a circuit and an oscillator. The circuit is configured to cause a number of pulses on the output clock signal of the clock multiplier circuit responsive to a control signal. The oscillator is configured to generate a stream pulses having the width, wherein the circuit is coupled to receive the stream of pulses.

Abstract: A tunable magnetic device which includes a permanent magnet in the shape of a ring, an inner aperture, a tuning member, and a field sensor secured to the permanent magnet. The tuning member may be a ferrous or magnetic material and may be secured to a non-magnetic tuning device. The inner aperture is preferably small compared to the permanent magnet. The magnetic device provides a magnetic field that is sensitive to the proximity of a ferrous object and provides a tunable mechanism to locally balance the magnetic field where the field sensor is located.

Abstract: There is provided a clock multiplication circuit simple in configuration, easy to adjust the characteristics thereof, and capable of shortening lockup time. The clock multiplication circuit is a circuit for delivering an output clock signal at a frequency that is a multiple of the frequency of a reference clock signal as inputted. A counter of the circuit counts the number of rising edges of the output clock signal ST existing during a High level period of the reference clock signal SR, thereby delivering a count value CN. A subtracter subtracts the count value CN from a reference value BN, thereby delivering a difference value DN. An adder adds the difference value DN to a preceding integrated value IN, thereby calculating a new integrated value IN. A DA converter delivers the analog control voltage AV corresponding to the integrated value IN. A VCO delivers the output clock signal ST at a frequency corresponding to the analog control voltage AV.

Abstract: A frequency rate multiplier to produce an output with an output frequency as a ratio of an input frequency is described. In one embodiment, the frequency rate multiplier includes an accumulator register to store, based upon a first clock signal having the input frequency, a binary representation of the ratio having a first most significant bit and a second most significant bit, a first adder coupled to the accumulator register in a feedback arrangement to receive the binary representation stored in the accumulator register and, based upon the first clock signal, to repeatedly add the accumulator value to a programmable parameter value representing a component of the output frequency to obtain a first result, a secondary adder coupled between the first adder and the accumulator register to receive the first result and, based upon the second most significant bit, to add a constant value to the first result forming a second result to be stored into the accumulator register.

Abstract: A digital clock rate multiplier for multiplying the clock rate of an input signal to produce a multiplied output signal having a higher clock rate than the input signal. The digital clock rate multiplier includes a digital delay signal generator for developing first and second delay signals based on the input signal and a delayed version of the input signal, and a clock circuit for producing the multiplied output signal based at least partially on the first and second delay signals. The multiplied output signal may be used in high speed integrated circuits.

Abstract: A frequency multiplying system includes a frequency multiplier for multiplying a reference frequency to generate an internal clock, a delay circuit for introducing a variable delay to the internal clock, a plurality of clock generators each for generating first clocks in number corresponding to the number of frequency multiplication. The first clocks have the reference frequency and consecutive phase shifts from the phase of the reference-frequency clock. One of the first clocks having a rising edge leading from and nearest to the rising edge of the reference clock is selected and fed back to a phase comparator for controlling the variable delay of the delay circuit.

Abstract: A frequency doubler circuit arrangement comprises a full wave rectifier circuit having an input and a first terminal, the first terminal being connected to a first supply terminal via a first current source, and the input forming an input of the frequency doubler circuit arrangement. A biased transistor circuit is also provided, having a first terminal connected to the first supply terminal via a second current source and being connected to the first terminal of the rectifier circuit. Output terminals of the rectifier circuit and the biased transistor circuit form differential output terminals of the frequency doubler circuit arrangement. The respective outputs of the rectifier circuit and the biased transistor circuit may be connected to a second supply terminal via either an active filter load or a passive filter load, such as an inductance-capacitance-resistance filter.

Abstract: A slew based clock multiplier which outputs a fraction of a master clock without having to use, as a reference, an edge of a higher frequency clock, and without having to use precision delay cells to delay edges of the master clock. The slew based clock multiplier can be configured to provide such an output as the result of a ratio of input current sources, a ratio of capacitors in the circuit, or as a result of a combination of the two.

Abstract: A frequency conversion circuit for changing a frequency of an input signal to obtain an output signal, includes: a sum holding unit holding a sum; an integrating unit updating the sum by changing the sum by a natural number a in one direction at each input of a first predetermined signal based on the input signal; and an output signal generating unit outputting a second predetermined signal as the output signal at each time at which the sum has gone over (b*N+c), where N is an integer, c is a constant integer and b is a natural number equal to or larger than a.

Abstract: A clock generation circuit globally distributes a half-frequency clock and doubles the clock frequency locally in a local clock block circuit. The circuit contains several subcircuits which detect the global clock edges (transitions), double the clock frequency and generate two shaped local clocks. A rising edge detection circuit generates a pulse in response to a rising edge of the global clock. A falling edge detection circuit generates a pulse in response to a falling edge of the global clock. A master clock SR (set/reset) latch is reset in response to either pulse and a slave clock SR latch is set in response to either pulse. A delay circuit generates a delayed signal in response to the setting of the master clock SR latch. This delayed signal sets the master clock SR latch and resets the slave clock SR latch. The master clock latch output is repowered to drive the master latches and the slave clock latch output is repowered to drive the slave latches.

Abstract: A clock multiplication technique includes driving two oscillatory circuits by an input signal. One of the circuits has an inverted input. The oscillatory circuits are characterized by a transfer function having an unstable region bounded by two stable region. Oscillations produced during operation of each of the circuits in the unstable regions are combined to produce a signal whose frequency is a multiple of the input frequency.

Abstract: A programmable frequency multiplier receives data representing a desired multiplication ratio from a first configuration register. The ratio data is transferred to the frequency multiplier concurrently with the generation of an internal delayed reset signal which holds all configuration registers in a reset condition until the frequency multiplier achieves a locked state. The configuration registers are dependent upon the internal clock signal generated by the frequency multiplier for proper operation. By causing the configuration registers to renew operation only after the stable frequency multiplier operation the danger of corrupting the information in the configuration registers is minimized.

Abstract: A method and apparatus for producing multiple clock signals having controlled duty cycles and phase relationships includes processing that begins by generating a plurality of delayed clock signals from an input clock signal based on a delay control signal. The processing then continues by producing a first multiple clock signal from a first set of a plurality of delayed clock signals and the input clock signal. The processing then continues by producing a second multiplied clock signal from a second set of the plurality of delayed clock signals, where the second multiplied clock signal is delayed from the first multiplied clock signal in accordance with a delay of at least one of the delayed clock signals. The processing then continues by generating the delayed control signal based on the first multiplied clock signal, where the delay control signal controls delays of the plurality of delayed clock signals.

Abstract: Radio system including mixer device and switching circuit and method having switching signal feedback control for enhanced dynamic range and performance. Radio apparatus including: local oscillator input port for receiving periodic sinusoidal local oscillator signal; drive circuit for generating a substantially square-wave two-voltage level switching signal including: phase splitter circuit, voltage potential isolation circuit, and square wave signal generation circuit; FET mixing device; input/output signal separation circuit; analog-to-digital converter; and feedback control circuit. Radio tuner apparatus including low-band signal processing circuit; high-band signal processing circuit including first mixer circuit operating as an up-frequency converter, amplifier circuit, second mixer circuit operating as a down-frequency converter, and feedback control circuit for adjusting a duty cycle of a mixer switching device; signal combining circuit and output processing circuit.

Abstract: A frequency multiplier design that uses a flip-flop to output (1) a first edge on an output clock signal upon receipt of a first transition of an input clock signal and (2) a second edge on the output clock signal before receipt of a second transition of the input clock signal is provided. The frequency multiplier design uses circuitry dependent on the output clock signal to reset the flip-flop after some delay but before the second transition of the input clock signal, wherein the resetting of the flip-flop causes the flip-flop to output the second edge on the output clock signal.

Abstract: A frequency multiplier and method of frequency multiplication overcome the shortcomings of those frequency multiplication systems and methods that utilize a phase locked loop or a delay locked loop, and occupy smaller chip area and consume less power when embodied in an integrated circuit. A first duty cycle correction circuit receives a first signal and generates a second signal, the frequency of which is the same as that of the first signal and the duty cycle of which is 50:50. An edge detector detects edges of the second signal and generates a third signal corresponding to the detected edges. In an optional embodiment, a second duty cycle correction circuit receives the third signal and generates a fourth signal, the frequency of which is the same as that of the third signal and the duty cycle of which is 50:50.

Abstract: The novel frequency divider has an adjustable divider ratio. Such circuits are subject to demands for ever higher clock frequencies. The circuit generates the output signal in a blockwise manner and converts it into a sequential signal in a parallel-serial converter on the output side and outputs it in a bitwise manner. As a result, the essential part of the frequency divider circuit can be operated with a slower frequency than the input frequency, which in turn enables higher input frequencies.

Abstract: A programmable mixer includes a 1st mixing stage, a 2nd mixing stage, a coupling element, and a compensation module. The 1st mixing stage is operably coupled to mix one leg of a differential input signal with a differential local oscillation. The 2nd mixing stage is operably coupled to mix the other leg of the differential input with the differential local oscillation. The coupling element couples the 1st and 2nd mixing stages together. The compensation module is operably coupled to the 1st mixing stage and/or the 2nd mixing stage to modify the operational characteristics (e.g., current, impedance, gain, et cetera) of the 1st and/or 2nd mixing stages based on a control signal.

Abstract: A high performance ADC apparatus. The inventive apparatus comprises a front end ADC baseline device providing a baseline bit size at a baseline data rate and a selected dynamic range at a baseline clock rate. A first circuit is enabled for translating upward, by a selected factor, a reference clock to produce the baseline clock rate. A second circuit is enabled for decimating the baseline data rate of the baseline device to a data rate reduced by the selected factor, so as to achieve an oversampling rate equal to the selected factor. A final circuit is employed for producing an output data rate less than the baseline clock rate by the selected factor with the final resolution.

Abstract: A ferromagnetic film, which has an inherent resonant frequency, is disposed in a cavity resonator. An electromagnetic wave, which has an input frequency equal to the resonant frequency of the ferromagnetic film, is introduced to the ferromagnetic film from an orifice of the cavity resonator to generate a ferromagnetic resonance in the ferromagnetic film, and thus, multiply the input frequency of the electromagnetic wave.

Abstract: An integrated clock doubler and polarity control circuit are described. The circuit provides high speed response between an input signal and an output signal, achieving clock doubling by passing the input signal through a delay circuit and using the output of the delay circuit to select between two paths for inverting or not inverting the input signal to produce the output signal. In one embodiment, the inverting path is a CMOS inverter with input terminal receiving the input signal, output terminal providing the output signal, and power terminals controlled by the delay circuit.

Abstract: A frequency multiplier circuit and a controlling method thereof, which measures a period of a waveform by counting cycles of a fixed frequency timing signal, and reproduces the period by adding a number of prefixed length subperiods of the fixed frequency to the cycle count, making it as equal as possible to the period, so to minimize the reproduction error.

Abstract: A mixer including a stage for inputting a voltage signal to be shifted and a shift and output stage for providing frequency-shifted signals, a biasing network of the output stage including, between a high supply and a biasing node, a constant current source in parallel with an output element of a current mirror, an input element of which receives a bias order from the input stage.

Abstract: A frequency multiplying system includes a frequency multiplier for multiplying a reference frequency to generate an internal clock, a delay circuit for introducing a variable delay to the internal clock, a plurality of clock generators each for generating first clocks in number corresponding to the number of frequency multiplication. The first clocks have the reference frequency and consecutive phase shifts from the phase of the lo reference-frequency clock. One of the first clocks having a rising edge leading from and nearest to the rising edge of the reference clock is selected and fed back to a phase comparator for controlling the variable delay of the delay circuit.

Abstract: A memory clock generator apparatus and method are implemented. The memory clock is generated, “open loop,” from a processor clock. The processor clock is gated into, and propagated through a shift register. A set of outputs tapped off of the shift register is decoded, along with a plurality of control signals, in AND-OR logic to generate a clock output, which may run at a predetermined multiple of the memory clock rate. The clock output may have one of a plurality of ratios of memory clock period to processor clock period. The control signals select the ratio. The clock generator may be started asynchronously, and, additionally, the generator outputs a signal to the processor having an edge that has a predetermined temporal relationship with the start of the clock generator.

Abstract: Timing difference division circuit with a high operating speed and a small area, assuring broadband operation. The circuit includes a logic circuit L1 generating a first gate signal and a second gate signal based on a first input signal and a second input signal, a first switch element connected across a first power source and an inner node and having a control terminal to which is fed the first gate signal, a first series circuit made up of a second switch element and a first constant current source and a second series circuit made up of a third switch element and a second constant current source. The first and second series circuits are connected in parallel across the inner node and the second power source. The first and second gate signals are connected to control terminals of the second and third switches, respectively.

Abstract: Circuitry for a phase locked loop (PLL) includes a first frequency doubler; a first equalizer having an input coupled to an output of the first frequency doubler; a second frequency doubler having an input coupled to an output of the first equalizer; and a second equalizer having an input coupled to an output of the second frequency doubler and an output which is fed into the PLL. Each frequency doubler includes a first delay circuit having an input coupled to the input of the frequency doubler; and an XOR circuit having a first input coupled to an output of the delay circuit and a second input coupled to the input of the frequency doubler. The combination of the two frequency doublers in series quadruples the reference signal into the PLL, which allows the, PLL to have a smaller feedback divider ratio and a higher loop gain for reducing jitter. Advantageously, controls for the selection of the initial reference signal are provided.

Abstract: A frequency multiplication circuit is disclosed. The circuit includes a ring oscillator formed of an even number of phase shifting stages. Each phase shifting stage provides a high frequency output comprised of harmonics of the oscillation frequency of the oscillator. An input signal having a first frequency is injected into a feedback node of the oscillator, thereby injection locking the oscillator to the input signal such that the oscillation frequency of the oscillator is equal to the first frequency. An output signal is extracted from two of the phase shifting stages. One of the harmonic frequencies may be isolated in the output signal, thereby providing a clean output at a multiple of the input frequency. When the circuit is operated at high frequencies, the output signal consists substantially of the second harmonic frequency and the circuit operates as a frequency doubler.

Abstract: An electronic device which includes a periodic signal generator (12) and a frequency multiplier circuit (14) for multiplying the frequency of the periodic signal. The multiplier circuit is formed on the basis of an EXCLUSIVE-OR gate (20), which receives the periodic signal, and a frequency divider circuit (22) connected between the output and an input of the gate. From this divider circuit it is possible to derive in a very simple way quadrature signals, which makes it feasible to perform a modulation of the type known as “zero demodulation”. The multiplier circuit can operate in accordance with CML technology (Current Mode Logic).

Abstract: A damping resistance 20 is connected between the drain D of an FET 10 and a first end T3 of an output transmission line 13, and a damping resistance 21 is connected between the drain D of an FET 11 and the first end T3. The source of the FET 10 and the gate of the FET 11 are connected to a ground plane on the back surface of a substrate through a via which has a parasitic inductance when a multiplied frequency exceeds 20 GHz. The gate of the FET 10 and the source of the FET 11 receive microwaves of the same frequency and phase through an input transmission line 12.

Abstract: A programmable IF bandwidth is achieved in either a transmitter or receiver using fixed bandwidth filters. A minimum of two IF frequencies are used. A fixed bandwidth filter that is equal to or greater than the desired IF bandwidth is used at each IF. The Local Oscillators (LO's) are tuned to frequency convert the desired signal to a frequency that is offset towards one bandedge of the fixed IF filters. A first mixer and LO relocates the desired signal to one end of a first fixed IF filter. A second mixer and LO relocates the filtered signal to the opposite end of a second IF filter. The desired bandwidth is obtained as the sum of the frequency offset of the desired signal from the nearest bandedge of the first IF filter and the frequency offset of the desired signal from the opposite bandedge of the second IF filter.

Abstract: An adjustable clock multiplier circuit is disclosed which is believed to be of advantage for inexpensively and locally generating an adjustable high frequency clock, such as may be useful for built-in self test of an embedded memory element of a digital logic integrated circuit. The clock multiplier circuit uses a pulse generator of the monostable type to generate a pulse in response to the leading edge of an input clock signal. The pulse is delayed through a programmable delay circuit and then provided as a feedback input to the pulse generator. In such manner, an output clock signal comprised of a train of pulses is generated during a cycle of the input clock signal. A counter increments a count in response to pulses generated in this way. When the pulse count is too high, a limiter outputs an ADJUST DOWN signal which slows down the output cycle time of the clock multiplier.

Abstract: A clock divider circuit includes a state machine that receives an input clock signal and generates mutually exclusive set and reset control signals. The set and reset control signals are used to control set and reset passgates, respectively, selectively providing the input clock signal to the gate terminals of a pullup and a pulldown on the output node. The set and reset control signals are also provided to a keeper circuit that maintains a value placed on the output node.

Abstract: A sinusoidal signal multiplier circuit produces an output sinusoidal signal substantially without any DC component. This sinusoidal signal multiplier circuit includes a first multiplication cell receiving a first sinusoidal signal at a first input and a second sinusoidal signal at a second input. The first multiplication cell delivers a first output signal. The sinusoidal signal multiplier circuit also includes a second multiplication cell, identical to the first multiplication cell, that receives the second sinusoidal signal at its first input and the first sinusoidal signal at its second input, and delivers a second output signal. The sinusoidal signal multiplier circuit also includes an adder circuit to add the first output signal and the second output signal to provide from the sinusoidal signal multiplier circuit an output signal substantially without any DC component.