Abstract: Disclosed are apparatus and methodology subject matters for providing improved functionality of a meter in a 2-way communications arrangement, such as an Advanced Metering System (AMS) or Infrastructure (AMI). More particularly, the present technology relates to methodologies and apparatus for providing load sensing for utility meters which preferably are operable with remote disconnect features in an Advanced Metering Infrastructure (AMI) open operational framework. Meters per the present subject matter utilize a detection circuit, and separately utilize certain remote disconnect functionality. In particular, disconnect functionality is coupled with consideration of electric load information, such as load current as determined by the metering functionality.

Abstract: Systems, methods, and computer readable media that can mitigate the effects of semiconductor aging in a semiconductor device are described. Traditional methods of mitigating semiconductor aging can be wasteful since they overcorrect for aging using a high operational voltage. The approach discussed herein steps up the operational voltage for the electronic device with time based on predetermined aging models. This allows power consumption by the electronic device, particularly early in the designed operational life, to be much less than it would otherwise be.

Abstract: According to one embodiment, a semiconductor switch includes a voltage generator, a driver, a switch section, and a power supply controller. The voltage generator is configured to generate a first potential and a negative second potential. The first potential is higher than a power supply voltage supplied to a power supply terminal. The driver is connected to an output of the voltage generator and is configured to output the first potential in response to input of high level and to output the second potential in response to input of low level. The switch section is configured to switch connection between terminals in response to an output of the driver. The power supply controller is configured to control the output of the voltage generator.

Abstract: Power switching is facilitated. In accordance with one or more embodiments, a power-switch apparatus includes a plurality of switches coupled between a voltage supply and a switched voltage output. A test control circuit operates the switches for testing a subset thereof, therein indicating a condition of the subset, which may be indicated independently from a condition of the power-switch apparatus as a whole. In some implementations, on-chip current loads are applied to emulate off-chip loads for testing the subset of switches, or individual switches.

Abstract: According to one embodiment, a circuit comprises a Capacitive Trans-Impedance Amplifier (CTIA) configured to receive a current pulse at an input and convert the current pulse to a voltage step. The voltage step is directed to a first signal path and a second signal path. When the voltage step exceeds a first threshold, the first signal path directs an enable pulse to the second signal path. The second signal path generates an output pulse when the voltage step exceeds a second threshold and the enable pulse is enabled. The second signal path comprises a first, a second, and a third amplifier to increase detection of the voltage step by the second signal path.

Abstract: An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.

Abstract: Power supply detection circuit. The power supply detection circuit includes an input circuit responsive to a core power supply voltage to generate a first output voltage at a first node. The power supply detection circuit also includes a sense logic circuit to sense a voltage drop associated with the first output voltage, when the first output voltage is at a logic level HIGH. Further, the power supply detection circuit includes a current mirror circuit responsive to the voltage drop to increase voltage of the first output voltage to an input and output power supply voltage. Moreover, the power supply detection circuit also includes an output circuit that inverts the first output voltage to generate a second output voltage at a second node.

Abstract: A power-up signal generation circuit includes a fixed level transition voltage generation unit, a variable level transition voltage generation unit, a comparison unit, and a selective output unit. The fixed level transition voltage generation unit is configured to generate a fixed level transition voltage changing at a constant level of an external voltage. The variable level transition voltage generation unit is configured to generate a variable level transition voltage changing at a level of an external voltage which varies depending on temperature. The comparison unit is configured to compare the level of the fixed level transition voltage with the level of the variable level transition voltage, and generate a selection signal. The selective output unit is configured to output the fixed level transition voltage or the variable level transition voltage as a power-up signal in response to the selection signal.

Abstract: A data processing system includes a brown-out detection circuit with a first resistive element, a first transistor, a second transistor, and a comparator. The first resistive element has a first terminal coupled to a first power supply voltage terminal, and a second terminal. The first transistor has a first current electrode coupled to the second terminal of the first resistive element, a control electrode, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode coupled to a second power supply voltage terminal. The comparator has a first input terminal coupled to the first terminal of the first resistive element, a second input terminal coupled to the second terminal of the first resistive element, and an output terminal for providing a brown-out detection signal.

Abstract: A circuit for resetting a display having at least one driver outputting a driving voltage through an output channel to a corresponding data line of a panel comprises a first switch and a second switch. The first switch is actuated by a control pulse to transfer a reset voltage to the data line of the panel. The second switch is actuated by the control pulse to electrically isolate the output channel of the driver from the data line of the panel, wherein the control pulse is asserted during transient periods resulting from power-on and power-off of the display.

Abstract: The present disclosure relates generally to power-on-reset (POR) devices for activation of a circuit block powered by a battery. The POR devices activate a circuit block when a battery voltage level of a battery voltage generated by the battery is above a dead battery condition voltage level. So that the circuit block is activated after the battery voltage level of the battery voltage has reached the dead battery condition voltage level, the POR device includes a trigger circuit. The trigger circuit is operable to receive the battery voltage and is configured to generate a trigger signal in response to the battery voltage level being charged above a trigger voltage level, which is equal to or greater than the dead battery condition voltage level. The POR circuit is also operable to generate a POR signal in an activation state and activate the circuit block.

Abstract: An electronic integrated device may include a signal generation stage arranged to generate a first signal representative of an under voltage lockout logic signal. The signal generation stage may include a voltage divider block arranged to provide an internal reference voltage signal to a bandgap core group based upon a reference signal. The bandgap core group may generate the first signal based upon the internal reference voltage signal. The bandgap core group may further include a first generation module arranged to generate a output regulated reference voltage signal based upon the internal reference voltage signal, and a second generation module arranged to generate the first signal based upon the internal reference voltage signal and a driving signal obtained by a preliminary processing of the internal reference voltage signal by a bandgap core module included within the band gap core group.

Abstract: An object is to provide a reset signal generation circuit which has a simple circuit configuration without hysteresis characteristics so as not to occupy a larger area, and is resistant to noise and can surely generate a power-on reset signal; and to provide a semiconductor device including the reset signal generation circuit. The reset signal generation circuit includes a first buffer circuit, a low pass filter, a resistor, and a second buffer circuit. An output terminal of the first buffer circuit is electrically connected to an input terminal of the low pass filter. An output terminal of the low pass filter is electrically connected to one terminal of the resistor and an input terminal of the second buffer circuit. A constant potential is supplied to the other terminal of the resistor.

Abstract: Described herein is a method and apparatus to wake-up analog bias signals with minimum delay. The apparatus comprises a first logic unit operable to adjust a signal level of a gated bias signal via a first predetermined signal in response to a power-down event; a comparator operable to compare the gated bias signal with an un-gated bias signal, and operable to generate an output signal indicating the comparison result; and a self-timed logic unit coupled to the comparator and operable to generate a wake-up signal in response to an end of the power-down event and the output signal.

Abstract: A clock receiver in a semiconductor integrated circuit includes a first clock buffer configured to buffer an external clock to generate a low frequency buffered clock in response to a first operation signal; a second clock buffer configured to buffer the external clock to generate a high frequency buffered clock in response to a second operation signal; and an internal clock generating unit configured to receive the low frequency buffered clock and the high frequency buffered clock, to control states of the first operation signal and the second operation signal and to generate an internal clock.

Abstract: In one general aspect, an apparatus can include a first voltage detect circuit configured to produce an output signal at a first power supply voltage, and configured to be in a non-monitoring state at a second power supply voltage greater than the first power supply voltage. The apparatus can include a second voltage detect circuit configured to change from a non-monitoring state to a monitoring state and configured to produce an output signal at a third power supply voltage between the first power supply voltage and the second power supply voltage. The apparatus can also include a combination circuit configured to produce a power-on-reset signal based on a logical combination of the output signal produced by the first voltage detect circuit and the output signal produced by the second voltage detect circuit.

Abstract: A reset transistor is prevented from being deteriorated when power-down occurs during a programming operation or an erasing operation. It is made possible to protect the reset transistor as well as other transistors in a circuit to which a high voltage is applied when the power-down occurs during the erasing operation on an EEPROM, because the system is not reset all at once based only on a first reset signal POR of a power-on reset circuit, but is reset based on the first reset signal POR and a low voltage detection signal LD from a low voltage detection circuit so that the reset transistor is not turned on while the high voltage is applied to it.

Abstract: A reference voltage generation circuit includes a driving control unit configured to output an enable signal during a first time period in response to a power-on reset (POR) signal, a reference voltage generation unit configured to have an initial operation determined in response to the enable signal and to output a reference voltage maintained at a constant voltage level after the first time period, and a reference voltage control unit configured to fix the voltage level of the reference voltage to a first voltage upon a voltage level of the reference voltage being increased to at least a set voltage level.

Abstract: A driving controller for use in stabilizing transient voltages from power supplies is presented. The driving controller includes a first pulse generator, a second pulse generator, and a control signal generator. The first pulse generator is configured to generate a power-up pulse signal including a pulse activating at a time of terminating a power-up period. The second pulse generator is configured to generate a detection pulse signal including a pulse that is being active from a time when an internal voltage reaches a predetermined level. The control signal generator is configured to generate an operation control signal, which controls a driving controller activating the internal voltage, in response to the power-up pulse signal and the detection pulse signal.

Abstract: A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.

Abstract: A semiconductor integrated circuit includes a constant current circuit and a start-up circuit. The constant current circuit includes a first current mirror circuit including a first and second transistors; and a second current mirror circuit including a third transistor connected to a first node and a fourth transistor connected to a second node. The start-up circuit includes a fifth transistor that supplies start-up current to the constant current circuit via the second node; a sixth transistor that uses a potential of the first node as a control voltage; a seventh transistor that is connected to a third node into which current from the sixth transistor flows and that has a diode-connected configuration; a capacitor connected to a fourth node into which current from the seventh transistor flows; and a latch circuit that controls the fifth based on a potential of the fourth node.

Abstract: A reset circuit includes a power supply, a metal-oxide-semiconductor field-effect transistor (MOSFET) that has a gate, a drain, and a source, a capacitor, a Schmitt trigger; and an inverter. When a voltage of the power supply is applied to the gate and turns on the MOSFET, the power supply charges the capacitor. After a predetermined delay time, a voltage of the capacitor reaches a threshold voltage of the Schmitt trigger and turns on the Schmitt trigger, and the capacitor discharges through the Schmitt trigger to correspondingly generate a reset signal output by the inverter to reset an electronic device.

Abstract: A startup circuitry connected to a main circuit which has at least an output terminal connected to its feedback terminal by a feedback loop. The startup circuitry is connected to the main circuit in such a manner to break the feedback loop, by having a first circuit node connected to said output terminal of said main circuit and a second circuit node connected to its feedback terminal, said startup circuitry providing a correct output voltage value during the startup phase of said main circuit.

Abstract: A reset circuit used for resetting a processing unit of an electronic device includes a switch control unit, a first switch unit, and a reset signal generation unit. The switch control unit controls the on and off state of the first switch unit according to users' operation. The reset signal generation unit outputs a reset signal after the first switch unit has been off for a predetermined time period. The reset signal generation unit stops outputting the reset signal as the first switch unit turns on. The processing unit is reset when receiving the reset signal.

Abstract: A method and apparatus for fail-safe start-up circuit for subthreshold current sources have been disclosed.

Abstract: An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.

Abstract: A voltage detection enabling circuit is disclosed. The voltage detection enabling circuit includes a reference voltage generating unit, an enabling protection unit, and an enabling judgment unit. The reference voltage generating unit is coupled to a driving voltage, and generates a reference voltage signal. The enabling protection unit receives the reference voltage signal and outputs an enabling judgment signal when the reference voltage signal is higher than a voltage parameter. Particularly, the voltage parameter is a component parameter of an electronic component. Then the enabling judgment unit determines whether an enabling signal is generated or not according to the enabling judgment signal and the driving voltage.

Abstract: A reset circuit for resetting and terminating the resetting of a reset target includes an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET), a gate drive circuit configured to switch a drain voltage of the n-channel MOSFET from a low level to a high level when a power supply voltage exceeds a predetermined threshold, a sink circuit configured to maintain the drain voltage at the low level by sinking a current flowing from a drain side of the n-channel MOSFET to the sink circuit, and a block circuit configured to block the current sinking to the sink circuit when the power supply voltage exceeds the predetermined threshold. The low level indicates a state where the reset target is in a reset state and the high level indicates a state where the reset state of the reset target is terminated.

Abstract: A power on reset circuit is capable of changing logic level of reset signal at different threshold voltages.

Abstract: A power supply system, for discharging a resume and reset (RSMRST) signal during the RSMRST signal pull down, includes a voltage regulating circuit, a delay circuit, a switch circuit, and a discharge circuit. The voltage regulating circuit receives a first voltage signal and converts the first voltage signal to a second voltage signal. The delay circuit is charged by the second voltage signal and outputs the second voltage signal once fully charged. The switch circuit receives the second voltage signal and then outputs a RSMRST signal. The discharge circuit discharges the delay circuit. The delay circuit is charged during a first state and discharged during a second state.

Abstract: In a switch mode power supply, a circuit and method for switching between an internal clock and an external synchronization clock when a stable external clock has been detected, and for switching back to operating the power supply using said internal clock when a predetermined number of sequential external clock pulses exceed a predetermined switching period dropout threshold or are otherwise missing. In one embodiment, a power system comprises a plurality of power supplies connected in parallel to a common load and where each power supply is synchronized to the external clock when a stable external clock has been detected by each.

Abstract: Apparatus and methods for a power-on-reset (POR) circuit are provided. In an example, a (POR) circuit can include a self-bias module configured to provide a reference voltage, a feedback module configured to provide a feedback voltage, a comparison module configured to compare the feedback voltage to the reference voltage and to provide an output signal, an inverter configured to couple the output of the comparison module to an enable input of the self-bias module, and a switch module coupled to the inverter, wherein the switch module and the inverter are configured to disabled the self bias module when the feedback voltage exceeds the reference voltage.

Abstract: A adaptor circuit for a power supply includes a first comparison circuit, a timing circuit; and a second comparison circuit. An input of the first comparison circuit is electrically connected to a PS_ON terminal. The first comparison circuit includes a diode. An input of the second comparison circuit is electrically connected to the diode of the first comparison circuit via the timing circuit. When the PS_ON signal is powered on, the diode is off, and the timing circuit charges up in a predetermined time, and the second comparison circuit outputs a PWR_GOOD signal after the predetermined time. When the PS_ON signal is powered off, the diode turns on, and the timing circuit discharges, so the second comparison circuit stops outputting a PWR_GOOD signal.

Abstract: Methods, devices and circuits are provided for power-on-reset circuits with low static power consumption. One such circuit includes a detector that draws current from a supply voltage. The detector detects that the supply voltage has exceeded a trip-point voltage level and then disables current draw from the detector. The detector responds to an enable signal by enabling current draw from the detector. A pulse generator generates a reset signal in response the supply voltage transitioning from a voltage below the trip point voltage level to above the trip point voltage level. A monitor detects that the supply voltage has dropped and provides, in response thereto, the enable signal to the detector to enable current draw from the portion of the detector.

Abstract: A resume and reset (RSMRST) signal output circuit, for outputting a low level voltage RSMRST signal, includes a first switch circuit, a delay circuit, and a second switch circuit. The first switch circuit receives a first voltage signal and converts the first voltage signal to a second voltage signal. The delay circuit is charged by the second voltage signal and outputs the second voltage signal it is when fully charged. The second switch circuit receives the second voltage signal and outputs the low level voltage RSMRST signal. The delay circuit is charged during a first state and discharged during a second state.

Abstract: To provide a semiconductor device which can perform initialization to a first state of two states of the first state and a second state, and which can generate a signal having a potential corresponding to the initialized first state. The present invention is the semiconductor device which can perform initialization to “0” (a first state) of two states of “0” and “1” (a second state), and which can generate a signal having a potential corresponding to initialized “0”. The semiconductor device 10 includes a plurality of flip-flop circuits 2 that are connected in parallel and which can hold the two states of “0” and “1”; and an AND circuit 3 which generates and outputs a signal having a potential corresponding to “0” when a state held in at least one flip-flop circuit 2 among the flip-flop circuits 2 is “0”. The AND circuit is connected to the flip-flop circuits 2.

Abstract: A target circuit of an electronic device is placed in a suspended mode by disconnecting the target circuit from one or more voltage sources. A refresh controller periodically initiates a refresh operation during the suspended mode by temporarily reconnecting the target circuit to the one or more voltage sources for a duration sufficient to recharge capacitances of the target circuit. The refresh controller terminates the refresh operation by disconnecting the target circuit from the one or more voltage sources, thereby continuing the suspended mode of the electronic device. The refresh controller can employ a Very Low Frequency Oscillator (VLFO) to time the frequency of refresh operations. The VLFO manages the refresh initialization timing based on the voltage across a capacitor that is selectively charged or discharged so as to implement the refresh operation. The refresh controller further can employ a counter to time the duration of the refresh operation.

Abstract: A circuit in accordance with one embodiment of the invention can include a variable voltage generator that is coupled to receive an input voltage. Furthermore, the circuit can include a non-volatile memory that is coupled to the variable voltage generator. The non-volatile memory can be coupled to receive programming for controlling an output voltage of the variable voltage generator.

Abstract: An internal voltage generating method performed in a semiconductor device, the internal voltage generating method including generating a plurality of initialization signals corresponding to a plurality of external power supply voltages; detecting a transition of a lastly-generated initialization signal from among the plurality of initialization signals and generating a detection signal; and generating a first internal voltage according to the detection signal.

Abstract: A low voltage testing circuit (125), system (100 and 200), and method for performing low-voltage testing of a circuit (127) in an integrated circuit package (104 and 204) include a selectable threshold reset circuit (125) that includes a voltage-divider ladder (320) that produces a voltage that is a fraction of a power supply voltage, a comparator (310) that compares the fraction with a reference voltage, a switch (350) that controls topology of the voltage-divider ladder thereby changing a value of the fraction, the switch controlled by a signal from a production tester (102 and 202), the signal causing a reset threshold of the selectable threshold reset circuit to be reduced below a normal reset threshold to allow testing of the circuit at a power supply voltage below the normal reset threshold.

Abstract: A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.

Abstract: An information handling system (IHS) is disclosed providing a power supply operable to provide an output current to the IHS during power initiation. The IHS may also include a first power component associated with a first power stage wherein the first power stage may have a first current threshold. Furthermore, the IHS may include a power control logic coupled to the power supply and the first power component. As such, the power control logic may be operable to communicate the first power stage to the power supply, and if the output current does not exceed the first current threshold during the first power stage, the power control logic may be operable to communicate a second power stage having a second current threshold to the power supply.

Abstract: A system can include at least one power supervisor coupled between two supply voltage terminals and including a comparator circuit configured to assert at least one output signal in response to a voltage between the terminals varying from at least one trip voltage, and a memory coupled to a programming interface for storing values that establish the at least one trip voltage; and circuitry coupled between the terminals that receives the at least one output signal, and configured to hold at least a portion of the circuitry in one mode of operation in response to the assertion of at least one output signal.

Abstract: A power-on reset circuit includes a current source circuit supplying a current that varies according to a temperature to a first node, a first transistor connected between the first node and a ground voltage and having a gate connected with a power supply voltage, and an output circuit connected with the first node and outputting a power-on reset signal in response to a signal applied to the first node.

Abstract: A signal generating apparatus, for generating a power-on-reset signal, including a bias circuit and a power-on-reset signal generating circuit is disclosed. The bias circuit is for generating an output bias voltage, and includes at least one bipolar junction transistor (BJT), wherein a base terminal of the BJT is coupled to a collector terminal of the BJT, and the output bias voltage is related to an emitter-to-base voltage of the BJT. The power-on-reset signal generating circuit is coupled to the bias circuit, and is for generating a duplicated voltage by duplicating the output bias voltage, wherein the power-on-reset signal is generated according to the duplicated voltage.

Abstract: Circuit, method for operating a circuit, and use, having a voltage regulator, which has a regulator output for providing a supply voltage, which for the supply can be connected to at least one first digital subcircuit via a first switch and to a second digital subcircuit via a second switch, wherein the voltage regulator is formed to output a first status signal dependent on the supply voltage, and to turn on the first switch by the first status signal is connected to a first control input of the first switch, and the first switch is formed to output a second status signal dependent on its switching state, and to turn on the second switch by the second status signal is connected to a second control input of the second switch.

Abstract: A power-up control circuit utilizes on-chip circuits, multiple voltages, a ring oscillator and counter, and edge and level detection circuits to guarantee reset during power-up conditions and continues the reset state with a variable length counter to guarantee a predictable reset. In addition, a clean start-up after a logical power-down condition is provided.

Abstract: A data processing system (100), such as a System-on-Chip, includes a processor (120), a memory (140) that has an expected minimum data retention voltage, and a brown-out detector (160), which includes a brown-out detection circuit (201) that has an analog output, and an output circuit (248 and 252) that converts the analog output of the brown-out detection circuit to a digital brown-out flag. The brown-out detection circuit includes a self-biased current reference, current mirrors, and a current comparator. The brown-out detector monitors voltage of a power supply of the memory, and the brown-out detector asserts the digital brown-out flag to the processor when the voltage of the power supply is at, or slightly above, a highest expected minimum data retention voltage.

Abstract: The present invention is a circuit and method for providing a reference voltage and/or one or more circuit/circuit-block enabling signals for an IC. As the voltage level on a power supply line ramps upward towards or above a nominal operating voltage, a first threshold voltage detector circuit segment may be activated and may begin to generate a bandgap reset signal once the voltage level of the power supply reaches a first threshold voltage level. The bandgap reset signal may trigger the power-up and operation of a bandgap reference circuit segment, and according to further embodiments of the present invention, a second threshold voltage detector circuit segment, which second threshold voltage detector circuit segment may be matched with the first voltage detector circuit, may generate a voltage reset signal indicating that the bandgap reference source is powering-up. Once the supply voltage reaches a third threshold reference voltage, the first detector may disable the bandgap reset.

Abstract: A resume device is provided. The device detects voltage variation in standby mode. When a big voltage variation is detected, a resume process is run and a sound is played. Volume of the sound is adjustable and power is maintained within a proper range. Thus, power consumption is saved, efficiency is improved and resume process is enhanced.