Abstract: An apparatus and method for testing is provided. An integrated circuit includes a comparison circuit that is arranged to trip based on a power supply signal reaching a trip point. The integrated circuit also includes an analog-to-digital converter that is arranged to convert the power supply signal into a digital signal. The integrated circuit also includes a storage component that stores a digital value associated with the digital signal, and provides the power supply value at an output pin of the integrated circuit. The integrated circuit includes a latch that is coupled between the analog-to-digital converter and the storage component. The latch is arranged to open when the comparison circuit trips, such that, when the comparison circuit trips, the storage component continues to store a digital value such that the digital value corresponds to the voltage associated with the power supply signal when the comparison circuit tripped.

Abstract: A system for initializing circuitry is presented. The system employs a power-on reset circuit having a threshold voltage and a programmable switch circuit. The power-on reset circuit has a detector circuit for detecting a reference voltage, and a one-sided latch for generating an output voltage reflective of the reference voltage. The detector circuit has a threshold after which the one-sided latch is activated. The programmable switch circuit receives the output voltage of the power-on reset circuit and generates an enable signal and its complement based on the status of an internal fuse. The switch point of the power-on reset circuit provides for a rapid increase in output voltage that offsets parasitic leakage current in the programmable switch circuit that can result in improper enable signal output. A high resistance direct path to ground on an output node of the power-on reset circuit prevents residual charge from causing an undesired misfire.

Abstract: A clock signal initialization circuit capable of preventing the operating frequency of a semiconductor integrated circuit from exceeding the maximum permissible frequency determined based on the power consumption of that semiconductor integrated circuit even when the PLL circuit is in a transient state at the start-up is provided. A clock signal initialization circuit for a semiconductor integrated circuit that operates in synchronization with a clock signal generated by a PLL circuit, includes a controller that derives a clock signal having a frequency no greater than a maximum permissible frequency determined based on a power consumption of the semiconductor integrated circuit as a supply clock signal to the semiconductor integrated circuit at least until the PLL circuit becomes a locked state after power-on.

Abstract: A method comprises identifying a number of power domains in a device, connecting the power domains to each other by a number of control devices during a wake-up mode of the device, and disconnecting the power domains after the wake-up mode of the device.

Abstract: Energy saving circuit of a computer is connected between a power supply and a motherboard. The energy saving circuit includes six electronic switches and a switch. When the computer is in the stand-by state, and the switch is pressed, the motherboard of the computer receives a standby voltage and the motherboard maintains the stand-by state. The energy-saving circuit can shut off the standby voltage by pressing the switch when the computer is powered off to save energy.

Abstract: The present relates to a start-up circuit, which is used for starting up a variable power supply circuit, which comprises a detection circuit and a transition circuit. The detection circuit is used for detecting an output voltage of the variable power supply and producing a detection signal. The transition circuit is coupled to the detection circuit. It transits the level of the detection signal and produces a control signal for starting up or cutting off the variable power supply. Thereby, the problem of incapability in transition can be avoided as well as achieving the purpose of low power consumption.

Abstract: A power-on reset (POR) circuit for generating a POR signal includes a current source to generate an input current. The input current is a supply voltage dependent current. The POR circuit includes a first diode operable to receive the input current to output a first voltage signal. The first diode is electrically connected in series with a resistor. Further, the POR circuit includes a second diode operable to receive the input current to output a second voltage signal. Further, the POR circuit includes a comparator operable to receive the first voltage signal and the second voltage signal to generate the POR signal at a predefined trip point. The predefined trip point is a point at which the first voltage signal equals the second voltage signal. Furthermore, the POR circuit includes a temperature compensation circuit to compensate for the variation of the predefined trip point.

Abstract: An integrated circuit includes a reset control circuit suitable for outputting a reset signal when one of a first voltage and a second voltage has lower level than a reference level, and a reset execution circuit suitable for resetting a peripheral circuit based on the reset signal.

Abstract: A signal generation device is provided to generate an output signal with constant frequency. The signal generation device includes a frequency-control circuit and a voltage-controlled delay line. The frequency-control circuit includes a pulse generator, generating a reference pulse signal according to a transition of the reference signal and a comparison pulse signal according to a transition of the comparison result signal, to re-shape the reference signal and the comparison result signal into narrow pulses suitable for clocking and resetting flip-flops.

Abstract: To increase the degree of integration of a semiconductor device such as a DCDC converter. In a semiconductor device (e.g., DCDC converter) including a controller circuit and a switching transistor, the switching transistor formed using an oxide semiconductor layer is stacked over a substrate on which the controller circuit is formed. The switching transistor includes a backgate to release heat generated in the oxide semiconductor layer. The backgate has electrical conduction with a wiring to release heat and prevent a temperature increase with integration. Moreover, for power saving, a potential hold portion including a transistor and a capacitor may be formed using part of the oxide semiconductor layer over the controller circuit. The potential hold portion is formed in a circuit for generating a bias potential in the controller circuit.

Abstract: In accordance with one embodiment, a circuit arrangement is provided including a circuit having a first terminal for a first supply potential and a second terminal for a second supply potential, wherein the first terminal is coupled to the first supply potential; a switch, by means of which the second terminal can be coupled to the second supply potential; a voltage source coupled to the second terminal; and a control device designed to open the switch in reaction to receiving a turn-off signal in an operating mode in which the switch is closed, and subsequently to control the voltage source in such a way that it varies the potential of the second terminal in the direction of the first supply potential.

Abstract: A drive circuit is provided with an input terminal for receiving input signals, an output terminal that outputs drive signals generated from the input signals, a control power supply terminal that receives a control power supply voltage, an output terminal that outputs an output signal, and a reset terminal that receives a reset signal. The output signal is given to a gate of a MOSFET. A secondary side circuit and a MOSFET constitute a step-down chopper circuit, which steps down a voltage through duty ratio control of the gate drive signal and generates a control power supply voltage. Upon receipt of a reset signal, the drive circuit stops outputting the drive signal and changes the output signal so as to reduce the control power supply voltage VCC.

Abstract: To provide a semiconductor device provided with a power-on reset circuit that can reliably detect decrease in power-supply voltage. The power-on reset circuit provided on the semiconductor device includes: a first comparison circuit that compares a primary voltage with a reference value; and a second comparison circuit that compares a secondary voltage with the reference value. The power-on reset circuit issues a reset signal based on comparison results of the first and second comparison circuits.

Abstract: A fast AC voltage detector includes a bridge rectifier connected to an AC power source, a threshold detector connected to an output of the bridge rectifier, a voltage isolation circuit connected to the threshold detector, a continuous voltage averager connected to an output of the voltage isolation circuit, and a Schmidt trigger connected to the continuous voltage averager. The Schmidt trigger is operable to output a first voltage level when a load is preset on said AC power source and a second voltage level when no load is present on said AC power source.

Abstract: A semiconductor device for ignition performing a current control function and a self shut down function can include a pulse generating circuit, a switching circuit, and a current source circuit, the three circuits together generating a pulse current that discharges a capacitor in the self shut down process. This construction can serve to suppress oscillation of a collector current Ic of the output stage IGBT in the operating processes of the current control circuit and the self shut down circuit, thus preventing or minimizing the likelihood of the ignition plug from erroneous ignition. In addition, the discharge of the capacitor in a pulsed mode can allow for down-sizing of the capacitor, which can contribute to minimization of the semiconductor device.

Abstract: To realize an optimal power-on reset in a system in which the rise of the power supply voltage is sharp. A semiconductor device according to the present invention includes two diodes connected in parallel between power supplies, and a resistor circuit and a capacitance element connected in parallel between one power supply and each of the two diodes, and outputs a comparison result between voltages outputted from the two resistor circuits as a reset signal.

Abstract: An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit.

Abstract: A time sequencing circuit for a power supply unit to ensure the correct sequencing of system voltages for a computer from a power supply unit includes first to ninth resistors, first to fifth electronic switches, and a capacitor. Each of the first to fifth electronic switches includes first to third terminals. When the power supply unit outputs all required voltages, the power supply unit outputs a high-voltage level indicating power good and the computer can start up. If any one of the required voltages is not being outputted, the power supply unit outputs a low-voltage level good signal until any non-output of voltage is cured.

Abstract: A clock control device is disclosed, which relates to a technology for reducing the amount of current consumption when a semiconductor device operates at a high speed. The clock control device includes: a chip-select-signal control block configured to generate a chip-select-control signal by latching a chip select signal, and output a fast chip select signal according to the chip-select-control signal; and a clock control block configured to drive a clock signal in response to the fast chip select signal when a command clock enable signal is activated, thereby generating a clock control signal, wherein the chip-select-signal control block latches the chip-select-control signal, and controls the chip-select-control signal to be toggled after the command clock enable signal is transitioned.

Abstract: A voltage change detection device, which reduces a deviation of a detection potential and detects a voltage change within a predetermined detection potential even when the threshold voltage of a field effect transistor is deviated. The voltage change detection device includes a first field effect transistor, a second field effect transistor, and a detection signal generator. The first field effect transistor has a drain connected to a power supply potential, a source connected to a first constant current source or a first resistor at a first node, and a gate connected to a fixed voltage. The second field effect transistor has a drain and a gate connected to the power supply potential and a source connected to a second constant current source or a second resistor at a second node. The detection signal generator generates a detection signal indicating that the power supply potential has crossed a predetermined detection potential.

Abstract: Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor device. The controller generates a power voltage signal. The semiconductor device generates a power-up signal in response to the power voltage signal, generates a first selection pulse, a second selection pulse and an initialization pulse signal, generates a first fuse signal for controlling an internal operation according to a cut state of a first fuse, and generates a second fuse signal for controlling the internal operation according to a cut state of a second fuse.

Abstract: An integrated circuit and method for using a synchronous reset pulse to reset a circuitry comprising a plurality of clock domains are disclosed. For example, the method of the present disclosure provides a reset signal that is synched to one clock, takes the synchronous signal and resets circuits in a plurality of clock domains. In order to reset a portion of the circuit which is in a particular clock domain, the reset needs to be synchronized to the clock of the particular domain.

Abstract: An integrated circuit includes a reset control circuit suitable for outputting a reset signal when one of a first voltage and a second voltage has lower level than a reference level, and a reset execution circuit suitable for resetting a peripheral circuit based on the reset signal.

Abstract: The present invention discloses a circuit and a method of adjusting system clock in low voltage detection, and a low voltage reset circuit. The circuit of adjusting system clock in low voltage detection comprises: a clock generator for supplying a clock to at least one circuit in a system; and a low voltage reset circuit for generating an adjustment signal according to a detected voltage level, so that the clock generator adjusts or stops the clock supplied to the at least one circuit in the system.

Abstract: A synchronizing circuit that is capable of generating a reproduced clock signal synchronized with a reference clock signal without causing a false lock and a clock data recovery circuit including the same are provided. To generate a clock signal synchronized with a reference clock signal associated with a data transition point that appears every predetermined period in an input data signal, the following false-lock avoidance processing is performed. That is, precharging of a first line is started when a phase control voltage applied to the first line by a charge pump falls below a lower-limit reference voltage, and the precharging of the first line is continued until the phase control voltage exceeds an upper-limit reference voltage.

Abstract: A voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared.

Abstract: In an embodiment, a circuit configured for asymmetric ageing prevention in an integrated circuit (IC) comprises a primary clock configured to generate a primary clock signal, a secondary clock configured to generate a secondary clock signal, a state determination circuit, and a control circuit. The state determination circuit is configured to determine a current operating state associated with at least one of a primary clock condition and a power-on-reset condition in the IC. The control circuit is configured to generate a control signal in response to a determination of an first operating state. The control signal is configured to facilitate a transition from the primary clock to the secondary clock upon determination of the first operating state, and a transition from a safe operating mode to a normal operating mode upon determination of a second operating state. The secondary clock is associated with a safe operating mode of the IC.

Abstract: A system for synchronizing a functional reset between first and second clock domains that operate on first and second clock signals, respectively. The system includes first, second and third synchronizer flip-flops that operate on the second clock signal. The first synchronizer flip-flop receives a functional reset signal generated by the first clock domain at its reset terminal and generates a low output signal. The low output signal causes the second synchronizer flip-flop and subsequently the third synchronizer flip-flop to generate low output signals at positive edges of the second clock signal. The low output signal generated by the third synchronizer flip-flop is used to reset the second clock domain.

Abstract: An electronic device has a power control module for causing selected functional blocks to run in a low power mode of operation, while leaving other functional blocks supplied continuously with power. A power mode control distribution network includes serially connected chains of buffers in a distribution tree for distributing power mode control signals received at a common input end to respective output ends which are connected to respective functional blocks. In the low power mode of operation the power control module causes power to be supplied continuously to output buffers at the output ends of the chains while causing power supplied to other buffers to be reduced or cut-off. The output buffers include feedback paths for causing the states of the output buffers prior to the low power mode of operation to latch during the low power mode of operation.

Abstract: Methods, apparatus, and fabrication techniques relating to improved propagation of fuse data through an integrated circuit device during scan shift reset. In some embodiments, the methods comprise loading a first value of at least one fuse bit to an integrated circuit device, during a time period when a clock signal having a first frequency is provided to at least one component of the integrated circuit device; disabling a scan shift after the loading of the first value; inactivating the clock signal after the loading of the first value; propagating the first value of the at least one fuse bit to the at least one component of the integrated circuit device; and reactivating the clock signal after the propagation of the first value.

Abstract: A voltage detection circuit includes a reference voltage and current supply configured to generate a reference voltage and a reference current; a switching element configured to shift from an off-state to an on-state when the reference voltage is higher than a predetermined threshold voltage; a current mirror circuit allowing a current corresponding to the reference current to flow through the switching element in the on-state; a capacitive element coupled in series to the current mirror circuit and charged with the current flowing through the switching element; and an inverter configured to output an enable signal activated based on a terminal voltage of the capacitive element.

Abstract: A power selector for switching power supplies is implemented using a variety of methods and devices. According to an example embodiment of the present disclosure, an arrangement provides power to a circuit by selecting between a first supply and a second supply. The first power circuit provides a regulated level of power to the integrated circuit (IC) having an operating power level specified as a circuit operating level for providing power to the IC. The second power circuit provides power to the IC. A power-signal arbitration circuit for assessing VDDREG and whether the second power circuit is to provide power to the IC as an alternative to the first power circuit providing power to the IC is based on a threshold power level indicative of the specified operating power level and the regulated level of power. Based on the power-signal arbitration circuit's assessment, providing an arbitration-control signal to the power-signal switching circuit.

Abstract: The present disclosure relates generally to power-on-reset (POR) devices for activation of a circuit block powered by a battery. The POR devices activate a circuit block when a battery voltage level of a battery voltage generated by the battery is above a dead battery condition voltage level. So that the circuit block is activated after the battery voltage level of the battery voltage has reached the dead battery condition voltage level, the POR device includes a trigger circuit. The trigger circuit is operable to receive the battery voltage and is configured to generate a trigger signal in response to the battery voltage level being charged above a trigger voltage level, which is equal to or greater than the dead battery condition voltage level. The POR circuit is also operable to generate a POR signal in an activation state and activate the circuit block.

Abstract: In aspects of the invention, a semiconductor device can include one level shift circuit that outputs a low-side input signal as a high-side signal upon raising a signal level, a pulse modulation circuit that operates in a low-side region, generates a data symbol constituted by or more bits and representing a set signal or a reset signal, where bit is defined as a combination of codes forming a pair. The pulse generation circuit can output the generated data symbol as an input signal of the level shift circuit. Also included can be a pulse demodulation circuit that operates in a high-side region, demodulates the data symbol outputted from the level shift circuit and generates a level-shifted set signal or reset signal; and a control circuit that controls conduction/non-conduction of the high-potential-side switching element on the basis of the level-shifted set signal or reset signal outputted from the pulse demodulation circuit.

Abstract: Externally configurable power-on-reset systems and methods for integrated circuits are disclosed that utilize internal power-on-reset circuitry and reset control circuitry to provide operational configurations determined by external connections. In one configuration where no dedicated external reset signal is desired, the reset control circuitry relies upon the internal power-one-reset circuitry to generate the internal reset control signal. In another configuration where an external reset signal is utilized, the reset control circuitry relies upon the external reset signal, which overrides the internal power-on-reset circuitry, to generate the internal reset control signal. In further configurations, the reset control circuitry utilizes logic circuitry controlled through a digital interface to determine when the internal reset control signal can be de-asserted.

Abstract: A power-on reset circuit has a first impedance device, a first switch device, a first capacitor, a second switch device, a third switch device, a fourth switch device, a second impedance device, a second capacitor, and a control circuit coupled to a reset input terminal of a circuit device. When the power-on reset circuit is supplied with electric power, the first switch device and the third switch device are turned on and the second switch device and the fourth switch device are turned off. When the electric power is removed from the power-on reset circuit, the first switch device and the third switch device are turned off and the second switch device and the fourth switch device are turned on. The second capacitor is discharged through the fourth switch to a voltage level being close to a ground voltage.

Abstract: A semiconductor device having a power tracking circuit configured for activating a power tracking signal for a period corresponding to a period during which an external voltage retains a level lower than a level of a low power mode reference voltage if the external voltage retains the level lower than the level of the low power mode reference voltage for at least a preselected time.

Abstract: A semiconductor device includes a power-on reset circuit configured to receive a power voltage and generate a power-on reset signal varying with a voltage level of the power voltage, an internal circuit configured to be initialized and operated in response to the power-on reset signal and generate a hold signal based on an operation mode of the internal circuit, and a reset protection circuit configured to deactivate the power-on reset circuit in response to the hold signal and provide a replacement signal for replacing the power-on reset signal to the internal circuit when the power-on reset circuit is deactivated.

Abstract: A power-on reset circuit includes a voltage detector unit to output an electrical signal in response to a power supply voltage received from a power supply terminal, an inverter to output a reset signal according to a level of the electrical signal from the voltage detector unit, a first switch unit to be turned on or off in response to the reset signal from the inverter; a first discharge unit to discharge the electrical signal in response to the power supply voltage from the first switch unit, a second switch unit to be turned on according to a start pulse signal from an external device and to receive the power supply voltage from the power supply terminal, and a second discharge unit to discharge the electrical signal in response to the power supply voltage from the second switch.

Abstract: A low power State Retention Power Gating (SRPG) cell has a retention component and a non-retention component, and is operable in a run state, a first retention state, and a second retention state. In the run state, the retention and non-retention components are powered with a supply voltage. In the first retention state, the retention component is powered at the same supply voltage as in the run state, and the non-retention component is powered down. In the second retention state, the retention component is powered at a lower supply voltage than in the run state, and the non-retention component is powered down.

Abstract: A multi-phase clock generation circuit includes a first clock buffer unit configured to invert and buffer a first internal clock and a second internal clock in response to an external clock, and to generate a third internal clock and a fourth internal clock, and a second clock buffer unit configured to invert and buffer the third internal clock and the fourth internal clock in response to the external clock, and to generate the first internal clock and the second internal clock.

Abstract: Integrated circuit devices include first and second periodic signal generators and a power down detection circuit. The first periodic signal generator is configured to generate at least a first periodic signal having a first frequency at an output thereof and the second periodic signal generator is configured to generate a second periodic signal having a second frequency less than the first frequency at an output thereof. The power down detection circuit is configured to selectively provide one or the other of the first and second periodic signals to an output terminal of the integrated circuit device, in response to monitoring a status of a signal received at an input terminal of the integrated circuit device. This received signal reflects a power down status of an external device that receives the selected one of the first and second periodic signals.

Abstract: An integrated circuit device includes a first module disposed within a first power domain, a second module disposed in a second power domain that is a sub-domain of the first power domain, first power gating logic, and second power gating logic. The first power gating logic generates a first virtual power supply for the first module. The second power gating logic is powered by the first virtual power supply for generating a second virtual power supply for the second power domain.

Abstract: Methods of multi-protocol system and integrated circuit for multi-protocol communication on a single wire are provided. The method, adopted by a multi- protocol system containing a master device, a peripheral device and a slave device coupled together by a single wire, wherein the slave device is capable of operating in first and second operation modes. The method includes: receiving, by the slave device, an analog signal from the peripheral device on a single wire in the first operation mode; transmitting, by the master device, a digital signal containing a preamble pattern on the single wire; and after detecting the preamble pattern, switching, by the slave device, from the first to the second operation mode which includes suspending receiving the analog signal on the single wire, and communicating with the master device in serial digital data via the single wire.

Abstract: In an embodiment, a circuit configured for asymmetric ageing prevention in an integrated circuit (IC) comprises a primary clock configured to generate a primary clock signal, a secondary clock configured to generate a secondary clock signal, a state determination circuit, and a control circuit. The state determination circuit is configured to determine a current operating state associated with at least one of a primary clock condition and a power-on-reset condition in the IC. The control circuit is configured to generate a control signal in response to a determination of an first operating state. The control signal is configured to facilitate a transition from the primary clock to the secondary clock upon determination of the first operating state, and a transition from a safe operating mode to a normal operating mode upon determination of a second operating state. The secondary clock is associated with a safe operating mode of the IC.

Abstract: A power-on circuit is connected to a video graphics array (VGA) connector of a display, a power supply unit (PSU), and a super input output (SIO) chip of a motherboard. The power-on circuit includes first to fourth electronic switches. The VGA connector is connected to the first electronic switch. The first electronic switch is connected to the second electronic switch. The second electronic switch is respectively connected to the third electronic switch and the fourth electronic switch. The fourth electronic switch is connected to the SIO chip. The power-on circuit could power on the motherboard via the power button on the display.

Abstract: A power on reset circuit including: a startup circuit keeping an operation signal in an operating state during a power supply rises; a bias circuit keeping the operation signal in the operating state; a BGR circuit being activated during the operating state, and outputting a fixed voltage after a predetermined time elapses; a power supply divided voltage generation circuit outputting a reference voltage; an activation detection circuit generating a control signal which becomes inactive when a power supply rises and becomes active when the fixed voltage reaches a predetermined level; a comparator circuit outputting a power on signal and detecting as the power on signal when the reference voltage is greater than the fixed voltage; and a switch turning on and fixing an output of the comparator circuit to an inactive logical value while the control signal is inactive, and turning off while the control signal is active.

Abstract: An electronic circuit comprises a reset input for receiving an input reset signal, a clock input for receiving a clock signal, and a reset output for providing an output reset signal. And it comprises a synchronous reset signal path comprising a synchronization unit, arranged to receive the input reset signal and provide the input reset signal synchronized with the clock signal to the reset output when the clock signal is available, and an asynchronous reset signal path arranged to provide the input reset signal to the reset output when a current clock availability information in a clock monitoring signal indicates that the clock signal is not available.

Abstract: A semiconductor device includes a division unit configured to divide an oscillation signal and to generate a plurality of divided signals having different division ratios each other, a delay amount determination unit configured to combine an source signal, the oscillation signal, and the plurality of divided signals and to generate a delay amount information signal with information on a given delay amount, and an edge-delayed signal output unit configured to generate at least one edge-delayed signal corresponding to the given delay amount in response to the source signal and the delay amount information signal.

Abstract: A power on reset circuit is capable of changing logic level of reset signal at different threshold voltages.