Abstract: A method for determining phase information in a radar system comprises receiving a first RF oscillator signal at a first input node and receiving a second RF oscillator signal at a second input node, wherein an arrangement having a multiplicity of delay elements is connected between the first input node and the second input node, and wherein corresponding RF signals representing a superposition of first RF oscillator signal and second RF oscillator signal are present at different positions of the arrangement. The method further comprises generating measurement values representing the amplitudes of the RF signals, generating digital representations of the measurement values, and calculating a relative phase value, representing the difference between the phase of the second RF oscillator signal and the phase of the first RF oscillator signal, on the basis of the digital representations of the measurement values.

Abstract: Disclosed is a fast lock phase-locked loop circuit for avoiding cycle slip, which belongs to the technical field of integrated circuits. The fast lock phase-locked loop circuit includes a phase frequency detector, a charge pump, an intermediate stage circuit, a loop filter, a voltage-controlled oscillator and a frequency divider. The phase frequency detector, the charge pump, the intermediate stage circuit, the loop filter and the voltage-controlled oscillator are connected in sequence; an output OUT end of the voltage-controlled oscillator is connected with an input IN end of frequency divider, and an output OUT end of the frequency divider is connected with an input IN end of the phase frequency detector to form a feedback path. The output clock frequency of the VCO and the expected frequency, i.e., the reference clock frequency and the feedback clock frequency, are prevented from being too close when the loop is started.

Abstract: A charge pump has a first branch that includes a first node connected between a first pull-up switch and a first pull-down switch and a second branch that includes a second node connected between a second pull-up switch and a second pull-down switch. The second branch is connected in parallel with the first branch. The charge pump has a voltage equalization circuit to equalize a first voltage at the first node and a second voltage at the second node. A third branch includes a third node that is connected between a third pull-up switch and a third pull-down switch. The third node is connected to the second node. The third pull-up switch and the first pull-up switch are controlled by a common pull-up signal. The third pull-down switch and the first pull-down switch are controlled by a common pull-down signal.

Abstract: A system includes a charge pump to charge wordlines of a memory array, a pump regulator coupled including a level detector, and dynamic clock logic coupled between the level detector and an oscillator. The logic provides clock signals to the charge pump and is to perform operations including: detecting that the charge pump has entered a recovery period; causing the oscillator to output, to the charge pump during a first time period of the recovery period, a first clock signal comprising a lower frequency than output during a time period preceding the recovery period; detecting that a voltage level from the level detector satisfies a trip point criterion; and causing the oscillator to output, to the charge pump during a second time period of the recovery period and responsive to the detecting, a second clock signal comprising a higher frequency than output during the time period preceding the recovery period.

Abstract: An integrated circuit chip and test method thereof are provided. The integrated circuit chip of the disclosure includes a first chip circuit and a plurality of external pins. The first chip circuit includes a plurality of first internal pads, a plurality of second internal pads and a current mirror circuit. The current mirror circuit is coupled to one of the plurality of first internal pads and the plurality of second internal pads. The plurality of external pins are coupled to the plurality of first internal pads.

Abstract: A clock signal generating circuit includes a detecting circuit configured to generate a first voltage based on first and second clock signals and adjust a level of the first voltage in response to first and second setup voltages and a resistance variable code, a comparing circuit configured to compare the first voltage and a reference voltage and output a check signal according to a comparison result, a code generating circuit configured to perform a first modulation operation for determining the resistance variable code in response to the check signal and perform a second modulation operation for determining a control code in response to the check signal, and an oscillator configured to adjust an amplitude of the first and second clock signals in response to the control code, and output the first and second clock signals having the adjusted amplitude.

Abstract: A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period, a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.

Abstract: A charge pump includes: (I) a current source; (II) a p-channel source current network including: a first p-channel transistor; a second p-channel transistor; a p-channel current switch including at least one source terminal coupled to the drain terminal of the first p-channel transistor, at least one gate coupled to a phase comparator, and at least one drain terminal; a third p-channel transistor; and (III) a n-channel sink current network including: a first n-channel transistor; a second n-channel transistor; a third n-channel transistor; a n-channel current switch comprising at least one drain terminal coupled to the source terminal of the third n-channel transistor, at least one gate coupled to the phase comparator; and at least one source terminal coupled to the drain terminal of the first n-channel transistor; and wherein the p-channel source current network and the n-channel sink current network draw a baseline current from the first p-channel transistor.

Abstract: Aspects generally relate methods and apparatuses of gate leakage detection of a transistor. A gate pad is coupled to a gate of a MOS transistor. A gate leakage detection circuit is coupled to the gate pad, wherein the gate leakage detection circuit is configured to estimate a gate leakage current. Based on the estimated gate leakage current determining a quality of a gate fabrication process.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for drivers with reduced voltage noise. Clock signals may be provided to semiconductor devices, and may be distributed throughout the device. Driven are provided along signal paths within the device which may act as buffers for the clock signals. Each clock signal may be coupled to multiple driver circuits within the driver. Each of the multiple driver circuits may be coupled to a different pair of power supply voltage lines. The driver circuits may all have a similar delay to each other.

Abstract: A charge pump circuit includes first and second capacitors, first and second controllable current generating circuits, and an interconnection circuit. A first terminal of the first controllable current generating circuit is coupled to a first plate of the first capacitor. A first terminal of the second controllable current generating circuit is coupled to a first plate of the second capacitor. During a first operation mode, the first controllable current generating circuit refers to a first control input for selectively providing a first current, and the second controllable current generating circuit refers to a second control input for selectively providing a second current. During a second operation mode, the interconnection circuit couples the first plate of the second capacitor to a first power rail, and couples both of the second plate of the second capacitor and the first plate of the first capacitor to an output terminal.

Abstract: The present invention provides a clock generating circuit, wherein the clock generating circuit includes a phase detector, an integral path, a proportional path, a bias path and an oscillator. In the operations of the clock generating circuit, the phase detector generates a detection result according to a reference signal and a feedback signal, a first charge pump within the integral path generates a first control signal according to the detection result, a second charge pump within proportional path generates a second control signal according to the detection result, a low-pass filter within the bias path filters the first control signal to generate a third control signal, and the oscillator generates a clock signal according to the first control signal, the second control signal and the third control signal.

Abstract: A unity gain buffer is shared by a charge pump and an active loop filter in a phase-locked loop. The charge pump uses the unity gain buffer to reduce current mismatch in the charge pump and the active loop filter uses the unity gain buffer in a circuit that increases the effective capacitance of the active loop filter.

Abstract: A charge-based charge pump with wide output voltage range is provided. In the charge-based charge pump, the digital logic circuit is configured to receive an up pulse signal and a down pulse signal and output a plurality of switching signals for controlling the first NMOS, the positive hold subcircuit, the first dynamic body-bias generator, the positive charge transfer subcircuit, the first static body-bias generator, the first PMOS, the negative hold subcircuit, the second dynamic body-bias generator, the negative charge transfer subcircuit and the second static body-bias generator electrically connected therewith, so as to allow the output voltage to range from ?0.84·VDD to 1.82·VDD. The charge-based charge pump is triggered by the up or down pulse signal or works in a default state, and the top plate and the bottom plate of the pump capacitor are electrically connected to different node and terminal according to the plurality of switching signals.

Abstract: The invention concerns a digital delay locked loop comprising: first and second digitally controllable delay lines (202B, 204B) coupled in series with each other, each comprising a lead portion (214, 218) and a lag portion (216, 220), the first digitally controllable delay line receiving a reference timing signal (TREF) and the second digitally controllable delay line outputting a delayed timing signal (TREF); and a time to digital converter (212) configured to evaluate a phase difference between the reference signal (TREF) and the delayed timing signal (TREF?) and to generate a first control signal (DLEAD_[0:n]) for controlling said lead portions (214, 218) or a second control signal (DLAG[0:n]) for controlling said lag portions (216, 220) based on the sign and magnitude of the phase difference.

Abstract: The inventive concept includes an oscillating circuit, a phase inverting circuit, and a phase detecting circuit. The oscillating circuit generates a first clock to be used to sample an input signal. The phase inverting circuit outputs a second clock based on the first clock. The phase detecting circuit generates a control signal having a first logic value when a phase difference between a phase of the input signal and a phase of the second clock is less than a reference value for a reference time or more. The phase detecting circuit generates the control signal having a second logic value when the phase difference is equal to or greater than the reference value or when the phase difference is less than the reference value for a time shorter than the reference time.

Abstract: A loss of signal circuit has a multiplexer and a photodiode coupled to a first input of the multiplexer. A reference signal generator is coupled to a second input of the multiplexer. An amplifier is coupled to an output of the multiplexer. A demultiplexer includes an input of the demultiplexer coupled to an output of the amplifier. A first capacitor is coupled to a first output of the demultiplexer. A second capacitor is coupled to a second output of the demultiplexer. A comparator has a first input coupled to the first output of the demultiplexer and a second input of the comparator is coupled to the second output of the demultiplexer.

Abstract: A phase locked loop (PLL) includes a multiplexer (MUX), a phase detector, a filter block, an oscillator, a frequency divider, and a clock switch controller, and achieves hitless switching between a primary clock and a redundant clock. The clock switch controller, upon detecting a condition requiring switching from the primary clock to the redundant clock, is operable to restart the feedback divider synchronously with respect to the redundant clock, and derive the output of the PLL from the redundant clock. The PLL further includes a delay block to process delayed phase error signals generated by the phase detector. The PLL performs hitless clock switching in the event of input clock loss or in response to a command to switch input clocks. The PLL further includes circuitry for estimating and cancelling residual phase errors.

Abstract: Methods and apparatus are disclosed to generate an oscillating output signal having a voltage swing greater than a voltage swing across nodes of active devices. An example oscillator includes a tank to generate an oscillating output signal in response receiving an edge of an enable signal; a feedback generator including a first gain stage forming a first feedback loop with the tank, the first feedback loop providing a first charge to maintain the oscillating output signal and a second gain stage forming a second feedback loop with the tank, the second feedback loop providing a second charge to maintain the oscillating output signal, the first and second charges combining with the oscillating output signal to generate a high voltage swing; and an attenuator connected between the tank and the feedback generator to isolate the tank from active components of the feedback generator.

Abstract: An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.

Abstract: A current control circuit and a bias generator including the current control circuit are provided. The bias generator may include a current mirror circuit configured to generate one of a first current and a second current based on a reference current; a switch circuit configured to transfer one of the first current and the second current to a variable resistor; an operational amplifier including a first input node connected to the switch circuit, a second input node that receives a reference voltage, and an output node that outputs a bias voltage; and the variable resistor connected between the first input node and the output node of the operational amplifier. By switching operation of the switch circuit, a direction in which the first current flows in the variable resistor may be different from a direction in which the second current flows in the variable resistor.

Abstract: A system, in some embodiments, comprises: an antenna; a receiver, coupled to the antenna, to receive wireless signals from another electronic device; a signal processor (SP) coupled to the receiver; and a phase locked loop (PLL), distributed among the receiver and the SP, to synchronize the frequency of a data sampling clock used by the SP with the frequency of a source clock determined by the receiver.

Abstract: A circuit includes: an oscillator configured to generate an oscillation clock signal; an NMOS transistor having a source connected with a power terminal of the oscillator, and a drain connected with a first power supply line to which a first power supply voltage is supplied; an operational amplifier configured to control a gate voltage of the NMOS transistor based on a voltage of the power terminal of the oscillator; and a charge pump. The charge pump is configured to use the oscillation clock signal or a clock signal generated from the oscillation clock signal to boost the first power supply voltage and generate a boosted power supply voltage, and to supply the boosted power supply voltage to the power terminal of the operational amplifier.

Abstract: A charge pump circuit and a phase-locked loop (PLL) system using the same are provided. The charge pump circuit includes an upper current source, a lower current source and a plurality of switches. The switches are turned on or off by an error signal to increase or decrease the control voltage of the voltage-controlled oscillator (VCO) and further control the frequency of the output signal of the VCO. When the reference frequency signal matches with the divided frequency signal from the VCO, the upper current source and the lower current source are bypassed to decrease the voltage across the MOSFET, thereby minimizes the influence of the leakage current on the control voltage of VCO. In this way, the output jitter can be reduced due to smaller magnitude of peak-to-peak voltage on the control voltage of VCO in the PLL system caused by the leakage current of the MOSFET.

Abstract: Techniques are disclosed relating to clock and data recovery circuitry. In some embodiments, a slicing circuit may be configured to sample an input signal to generate a first and second sampled data signal. In some embodiments, a phase detector circuit may be configured to compare the phases of the first and second sampled data signals. In some embodiments, a first charge pump may be configured to supply a first current to a circuit node, and a second charge pump may be configured to supply a second current to the circuit node. In some embodiments, a voltage-controlled oscillator may be configured to adjust a frequency of first and second clock signals based on a voltage of the circuit node.

Abstract: An apparatus for performing resistance control on a current sensing component in an electronic device and an associated method are provided. For example, the apparatus may comprise a power switching unit and a feedback module, and the power switching unit is utilized as the current sensing component when the power switching unit enables the power path. The feedback module may comprise: a power switching unit replica that receives a first voltage at the battery terminal and outputs a second voltage; a first current source, coupled between the power switching unit replica and a ground terminal, arranged to receive the second voltage; a reference voltage generator that generates a third voltage; and an error amplifier that receives the second voltage and the third voltage and outputs a fourth voltage, wherein the feedback module controls both of the power switching unit and the power switching unit replica according to the fourth voltage.

Abstract: According to one embodiment, a PLL circuit includes: a digital phase comparator that captures an instantaneous value of a reference clock signal, which is a digital since wave, in synchronization with a feedback clock signal, and detects a phase difference between the reference clock signal and the feedback clock signal based on the captured instantaneous value; a control voltage generation unit that generates a control voltage according to the phase difference; a voltage control oscillator that generates an output clock signal having a frequency according to the control voltage; a frequency divider that divides a frequency of the output clock signal to generate the feedback clock signal; and a control unit that amplifies the reference clock signal to be supplied to the digital phase comparator with an amplification factor according to the phase difference.

Abstract: The control device includes a control signal supply unit, a frequency changing unit, and a storage unit. The control signal supply unit generates a control signal, and supplies the generated control signal to the switching element. The storage unit stores a frequency table defining a change value of a frequency of the control signal. The frequency changing unit changes the frequency of the control signal every time a predetermined time period elapses, according to the change value defined in the frequency table.

Abstract: A CDR circuit includes a data-determination-circuit to determine a value of a data-signal, based on a first comparison-result of comparing the data-signal with first threshold-values at a timing of a clock-signal, a comparison-circuit to compare the data-signal with a second threshold-value at the timing to generate a second comparison-result, a phase-detection-circuit to detect data-patterns in which first to third symbols are temporally consecutive, based on a determination-result, the data-patterns forming that a value of the second symbol is larger than the first symbol and smaller than the third symbol, or the in value of the second symbol is smaller than the first symbol and larger than the third symbol, wherein the phase-detection-circuit generates a phase-difference-signal for controlling a phase of the clock-signal to advance or delay, based on the second comparison-result at the second symbol, and a phase-adjustment-circuit to adjust the phase of the clock-signal based on the phase-difference-signal

Abstract: One aspect relates to a method for operating a charge pump including comparing a drain voltage of a current sink transistor of the charge pump with a drain voltage of a current reference transistor, adjusting a gate bias voltage of the current sink transistor and the current reference transistor using a first error amplifier in a direction that reduces a difference between the drain voltage of the current sink transistor and the drain voltage of the current reference transistor, comparing a common-mode voltage of a loop filter with a reference voltage, and adjusting a gate bias voltage of a current source transistor of the charge pump using a second error amplifier in a direction that reduces a difference between the common-mode voltage of the loop filter and the reference voltage, wherein the first error amplifier includes a larger number of amplifying stages than the second error amplifier.

Abstract: The present disclosure provides a DRAM. The DRAM includes a memory array of memory cells, a control device and a charge pump circuit. The control device derives an information associated with a command, and determine, based on the information, whether to provide an amount of electrical energy greater than, less than, or equal to an amount of electrical energy currently required. The charge pump circuit provides the memory array with the resultant amount of electrical energy based on the determination.

Abstract: The phase-locked loop circuit according to one embodiment includes a low-pass filter including a first transistor, and a second transistor. The low-pass filter converts a first current into a first voltage, and a second current into a second voltage. The first current and the second current are generated in accordance with a pulse width of the same signal. The first transistor includes a gate input with the first voltage, a first terminal grounded, a second terminal electrically coupled to a gate of the second transistor, and a gate oxide film thicker than that of the second transistor. The second transistor includes the gate input with the second voltage.

Abstract: A method for implementing a CMOS input buffer that consumes very low current even when input levels are less than full swing. An additional optional stage enables conversion to very low voltage swing. The circuit can be manufactured with a standard CMOS processing technology and with high immunity to variation of process parameters. The circuit provides some hysteresis response, enhancing the input voltage margin.

Abstract: A method of generating an output signal includes determining a sampling period N according to a number of most significant bits (MSBs) of a divider number control signal. The method also includes determining a first logic value of a control signal by a comparing circuit based on the sampling period N, and generating a coarse tuning signal by a code generating circuit based on a phase difference signal and the control signal. When an M-th least significant bit (LSB) of the number of MSBs of the divider number control signal equals a second logic value, the sampling period N is set based on the M-th LSB of the number of MSBs of the divider number control signal.

Abstract: One aspect of the present disclosure relates to a method for operating a charge pump. The method includes comparing a drain voltage of a current sink transistor of the charge pump with a drain voltage of a current reference transistor, and adjusting a gate bias voltage of the current sink transistor and the current reference transistor in a direction that reduces a difference between the drain voltage of the current sink transistor and the drain voltage of the current reference transistor. The method also includes comparing a common-mode voltage of a loop filter with a reference voltage, and adjusting a gate bias voltage of a current source transistor of the charge pump in a direction that reduces a difference between the common-mode voltage of the loop filter and the reference voltage.

Abstract: A charge pump circuit comprises a first bipolar transistor device and a second bipolar switching device arranged in a differential pair configuration. A first terminal of each of the first and second bipolar switching devices are coupled to a supply. A second like terminal of each of the first and second bipolar switching devices are coupled together and to ground potential via a pulsed current source. A field effect switching device is also provided and the first terminal of the first bipolar switching device is coupled to the voltage supply via the field effect switching device.

Abstract: A programmable charge pump, such as for use in CMOS phase-locked loop circuits, is provided. In an example, the charge pump includes a reference stage that provides DC signals to an output stage of the charge pump. The output stage includes output switches for generating output pulses in accordance with external control signals. In an example, loop performance can be improved when an output stage of the charge pump provides a relatively large output impedance. The output switches can be isolated when the charge pump is in an OFF state. For example, respective isolation switches can be used to substantially concurrently switch source and drain terminals for each of the output switches in the charge pump. In an example, a reference stage of the charge pump can provide a buffer for reducing charge-sharing between the output switches and an output node of the output stage.

Abstract: A frequency converting element includes a mixer and a charge pump. The mixer has first and second input nodes and an output node, and an input code of the charge pump is coupled to the output node of the mixer. The charge pump receives a mixer output signal at the input node of the charge pump, and outputs an amplified version of the mixer output signal.

Abstract: Disclosed is an all-digital delay locked loop circuit based on a time-to-digital converter and a control method thereof. The all-digital delay locked loop circuit includes a phase inversion locking control circuit for determining whether or not to use a phase inversion locking algorithm by detecting a phase difference between an input clock and an output clock and outputting the input clock or an inverted input clock; and a phase synchronization unit connected to an output terminal of the phase inversion locking control circuit to receive an output signal of the phase inversion locking control circuit and a control signal and perform phase synchronization, in which the phase synchronization unit includes a digital control delay line for receiving the input clock or the inverted input clock output from the phase inversion locking control circuit and reducing a phase error between the input clock and the output clock.

Abstract: Disclosed herein is a circuit including a phase frequency detector (PFD) configured to compare phases of an input signal and a feedback signal, and to generate first and second control signals as a function of that comparison. An attenuation circuit includes a capacitor coupled in series between a node and a switching node, and is configured to charge the capacitor and disconnect the switching node from ground based on assertion of the first control signal, and discharge the capacitor and connect the switching node to ground based on assertion of the second control signal.

Abstract: A phase locked loop circuit includes a first current source that outputs a current from a first output node. The phase locked loop circuit includes a driving current circuit that includes a first voltage node set at a voltage corresponding to a supplied current and outputs a driving current from a driving current node according to the current supplied to the first voltage node. The phase locked loop circuit includes a current-voltage converter circuit that includes a second voltage node set at a supplied current. The phase locked loop circuit includes a first current switch circuit that electrically connects the first output node and the first voltage node or electrically connects the first output node and the second voltage node. The phase locked loop circuit includes an oscillator that receives the driving current and changes an oscillatory frequency according to a magnitude of the driving current.

Abstract: An apparatus including: a current source configured to generate current; a bias node coupled to the current source; a switching current source circuit coupled to the current source and the bias node to allow the current to flow through the switching current source circuit into the bias node; a biasing circuit configured to receive a control signal from a phase detector, and mirror the current flowing through the switching current source circuit in response to the control signal; and a switch device disposed between the switching current source circuit and the biasing circuit to isolate the switching current source circuit from the biasing circuit.

Abstract: A delay circuit includes a current circuit, a first current mirror circuit, a second current mirror circuit, a self-compensation circuit, and a delay capacitor. A fixed ratio is between the first current and the second current provided by the current circuit. The first current mirror circuit generates a first mirror current in response to the first current. A partial current of the second current flowing through the second current mirror circuit is a base current, and the second current mirror circuit generates a second mirror current in response to the base current. The self-compensation circuit generates a feedback current in response to the second mirror current. The delay capacitor generates a delay signal. The charging current is equal to the second current subtracting the base current. The first mirror current is the sum of the base current, the second mirror current, and the feedback current.

Abstract: It is disclosed a mixer arrangement for complex signal mixing comprising a first harmonic rejection mixer, and a second harmonic rejection mixer. Each of the harmonic rejection mixers comprises mixer unit cells wherein each mixer unit cell comprises a differential input, transconductance elements corresponding to the differential input, and a switching network arranged to switch signals from the transconductance elements to a differential output, and the first and the second harmonic rejection mixers have mutual quadrature phase relationship. The first and the second rejection mixer share a plurality of mixer unit cell, each comprising an input for receiving a signal to be mixed, an input for receiving control signals derived from a local oscillator signal, and one output for each of the first and second harmonic rejection mixers. A radio circuit comprising such a mixer arrangement and a communication apparatus comprising such a radio circuit are also disclosed.

Abstract: A phase-locked-loop includes a phase-frequency-detector (PFD) comparing phases of an input signal and feedback signal, and generating therefrom control signals. An attenuation circuit in series with the PFD includes a filter between a voltage-controlled-oscillator (VCO) control node and ground. A buffer is coupled to the VCO control node. An impedance network is coupled to the VCO control node and has an impedance element coupled to a first current source so voltage at the VCO control node increases when control signals indicate the phase of the input signal leads the feedback signal, and coupled to a second current source so voltage at the VCO control node decreases when control signals indicate a lagging phase. A VCO is coupled to the VCO control node to generate an output signal, with the phase of the output signal matching the input signal. The feedback signal is based upon the output signal.

Abstract: A charge pump circuit used for a charge pump phase-locked loop that includes a charging and discharging unit, two complementary circuit units, two operational amplifier units, an inverter unit, and a current mirror unit. The charge pump circuit resolves the matching problem of charging and discharging currents and the charge sharing problem in existing charge pump circuits. Both complementary circuit units positively and reversely compensate the charging and discharging unit to keep the charging and discharging currents of capacitors constant. Thus, the problem of the change of charging and discharging currents is resolved, the voltage linear variation of the charge pump capacitors is achieved, and the charging and discharging of the capacitors can be accurately controlled. The charge pump circuit is simple in structure, easy to integrate, high in the matching precision of the charging and discharging current sources, and suitable for low voltage and low power consumption applications.

Abstract: First and second determination units determine amplitude levels of an input data signal in synchronization with respective first and second clocks, a phase detector detects a phase relationship between the input data signal and the second clock based on the amplitude levels, and first and second phase adjusters adjust phases of the respective first and second clocks according to a detection result of the phase detector. Further, a correction unit corrects a skew generated between the first and second clocks which arrive at the first and second determination units. A correction amount determination unit determines a correction amount corresponding to the skew in the correction unit according to the detection result in the phase detector when a phase difference set between the first and second clocks is made zero.

Abstract: An apparatus relates generally to the generation of an oscillating signal. In this apparatus, a fractional-N generator is for receiving a frequency control word and a reference signal. A multiplying injection-locked oscillator is coupled to the fractional-N generator for receiving a clock signal for outputting an oscillating signal. A frequency tracking loop is coupled to the fractional-N generator for receiving the clock signal, and further coupled to the multiplying injection-locked oscillator for receiving the oscillating signal.

Abstract: The present invention is directed to signal processing system and electrical circuits. More specifically, embodiments of the present invention provide a DLL system that provides phase correction by determining a system offset based on phase differences among the delay lines. The offset is used as a part of a feedback loop to provide phase corrections for the delay lines. There are other embodiments as well.

Abstract: A self-biased Phase Locked Loop (PLL) is provided. The self-biased PLL includes a bias current generator configured to generate a bias current Ib, wherein the bias current Ib includes one or more adjustable parameters for adjusting a loop bandwidth wn of the self-biased PLL. The one or more adjustable parameters in the bias current Ib includes at least one of a reference voltage Vref and a reference frequency Fref.