Phase Lock Loop Patents (Class 327/147)
  • Patent number: 10924094
    Abstract: A pulse width modulation control circuit and a control method of a pulse width modulation signal are provided. A counter circuit generates a count value according to a phase-locked loop clock, and resets the count value according to a transition point of a synchronization signal. A comparison circuit compares the count value with a duty ratio set value, and sets the pulse width modulation signal to a high level while the count value is less than the duty ratio set value.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: February 16, 2021
    Assignee: Power Forest Technology Corporation
    Inventor: Yueh-Chang Chen
  • Patent number: 10917048
    Abstract: An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: February 9, 2021
    Assignee: Blue Danube Systems, Inc.
    Inventors: Mihai Banu, Yiping Feng
  • Patent number: 10892911
    Abstract: A controller area network receiver includes a measurement circuit, a filter circuit, and a frame detection circuit. The measurement circuit is coupled to a bit stream input terminal, and includes a timer circuit and error calculation circuitry. The timer circuit is coupled to the bit stream input terminal and a reference clock generator circuit. The error calculation circuitry is coupled to the timer circuit. The filter circuit is coupled to the measurement circuit, and includes error clipping control circuitry and clock period adjustment circuitry. The error clipping control circuitry is coupled to the error calculation circuitry. The clock period adjustment circuitry is coupled to the error calculation circuitry and the timer circuit. The frame detection circuit is coupled to the filter circuit and the bit stream input terminal.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: January 12, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Roy David Wojciechowski
  • Patent number: 10868523
    Abstract: An apparatus is provided to improve lock time of a phase locked loop, wherein the apparatus comprises: a ring oscillator including at least two delay stages, wherein each delay stage has a controllable delay; and a multiphase frequency monitor coupled to the ring oscillator to monitor frequency at an output of at least two delay stages of the ring oscillator.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: William Li, Mohsen Nasroullahi, Khoa Nguyen
  • Patent number: 10855293
    Abstract: The present disclosure discloses a quick-start clock system, which includes: a digital subsidiary circuit configured to output a digital control value; a phase-locked loop including a programmable voltage-controlled oscillator circuit and a frequency dividing circuit connected to each other and both connected to the digital subsidiary circuit, the programmable voltage-controlled oscillator circuit obtains the digital control value output, and output a clock signal according to the digital control value, the frequency dividing circuit performs a frequency dividing operation on the clock signal; and a crystal oscillator circuit connected to the phase-locked loop, which includes a crystal and an oscillation injecting circuit connected to the crystal, the oscillation injecting circuit converts the clock signal performed with the frequency dividing operation to a co-frequency fully differential signal, and inject the co-frequency fully differential signal into the crystal.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: December 1, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Mengwen Zhang
  • Patent number: 10855380
    Abstract: Techniques and circuits are proposed to increase averaging in the clock recovery band based on an amount of channel overlap in receivers using excess bandwidth for clock recovery, to mitigate the impact of spectral energy leaking into an active channel of interest from an adjacent active channel and to improve the accuracy of the phase estimate of the received transmitted clock.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: December 1, 2020
    Assignee: Ciena Corporation
    Inventors: Sadok Aouini, Bilal Riaz, Naim Ben-Hamida, Lukas Jakober, Ahmad Abdo
  • Patent number: 10833686
    Abstract: The PLL circuit comprises a phase/frequency detector (302), a loop filter (304, 306), a VCO (308) and a feedback loop (320). The VCO can be electrically disconnected from the PLL and comprises a programmable trimming circuit (316) and a current-controlled oscillator (318). For calibration the VCO is electrically disconnected from the loop filter and from the feedback loop, a constant reference voltage is applied to the voltage input (IN), a center frequency programming code (L) is applied to the trimming circuit, the center frequency programming code is iteratively adjusted until a desired center frequency is obtained, a gain programming code (K) is applied to the trimming circuit while the adjusted code is still applied, and the gain programming code is iteratively adjusted until a desired gain is obtained. Then the VCO is connected to the PLL, which is then ready for normal operation.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: November 10, 2020
    Assignee: ams AG
    Inventors: Jia Sheng Chen, Gregor Schatzberger
  • Patent number: 10826508
    Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: November 3, 2020
    Assignee: Infineon Technologies AG
    Inventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
  • Patent number: 10826504
    Abstract: A time-to-digital converter and a phase difference detection method are disclosed. The time-to-digital converter includes a detection unit and a digital control circuit. The detection unit comprising: a phase detection circuit, a first and a second clock signal are respectively coupled to an identical input terminal of the phase detection circuit and a reference signal is coupled to another input terminal of the phase detection circuit; the phase detection circuit is configured to output a pulse width corresponding to a phase difference between the first or the second clock signal and the reference signal; a filter circuit, coupled to an output terminal of the phase detection circuit; a ring oscillator circuit, coupled to an output terminal of the filter circuit and configured to output an oscillation clock signal corresponding to the pulse width. The digital control circuit is configured to provide the reference signal and receive the oscillation clock signal.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: November 3, 2020
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Pengzhan Zhang, Yong Wang, Yanhong Li, Yaomin Wu, Zhongyuan Chang
  • Patent number: 10819356
    Abstract: A PLL frequency synthesizer includes a voltage controlled oscillator that outputs an oscillation signal having a frequency corresponding to a control voltage value, a phase comparison unit that outputs a phase difference signal representing a phase difference between a feedback oscillation signal and a reference oscillation signal, a charge pump that outputs a charge and discharge current according to the phase difference, a loop filter that outputs the control voltage value, which is increased or decreased according to a charge and discharge amount of a capacitive element, to the voltage controlled oscillator, a detection unit that detects a change rate of the control voltage value, and a control unit that adjusts the charge and discharge current, a characteristic of the loop filter, or a characteristic of the voltage controlled oscillator based on a detection result of the detection unit.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: October 27, 2020
    Assignee: THINE ELECTRONICS, INC.
    Inventor: Shunichi Kubo
  • Patent number: 10809669
    Abstract: Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by a delay. Gate circuitry generates a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired delay.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Gil Horovitz, Aryeh Farber, Nisim Machluf, Evgeny Shumaker, Igal Kushnir
  • Patent number: 10768580
    Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: September 8, 2020
    Assignee: Intel IP Corporation
    Inventors: Yair Dgani, Michael Kerner, Elan Banin, Evgeny Shumaker, Gil Horovitz, Ofir Degani, Rotem Banin, Aryeh Farber, Rotem Avivi, Eshel Gordon, Tami Sela
  • Patent number: 10771010
    Abstract: A circuit device includes a processing circuit and an oscillation signal generation circuit. The processing circuit performs Kalman filter processing for a result of phase comparison between an input signal based on an oscillation signal and a reference signal and performs loop filter processing for the result of phase comparison. The oscillation signal generation circuit generates the oscillation signal of an oscillation frequency set by frequency control data which is output data of the loop filter processing by using the frequency control data and a resonator. The processing circuit estimates a truth value for an observed value of the result of phase comparison by using the Kalman filter processing.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: September 8, 2020
    Assignee: Seiko Epson Corporation
    Inventor: Yasuhiro Sudo
  • Patent number: 10761136
    Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: September 1, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert G. Gerowitz, Sarah B. Higgins, Joseph A. Iadanza
  • Patent number: 10727749
    Abstract: A dual rail power supply system and a method for providing a first voltage and a second voltage to a load are presented. The power supply system draws a load current from the dual rail power supply system. The system has a first voltage rail for coupling to a first terminal of the load, a second voltage rail for coupling to a second terminal of the load, a first power converter to provide the first voltage at the first voltage rail, a second power converter to provide the second voltage at the second voltage rail, a third power converter comprising a first output coupled to the first voltage rail and a second output coupled to the second voltage rail. The third power converter generates a slave current and provides the slave current to the load such that the load current comprises the slave current, during a first mode.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: July 28, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Cheng-Teng Chen, Ruei-Hong Peng, Yuan Wen Hsiao, Alan Somerville
  • Patent number: 10715154
    Abstract: A digitally controlled oscillator, including: a frequency divider chain, configured to perform frequency division on an input clock signal to produce K basic clock signals, wherein frequencies and periods of the K basic dock signals are the same and a time difference between two adjacent basic clock signals is a basic time unit; and a frequency synthesizer, configured to receive the K basic clock signals from the frequency divider chain, determine a first period and a second period according to the basic time unit and a frequency control word, and generate a synthetic clock signal based on the K basic clock signals, wherein the synthetic clock signal uses the first period and the second period in an alternate manner.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 14, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Liming Xiu
  • Patent number: 10659096
    Abstract: A method of performing a frequency scan at a radio includes placing the radio in an active mode and, while maintaining the radio in the active mode, for each of a plurality of target frequencies determining a coarse frequency tuning value based on the target frequency. The radio places a phase locked loop (PLL) in an open-loop configuration and while the PLL is in the open-loop configuration, programs the VCO with the coarse frequency tuning value. The radio programs the divider with a feedback adjustment based on the target frequency, places the PLL in a closed-loop configuration, and in response to the PLL reaching a settled state, performs an operation based on an output signal of the PLL.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: May 19, 2020
    Assignee: NXP USA, Inc.
    Inventors: Khurram Waheed, Carlos Alberto Neri Castellanos
  • Patent number: 10659024
    Abstract: Methods and apparatuses for communicating information are described. In some embodiments, a first integrated circuit (IC) provides a clock signal and a data signal to a second IC, wherein the data bits of the data signal are timed according to the clock signal, and wherein the frequency of the clock signal is capable of being changed even when the data signal is valid.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: May 19, 2020
    Assignee: Rambus Inc.
    Inventors: Brian Hing-Kit Tsang, Jared L. Zerbe
  • Patent number: 10644868
    Abstract: A circuit includes a phase and frequency detector circuit to generate a first phase detect signal indicative of whether a polarity of a first clock is the same as a polarity of a second clock upon occurrence of an edge of a data signal. The second clock being 90 degrees out of phase with respect to the first clock. A lock detect circuit determines, based on the first phase detect signal, that a third clock is one of frequency and phase locked to the data signal, frequency and quadrature locked to the data signal, and not frequency locked to the data signal.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: May 5, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abishek Manian, Michael Gerald Vrazel
  • Patent number: 10637484
    Abstract: A circuit device includes an oscillation signal generation circuit that generates an oscillation signal by using a resonator and a processing circuit that estimates an aging characteristic of the oscillation frequency of the resonator based on the result of comparison between the phase of a reference signal based on a satellite signal transmitted from a navigation satellite and the phase of a clock signal based on the oscillation signal. The processing circuit estimates the aging characteristic based on an index value representing the reliability of the state of the received satellite signal and the result of the phase comparison.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: April 28, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Yasuhiro Sudo
  • Patent number: 10623706
    Abstract: Disclosed herein is a control system for a laser scanning projector. The control system includes a mirror controller generating a mirror synchronization signal for an oscillating mirror apparatus based upon a mirror clock signal. The control system also includes laser modulation circuitry for generating a laser synchronization signal as a function of a laser clock signal, and generating control signals for a laser that emits a laser beam that impinges on the oscillating mirror apparatus. Synchronization circuitry is for generating the laser clock signal and sending the laser clock signal to the laser modulation circuitry, receiving the mirror synchronization signal from the mirror controller, receiving the laser synchronization signal from the laser modulation circuitry, and modifying frequency and phase of the laser clock signal for the laser as a function of the mirror synchronization signal and the laser synchronization signal.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: April 14, 2020
    Assignee: STMicroelectronics Ltd
    Inventor: Elik Haran
  • Patent number: 10615807
    Abstract: A sub-sampling phase-locked loop is described, which comprises a digital-to-time converter, a sampler module, an interpolator, and a voltage controlled oscillator. The digital-to-time converter is configured to provide a first delay signal SDLY1 at a first point t1 in time and a second delay signal SDLY2 at a second point in time t2. The sampler module is configured to provide a first sample S1 of the oscillator output signal SOUT at the first point in time t1 and a second sample S2 of the oscillator output signal SOUT at the second point in time t2. The interpolator is configured to provide a sampler signal SSAMPL by interpolating the first sample S1 and the second sample S2. The voltage controlled oscillator is configured to control the oscillator output signal SOUT based on the sampler signal SSAMPL.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: April 7, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Anders Jakobsson
  • Patent number: 10615804
    Abstract: A clock and data recovery circuit includes a first phase detector, a first charge pump, a first voltage-controlled oscillator (VCO), and an auxiliary module. The auxiliary module includes: an auxiliary clock generator, generating an auxiliary clock signal; a second phase detector, coupled to the auxiliary clock generator, comparing a phase of the auxiliary clock signal with that of a first clock signal outputted by the first VCO; and a multiplexing selecting unit, outputting a multiplexing output signal to the first charge pump according to a selection signal.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: April 7, 2020
    Assignee: MEDIATEK INC.
    Inventors: Chien-Chung Wang, Meng-Tse Weng
  • Patent number: 10585140
    Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert G. Gerowitz, Sarah B. Higgins, Joseph A. Iadanza
  • Patent number: 10541696
    Abstract: An electronic device includes: an acquisition circuit, configured to collect the current environmental information for characterizing the environment of the electronic device; a processing circuit, configured to receive the current environmental information from the acquisition circuit; determine a target frequency control word corresponding to the current environmental information according to a preset expected operating status of the electronic device; and input the target frequency control word to the TAF-DPS clock generator; the TAF-DPS clock generator, configured to generate a clock signal according to the target frequency control word, and output the clock signal to a functional circuit; the functional circuit, configured to operate in accordance with the clock signal to make the electronic device reach the expected operating status.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: January 21, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Liming Xiu
  • Patent number: 10536154
    Abstract: In a PLL circuit, a multi-band control oscillator includes multiple bands gradually increasing or decreasing a frequency in accordance with a control signal and being separated from each other, is capable of selectively switching one band among the multiple bands, and generates a signal of a frequency corresponding to the control signal in the band that is switched as a reference signal. A band setting unit sets the band of the multi-band control oscillator. The band setting unit sets the band for a present or subsequent time after a control command generator finishes outputting the control command to gradually increase or decrease from a previous start frequency to a previous stop frequency and before the control command generator starts outputting the control command to gradually increase or decrease from a present start frequency.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: January 14, 2020
    Assignee: DENSO CORPORATION
    Inventor: Tomomitsu Kitamura
  • Patent number: 10534322
    Abstract: A multi-stop time-to-digital converter (TDC, 110) includes single-stop TDCs (510) connected to output nodes of a ring oscillator (504). Other features and embodiments are also provided.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: January 14, 2020
    Assignee: Integrated Device Technology, Inc.
    Inventor: Min Chu
  • Patent number: 10530384
    Abstract: Circuits comprising: digital-to-amplitude converter (DAC), comprising: binary weighted switching transistors (BWSTs), each having gate coupled to amplitude control bit ACB, and wherein the drain of each of the BWSTs are connected together and wherein the source of each of the BWSTs are connected together; transistor M1 having gate coupled to input signal and first bias voltage BV1 and source coupled to the drains of the BWSTs; transistor M2 having gate coupled to BV2 and source coupled to the drain of M1; transistor M3 having gate coupled to BV3 and source coupled to the drain of M2; transistor having gate coupled to BV4, source coupled to the drain of M3; and inverter having input coupled to another ACB and having output coupled to the output of the DAC and the drain of M4.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: January 7, 2020
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Anandaroop Chakrabarti, Harish Krishnaswamy
  • Patent number: 10509434
    Abstract: The amount of drift in an oscillator, as a function of temperature, can be profiled by adjusting the temperature and monitoring the corresponding change in frequency of the oscillator. Temperature sensors on a computing device can provide the temperature readings for the profiling, as well as readings during operation. A system clock on the computing device can be synchronized with a reliable external clock at a regular interval, such as every fifteen minutes. Between those synchronizations, the temperature values provided by the temperature sensors can be determined and the corresponding oscillator drift determined according to the oscillator profile. The drift value can be used to adjust the output of the system clock to account for variations that may become present between the synchronization times. Effects of factors such as voltage and humidity can also be profiled to provide a more accurate timing signal.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: December 17, 2019
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventor: Marcin Piotr Kowalski
  • Patent number: 10505556
    Abstract: A PLL has a controlled oscillator with a limited frequency range. It has a phase accumulator and a phase predictor whose ranges are limited to a value K related to their bit width. K is less than the ratio of the maximum output frequency and the minimum reference frequency. The PLL locks the output frequency to a value higher than the FCW times the reference frequency. The PLL includes a means for setting the output frequency to a target frequency before achieving final lock. The PLL may have a lock detector. After acquiring lock, the PLL may reduce the bit width and K value, for example by cutting power to or switching off some of the bits, or by switching off slow counters in a multi-counter system.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: December 10, 2019
    Assignee: Perceptia IP Pty Ltd
    Inventor: Julian Jenkins
  • Patent number: 10498343
    Abstract: A phase locked loop, for a particularly in a beamforming system comprises a digital loop filter to provide a digital control word to a controllable oscillator; a frequency divider configured to provide a first feedback signal and a second feedback signal in response to an oscillator signal, the second feedback signal delayed with respect to the first feedback signal; a first comparator path configured to receive the first feedback signal and a second comparator path configured to receive the second feedback signal, each of the first and second comparator path configured to provide a respective phase delay signal to the digital loop filter in response to a respective adjustment signal and a phase deviation between a common reference signal and the respective feedback signal.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: December 3, 2019
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (publ)
    Inventors: Henrik Sjoland, Tony Pahlsson
  • Patent number: 10491200
    Abstract: Methods and apparatuses for communicating information are described. In some embodiments, a first integrated circuit (IC) provides a clock signal and a data signal to a second IC, wherein the data bits of the data signal are timed according to the clock signal, and wherein the frequency of the clock signal is capable of being changed even when the data signal is valid.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: November 26, 2019
    Assignee: RAMBUS INC.
    Inventors: Brian Hing-Kit Tsang, Jared L. Zerbe
  • Patent number: 10491219
    Abstract: A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: November 26, 2019
    Assignee: SK hynix Inc.
    Inventors: Young Suk Seo, Seung Wook Oh, Da In Im
  • Patent number: 10473716
    Abstract: A leakage current measurement circuit is provided. The leakage current measurement circuit includes a leakage generation circuit and a detection circuit. The leakage generation circuit generates a leakage current from a start time point and generates a leakage voltage signal having a voltage level that changes from an initial voltage based on the leakage current. The detection circuit generates a detection signal having an activation time, the detection signal being generated from the start time point to a detection time point, and the detection time point corresponding to when the voltage level of the leakage voltage signal reaches a target voltage.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: November 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ghil-Geun Oh, Yeon-Joong Shin, Da-Rae Jung
  • Patent number: 10476657
    Abstract: A device and a method for supporting clock transfer of multiple clock domains, where the device includes N phase frequency detectors, N filters, N clock reconstructors, and N clock domain interfaces, where N is an integer greater than or equal to two, the N clock domain interfaces are in a one-to-one correspondence with the N phase frequency detectors, the N filters, and the N clock reconstructors, the N phase frequency detectors are respectively connected to N clock sources, and at least two clock sources of the N clock sources are different. The foregoing device flexibly adapt to multiple different clock domains, implement that a single device simultaneously supports clock transfer of multiple clock domains, and flexibly satisfy user demands without adding or replacing devices.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: November 12, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Jinhui Wang
  • Patent number: 10446106
    Abstract: A display apparatus includes a display panel, a gate driving part, a data driving part and a voltage providing part. The display panel displays an image, and includes gate lines and data lines. The gate driving part outputs gate signals to the gate lines. The data driving part outputs data signals to the data lines through data channels, and outputs a dummy data signal through a dummy data channel adjacent to a side of the display panel. The voltage providing part provides a driving voltage to the data driving part, receives the dummy data signal, and controls the driving voltage provided to the data driving part based on a voltage difference of the dummy data signal according to a time of the dummy data signal.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: October 15, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Taegon Im, Boyeon Kim, Jae-Han Lee
  • Patent number: 10447253
    Abstract: A high performance phase-locked loop, the device includes a phase frequency detector, a charge pump, a loop filter, a first oscillator having inverters, configured to generate a first current, a second oscillator having a scaled version of the inverters of the first oscillator, a digital to analog converter, configured to generate a second current by multiplying the first current and a frequency code, a voltage to current converter, configured to generate a third current by converting voltage output of the loop filter to current, wherein input current to the second oscillator is sum of the second current and the third current.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: October 15, 2019
    Assignee: MegaChips Corporation
    Inventor: Abhishek Kumar Khare
  • Patent number: 10439600
    Abstract: A transceiver device includes a pulse generator, an output node, and an internal bus that couples the pulse generator and the output node. The pulse generator is configured to selectively add at least one pulse to an outlet power supply signal conveyed by the internal bus to the output node, wherein the pulse generator includes a bootstrap capacitor with a first side coupled to the internal bus and a second side selectively coupled to at least one current source. A transceiver method includes receiving an inlet power supply signal and providing an outlet power supply signal to an output node, wherein the outlet power supply signal is based on the inlet power supply signal. The transceiver method also includes selectively adding a sync or data pulse to the outlet power supply signal based on a pulse scheme and a bootstrap capacitor coupled to the output node.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 8, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Jean-Paul Eggermont
  • Patent number: 10419766
    Abstract: Presented are a system and method for distributing video over a network. The system includes a source that outputs video with a first frame rate, a transmitter, a receiver, and a sink. The transmitter receives video from the source and processes the video by encoding the video with frame boundary information, packetizing, and transmitting the video. The receiver includes a frame buffer, a timing generator, and a PLL. The receiver receives and processes the video by retrieving the frame boundary information, decoding the video into sub-frames, and writing the sub-frames to the buffer. All the processing occurs on sub-frame portions of the video in sub-frame time intervals. The receiver transmits video with a second frame rate to the sink. The timing generator generates output timing and uses the PLL to synchronize the output timing with the frame boundary information and synchronizes the first and second frame rates.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: September 17, 2019
    Assignee: Crestron Electronics, Inc.
    Inventors: Mark LaBosco, Agesino Primatic, Michael Bottiglieri
  • Patent number: 10374619
    Abstract: An oscillator circuit includes an oscillating unit, a counter unit, and a set value generator. The oscillating unit is configured to output an oscillation signal having a frequency corresponding to an input frequency setting value. The counter unit is configured to count a number of pulses of the oscillation signal during a time period corresponding to a period of a reference signal input from outside. The set value generator is configured to generate the frequency setting value every predetermined time period based on the count of the pulses counted by the counter unit.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: August 6, 2019
    Assignee: NIHON DEMPA KOGYO CO., LTD.
    Inventor: Ken Miyahara
  • Patent number: 10360104
    Abstract: A system and method of utilizing ECC memory to detect software errors and malicious activities is disclosed. In one embodiment, after a pool of memory is freed, every data word in that pool is modified to ensure that an ECC error will occur if any data word in that pool is read again. In another embodiment, the ECC memory controller is used to detect and prevent non-secure applications from accessing secure portions of memory.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: July 23, 2019
    Assignee: Silicon Laboratories Inc.
    Inventor: Thomas S. David
  • Patent number: 10355701
    Abstract: A phase lock loop (PLL) circuit includes a selection mode device before a phase detector and time-to-digital converter (TDC). In a first mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the reference clock signal. In a second mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the feedback clock signal. In a third mode, the selection mode device outputs the reference and feedback clock signals. The phase detector and TDC are configured to generate a signal: indicating the reference clock frequency in the first mode; indicating of the feedback clock frequency in the second mode; and indicating a phase/frequency difference between the feedback and reference clocks in the third mode. These signals are used to control a VCO clock signal.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: July 16, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Bupesh Pandita, Eskinder Hailu, Zhuo Gao
  • Patent number: 10348312
    Abstract: A circuit for receiving data is described. The circuit comprises a phase detector circuit comprising a detector having a first input configured to receive a sum of an oscillator phase and a phase error, and a second input coupled to an output of a first sample selector; a second sample selector having an input coupled to receive the input data and generate output data; and an eye detection circuit comprising a third sample selector having an input coupled to receive the input data and a comparator for comparing outputs of the second sample selector and the third sample selector to determine how much an eye is open for a plurality of channels. A method of implementing a receiver is also described.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: July 9, 2019
    Assignee: XILINX, INC.
    Inventors: Paolo Novellini, Antonello Di Fresco
  • Patent number: 10348309
    Abstract: A circuit device includes a phase comparator that performs phase comparison between an input signal based on an oscillation signal and a reference signal, a processor that performs a digital signal process on phase comparison result data which is a result of the phase comparison so as to generate frequency control data, and an oscillation signal generation circuit that generates the oscillation signal having an oscillation frequency which is set on the basis of the frequency control data. The processor performs the digital signal process by using data used when a hold-over state is ended in a case where the hold-over state occurs due to the absence or the abnormality of the reference signal, and then the hold-over state is ended.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: July 9, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Katsuhito Nakajima
  • Patent number: 10257439
    Abstract: A semiconductor device including a selection section that selects and outputs one video signal from plural input video signals; a clock signal output section that outputs a clock signal that corresponds to the video signal selected by the selection section; and a masking section that, for a predetermined period starting from a point when the clock signal output from the clock signal output section is switched in accordance with a switching of the selection of the video signal, performs masking processing on a synchronization signal that, among plural synchronization signals that correspond respectively to the plural video signals, corresponds to the video signal selected by the selection section. The selection section outputs the selected video signal in synchronization with the synchronization signal that corresponds to the selected video signal and that has undergone masking processing.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: April 9, 2019
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Shusaku Maeda
  • Patent number: 10250240
    Abstract: Methods and apparatuses for communicating information are described. In some embodiments, a first integrated circuit (IC) provides a clock signal and a data signal to a second IC, wherein the data bits of the data signal are timed according to the clock signal, and wherein the frequency of the clock signal is capable of being changed even when the data signal is valid.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: April 2, 2019
    Assignee: Rambus Inc.
    Inventors: Brian Hing-Kit Tsang, Jared L. Zerbe
  • Patent number: 10243671
    Abstract: Techniques and circuits are proposed to increase averaging in the clock recovery band based on an amount of channel overlap in receivers using excess bandwidth for clock recovery, to mitigate the impact of spectral energy leaking into an active channel of interest from an adjacent active channel and to improve the accuracy of the phase estimate of the received transmitted clock.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: March 26, 2019
    Assignee: Ciena Corporation
    Inventors: Sadok Aouini, Bilal Riaz, Naim Ben-Hamida, Lukas Jakober, Ahmad Abdo
  • Patent number: 10234895
    Abstract: A clock synthesizer for synthesizing an output clock locked to a selected reference clock input has a pair of phase locked loops locked to respective reference clock inputs first generating first and second frequencies. One of the frequencies is selected to control a controlled oscillator for generating an output clock. The frequency offset between the first and second frequencies at the time of switching is stored and added to the frequency controlling the controlled oscillator.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: March 19, 2019
    Assignee: Microsemi Semiconductor ULC
    Inventors: Qu Gary Jin, Chao Zhao
  • Patent number: 10236894
    Abstract: The present disclosure relates to a Digital Phase Locked Loop (DPLL) for phase locking an output signal to a reference clock signal. The DPLL comprises a phase detector for detecting a phase error of a feedback signal with respect to the reference clock signal. The DPLL comprises a digitally controlled oscillator for generating the output signal based at least on a frequency control word and at least one control signal representative of the phase error. The phase detector comprises an integer circuit for generating a first control signal representative of an integer phase error. The phase detector comprises a fractional circuit comprising a Time-to-Digital Converter (TDC) for processing the feedback signal and a delayed reference clock signal. The fractional circuit is provided for generating from the TDC output a second control signal representative of a fractional phase error. The DPLL comprises an unwrapping unit for unwrapping the TDC output.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: March 19, 2019
    Assignee: Stichting IMEC Nederland
    Inventors: Johan van den Heuvel, Yao-Hong Liu
  • Patent number: 10230383
    Abstract: A time-to-digital converter including N stages of converting circuits, where N?2, and N is an integer. Each stage of converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of converting circuit outputs a delayed signal of the stage of converting circuit; and the arbiter in each stage of converting circuit receives a sampling clock and the delayed signal of the stage of converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of converting circuit. Output signals of the N stages of converting circuits form a non-linear binary number, to indicate a time difference between a clock signal and a reference signal.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: March 12, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hao Yan, Jiale Huang, Lei Lu