Phase Lock Loop Patents (Class 327/147)
  • Patent number: 11949377
    Abstract: An device having an oscillator circuit modifiable between a first operating mode and a second operating mode, wherein the first operating mode has a first frequency accuracy and a first power consumption, wherein the second operating mode has a second frequency accuracy and a second power consumption, wherein the second frequency accuracy is more accurate than the first frequency accuracy and the second power consumption is higher than the first power consumption, and a control circuit in communication with the oscillator circuit to modify the operating mode of the oscillator circuit.
    Type: Grant
    Filed: November 15, 2022
    Date of Patent: April 2, 2024
    Assignee: Microchip Technology Incorporated
    Inventors: Andrew Bottomley, David Simmonds
  • Patent number: 11909408
    Abstract: A SerDes module clock network architecture comprises, a reference clock input port, a plurality of data transmission channels, several user logic interfaces, several frequency division branches and a phase locked loop. The reference lock input port receives an input clock and conveys the input clock to the phase locked loop, the phase locked loop receives the input lock and outputs a PLL output clock signal, the PLL output clock signal is conveyed to the plurality of data transmission channels, and the PLL output clock signal is conveyed to the frequency division branches, and after frequency division, user interface clocks are output and conveyed to the user logic interfaces. When the PLL output clock signal in a SerDes is provided to an internal dedicated channel, several frequency division branches are also divided, and after frequency division, the signal is output to the user logic interfaces for use by an FPGA.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: February 20, 2024
    Assignee: SHENZHEN PANGO MICROSYSTEMS CO., LTD.
    Inventors: Shengwen Xiang, Ying Liu
  • Patent number: 11888586
    Abstract: A low-latency network device and method for treating serial data comprising an oscillator generating a device-wide clock; a receiving physical medium attachment (PMA) having an internal data width, a symbol timing synchronization module configured to receive the parallelized sample stream; and detect therefrom synchronized bit values corresponding to bit values of the received serial data; and a physical convergence sublayer (PCS). The PMA is configured to receive the serial data, deserialize the serial data based on the device-wide clock and internal data width, whereby the received serial data is oversampled, the oversampling of the received serial data being asynchronous relative to a timing of the received serial data, and output a parallelized sample stream. The PCS is configured to receive the synchronized bit values; and delineate packets therefrom to provide packet-delineated parallelized data. The PMA, the symbol timing synchronization module and the PCS are all driven by the device-wide clock.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: January 30, 2024
    Inventor: Alexandre Raymond
  • Patent number: 11838027
    Abstract: An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The TDC is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase difference between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. The normalization circuit selects one of a plurality of candidate gain parameters stored in the normalization circuit in response to the digital output signal, for being utilized as the gain parameter.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: December 5, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventor: Yu-Che Yang
  • Patent number: 11831318
    Abstract: A frequency multiplier system includes a first frequency multiplier circuit to generate a first signal having a first frequency. The first frequency multiplier circuit includes a first post-divider circuit to divide the first frequency of the first signal to a first output frequency within a bounded first range of frequencies, and a first programmable frequency transition controller to control a transitioning frequency relationship between the first signal having the first frequency and a target signal having a desired target frequency. The system includes a second frequency multiplier circuit to generate a second signal having a second frequency.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: November 28, 2023
    Assignee: Movellus Circuits Inc.
    Inventors: Scott Howe, Xiao Wu, Jeffrey Alan Fredenburg
  • Patent number: 11728817
    Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: August 15, 2023
    Assignee: MARVELL ASIA PTE LTD
    Inventors: Mrunmay Talegaonkar, Jorge Pernillo, Junyi Sun, Praveen Prabha, Chang-Feng Loi, Yu Liao, Jamal Riani, Belal Helal, Karthik S. Gopalakrishnan, Aaron Buchwald
  • Patent number: 11569831
    Abstract: A digital phase-locked loop (DPLL) may include a time-to-digital converter (TDC) to provide a phase error signal, a frequency-divider to perform frequency division on an output signal to generate a frequency-divided output signal, a delta-sigma-modulator (DSM) to provide a test signal that represents a quantization error of the DSM, and a digital-to-time converter (DTC) to at least partially remove the quantization error from the frequency-divided output signal based on the test signal to generate the feedback signal. The DPLL may include a circuit to cause the DTC to provide a percentage of the quantization error such that the percentage of the quantization error is in the phase error signal, and a TDC calibration component to calibrate the TDC by applying a gain adjustment factor to the TDC. The gain adjustment factor may be based on the test signal and the phase error signal including the percentage of the quantization error.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: January 31, 2023
    Assignee: Infineon Technologies AG
    Inventors: Luigi Grimaldi, Dmytro Cherniak, Qianqian Ha
  • Patent number: 11545986
    Abstract: A phase locking circuit includes: a phase comparator; a pulse generation circuit; a charge pump circuit; a loop filter circuit; and a voltage-controlled oscillator. The phase comparator samples a first level in synchronization with a received reference clock, and generates a first signal to be initialized to a second level that is different from the first level by using a feedback clock. The pulse generation circuit generates a second signal in accordance with the reference clock, and controls a phase of as output signal of the voltage-controlled oscillator to be the feedback clock to have a predetermined value by inputting the first signal and the second signal as a control voltage to the voltage-controlled oscillator through the charge pump circuit and the loop filter circuit.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: January 3, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Naoaki Hiyama
  • Patent number: 11469746
    Abstract: An integrated circuit device includes a sensing circuit configured to determine a delay code from a plurality of delay codes using a phase interpolation (PI) code and a plurality of input clock phases, a variable delay circuit coupled to the sensing circuit and configured to generate a variable delay based on the delay code and generate a delayed PI code using the PI code and the delay code, the delayed PI code corresponding to a code obtained from adding the variable delay to the PI code, and a phase interpolator coupled to the variable delay circuit and configured to generate an output clock phase from the plurality of input clock phases using the delayed PI code.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: October 11, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Vishnu Kalyanamahadevi Gopalan Jawarlal, Gunjan Mandal, Avneesh Singh Verma, Sanjeeb Kumar Ghosh
  • Patent number: 11469765
    Abstract: A system and corresponding method that achieves coherency and deterministic latency (CDL) autonomously upon power on is disclosed. The system, for example, a multi-channel RF system, may require CDL with respect to the digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) assigned to the channels in the system. CDL is achieved through a timed combination of external reference and synchronization signals, resetting and disabling of various clock dividers, and enabling clock generation. In addition to synchronizing all of the clocks, the data acquisition sequence must be synchronized across all of the channels, whether they are on chips, cards, or chassis. Data acquisition synchronization may be implemented using an initiator/target or a wired OR mode configuration.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: October 11, 2022
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Charles E. Brady, Hung Loui
  • Patent number: 11409324
    Abstract: A clock compensation circuit includes a delay circuit configured to generate a plurality of second clock signals by delaying a plurality of first clock signals, a voltage conversion circuit configured to convert phase differences between the plurality of second clock signals into voltages and output converted voltages as a plurality of phase difference voltages, and a comparison circuit configured to generate a plurality of phase difference detection signals by comparing the plurality of phase difference voltages with a reference voltage. The clock compensation circuit also includes a phase error control circuit configured to generate a plurality of control signals for controlling the delay circuit, the voltage conversion circuit, and the comparison circuit according to any of the plurality of second clock signals and the plurality of phase difference detection signals.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: August 9, 2022
    Assignee: SK hynix Inc.
    Inventors: Gi Moon Hong, Kyu Dong Hwang
  • Patent number: 11398825
    Abstract: A receiving device includes a phase-locked loop (PLL) circuit having a current control oscillator, a phase detector, an integral path, and a proportional path. The current control oscillator can generate an oscillation clock based on a first and second current. The phase detector can acquire a phase detection result based on the oscillation clock and a received signal. The integral path can generate the first current based on an integrated value of the phase detection results and supply the first current to the current control oscillator. The proportional path includes a digital-to-current converter to generate the second current based on the phase detection result and supply the second current to the current control oscillator. The receiving device includes a controller configured to adjust the second current based on frequency-current characteristics of the current control oscillator.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: July 26, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Masatomo Eimitsu
  • Patent number: 11387781
    Abstract: A fast start-up crystal oscillator (XO) and a fast start-up method thereof are provided. The fast start-up XO may include a XO core circuit, a frequency synthesizer, and a fast start-up interfacing circuit, wherein the frequency synthesizer may include a voltage control oscillator (VCO) and a divider. The XO core circuit generates a XO signal having a XO frequency. The VCO generates a VCO clock having a VCO frequency, and the divider generates a divided clock having a divided frequency, wherein the VCO frequency is divided by a divisor of the divider to obtain the divided frequency. The fast start-up interfacing circuit transmits the divided clock to the XO core circuit, and then generates a reference clock having the XO frequency according to the XO signal. More particularly, the VCO frequency is calibrated according to the reference clock, in order to make the divided frequency approach the XO frequency.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: July 12, 2022
    Assignee: MEDIATEK INC.
    Inventors: Keng-Meng Chang, Yao-Chi Wang, Yanjie Mo, Sen-You Liu, Chun-Ming Lin
  • Patent number: 11362668
    Abstract: A method of converting an N-bit digital code into analog output currents includes switchably connecting a first number of PN junctions to a positive output terminal and a second number of PN junctions to a negative output terminal based on the N-bit digital code; and switchably connecting a plurality of additional PN junctions to the positive output terminal and the negative output terminal based on the N-bit digital code, including connecting a first number of additional PN junctions to the positive output terminal based on the N-bit digital code and connecting a second number of additional PN junctions to the negative output terminal based on the N-bit digital code such that a first sum of the first number of PN junctions and the first number of additional PN junctions is equal to a second sum of the second number of PN junctions and the second number of additional PN junctions.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: June 14, 2022
    Inventors: Florian Brugger, Wolfgang Milachowski, Christoph Schroers
  • Patent number: 11265010
    Abstract: An incremental analog-to-digital converter (ADC) with high accuracy. The incremental ADC has a delta-sigma modulator, performing delta-sigma modulation on an analog input signal to output a quantized signal, and a digital filter, receiving the quantized signal to generate a digital representation of the analog input signal. A loop filter of the delta-sigma modulator has a preset circuit. In the preset circuit, the output terminal of the loop filter is preset rather than being reset during the reset phase of the incremental ADC.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: March 1, 2022
    Assignee: MEDIATEK INC.
    Inventors: Yun-Shiang Shu, Su-Hao Wu, Hung-Yi Hsieh, Albert Yen-Chih Chiou
  • Patent number: 11258630
    Abstract: A controller area network receiver includes a measurement circuit, a filter circuit, and a frame detection circuit. The measurement circuit is coupled to a bit stream input terminal, and includes a timer circuit and error calculation circuitry. The timer circuit is coupled to the bit stream input terminal and a reference clock generator circuit. The error calculation circuitry is coupled to the timer circuit. The filter circuit is coupled to the measurement circuit, and includes error clipping control circuitry and clock period adjustment circuitry. The error clipping control circuitry is coupled to the error calculation circuitry. The clock period adjustment circuitry is coupled to the error calculation circuitry and the timer circuit. The frame detection circuit is coupled to the filter circuit and the bit stream input terminal.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: February 22, 2022
    Assignee: Texas Instruments Incorporated
    Inventor: Roy David Wojciechowski
  • Patent number: 11218154
    Abstract: An integrated circuit according to an embodiment of the disclosure may include a plurality of function blocks, a spread spectrum clock (SSC) generator that generates a spread spectrum clock based on a frequency modulation rate value, a clock distribution circuit that distributes the generated spread spectrum clock into the plurality of function blocks, a memory that stores predetermined frequency modulation rate values respectively corresponding to the plurality of function blocks, and a control circuit, and the control circuit may be configured to generate the spread spectrum clock based on a smaller frequency modulation rate value among a first frequency modulation rate value and a second frequency modulation rate value respectively corresponding to a first function block and a second function block, which are operating, from among the plurality of function blocks. Moreover, various embodiment found through the present disclosure are possible.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: January 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungjoon Yoon, Cheolho Lee
  • Patent number: 11190194
    Abstract: A digital phase-locked loop has a digitally controlled oscillator with a first coarse tuning field for coarse tuning of the oscillator frequency, a second coarse tuning field for tuning of the oscillator frequency at finer intervals than the first coarse tuning field, and a fine tuning field for tuning the oscillator to an output frequency at finer intervals than the second coarse tuning field. The second coarse tuning field provides open loop tuning and is linear and connected parallel to the first coarse tuning field. The second coarse tuning field provides wide field temperature compensation and frequency error determination at start up based on an interpolated frequency value obtained prior to start up. Faster settling is provided with less complex algorithms.
    Type: Grant
    Filed: March 31, 2018
    Date of Patent: November 30, 2021
    Assignee: Apple Inc.
    Inventors: Christian Wicpalek, Andreas Roithmeier, Andreas Leistner, Thomas Gustedt, Herwig Dietl-Steinmaurer, Tobias Buckel
  • Patent number: 11177811
    Abstract: Systems and methods described herein are related to clock signal generation for synchronous electronic circuitry. Power management in electronic devices circuitry may be implemented by scaling the frequency multiple functional modules implemented in the synchronous electronic circuitry. The present disclosure discussed clock generators that may provide frequency scaling of clock signals for functional modules within an electronic device. Moreover, certain clock signal generators may reduce mitigate generation of large currents during frequency scaling by employing circuitry that leads to incremental frequency changes. Circuitry that allows substantially glitchless or reduced-glitch transition between clock rate frequencies are also discussed.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Michael D. Hutton, Audrey Kertesz
  • Patent number: 11171658
    Abstract: A semiconductor integrated circuit includes: a node to receive a reference clock signal; a voltage-controlled oscillation circuit to generate a clock signal based on a code corresponding to a frequency of the reference clock signal received by the node and on a control voltage; a calibration circuit to generate the code based on the frequency of the reference clock signal and on a frequency of the clock signal, and supply the generated code to the voltage-controlled oscillation circuit; and a phase locked loop circuit to generate the control voltage based on a phase difference of the clock signal with respect to the reference clock signal, and supply the generated control voltage to the voltage-controlled oscillation circuit. The voltage-controlled oscillation circuit is capable of changing the frequency of the clock signal based on the code supplied from the calibration circuit and on the control voltage supplied from the phase locked loop circuit.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: November 9, 2021
    Assignee: Kioxia Corporation
    Inventor: Yutaka Nakamura
  • Patent number: 11171654
    Abstract: A system includes delay locked loop (DLL) including a phase detector having a first input coupled to an input of the DLL, and a first delay circuit and a second delay circuit coupled in series between the input of the DLL and a second input of the phase detector. The DLL further includes a first control circuit, wherein an input of the first control circuit is coupled to an output of the phase detector, a first output of the first control circuit is coupled to a control input of the first delay circuit, and a second output of the first control circuit is coupled to a control input of the second delay circuit. The system also includes a second control circuit having an input coupled to the first control circuit, and a slave delay circuit having a control input coupled to an output of the second control circuit.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: November 9, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventor: Jeffrey Mark Hinrichs
  • Patent number: 11139825
    Abstract: A frequency ratio measurement device includes a counter section configured to count a time event of a first signal and output a count value obtained by multiplying the time event by k0, a time to digital converter section configured to output a time digital value corresponding to a phase difference between the first signal and a second signal, a combiner section configured to output a combined value of the count value and the time digital value, a subtractor section configured to output a difference value between a first value based on the combined value and a second value, a quantizer section configured to compare a third value based on the difference value with a predetermined threshold to thereby output a quantized value obtained by quantizing the third value, and a feedback section configured to output, based on a time event of the second signal, the second value based on the quantized value.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: October 5, 2021
    Inventor: Masayoshi Todorokihara
  • Patent number: 11075638
    Abstract: A calibration system of a digital phase locked loop (DPLL) includes a calibration circuit and a digitally controlled oscillator (DCO). The calibration circuit is configured to receive an input signal and a feedback signal, and generate a digital signal, based on a frequency of the input signal, a frequency of the feedback signal, and an input bias code. The DCO is configured to receive the input bias code and the digital signal, and generate a bias signal based on the input bias code. The DCO is further configured to generate an analog signal based on the bias signal and the digital signal, and generate the feedback signal such that the frequency of the feedback signal is based on an amplitude of the analog signal.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: July 27, 2021
    Assignee: NXP USA, INC.
    Inventors: Anand Kumar Sinha, Krishna Thakur, Pawan Sabharwal
  • Patent number: 11064564
    Abstract: An apparatus of a wireless communications device to transmit a sounding announcement frame (SAF) for use in a round-trip estimation to a receiving station, and associated method are provided. The apparatus is configured to encode an encoded field of the SAF that is one of a frame control field (FCF) or a sounding dialog token field (SDTF) of a null data packet announcement (NDPA) packet that forms the SAF to indicate to the receiving station that a communication different from a trigger frame may follow. The apparatus is also configured to configure the wireless device to transmit the NDPA packet to one or more stations.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Chittabrata Ghosh, Feng Jiang, Qinghua Li, Ganesh Venkatesan
  • Patent number: 11022820
    Abstract: Techniques and mechanisms for sensing an overlap of an ophthalmic device by an eyelid of a user while the ophthalmic device is disposed in or on an eye of the user. In an embodiment, a circuit, disposed in a sealed enclosure of the ophthalmic device, interacts via an electromagnetic field with a film of tear fluid that is formed on the ophthalmic device. Based on the electromagnetic interaction, an oscillation characteristic of the circuit is evaluated. The oscillation characteristic varies with a resistance that is due in part to an eyelid of the user overlapping at least some portion of the ophthalmic device. Based on the evaluated oscillation characteristic, an amount of the eyelid overlap is determined by circuitry of the ophthalmic device. In another embodiment, the amount of eyelid overlap is used to determine one or more characteristics of gazing by the user's eye.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: June 1, 2021
    Assignee: Verily Life Sciences LLC
    Inventors: Shungneng Lee, Uei-ming Jow, Nathan Pletcher
  • Patent number: 11025239
    Abstract: Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Andreas H. A. Arp, Fatih Cilek, Michael V. Koch, Matthias Ringe
  • Patent number: 11005421
    Abstract: A circuit device includes first and second output signal lines, an oscillation circuit that generates differential oscillation signals which are constituted by first and second signals, outputs the first signal to the first output signal line, and outputs the second signal to the second output signal line, a monitor circuit that includes a first input unit including a first input capacitor of which a one end is coupled to the first output signal line and an output unit which is coupled to the first input unit and outputs a monitor result, and a capacitance compensation circuit that includes a second input unit including a second input capacitor of which a one end is coupled to the second output signal line.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: May 11, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Tsutomu Ogihara
  • Patent number: 10972112
    Abstract: Embodiments described herein relate to a 50%-duty-cycle consecutive integer frequency divider and a phase-locked loop circuit having the frequency divider. The frequency divider includes a consecutive integer frequency divider module having a non-50%-duty-cycle, wherein the module receives a clock signal CLK and an input control signal CB and outputs a consecutive frequency division clock signal CLK1 comprising a non-50% duty cycle; a D flip-flop module for receiving the clock signal CLK and the consecutive frequency division clock signal CLK1 and outputting at least one clock signal CLKx; and a logic OR gate module for receiving the consecutive frequency division clock signal CLK1 and the at least one clock signal CLKx, and outputting an output clock signal CLKout comprising a 50% duty cycle.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: April 6, 2021
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Ning Zhang, Yuchun Liu
  • Patent number: 10943767
    Abstract: A system for measuring and controlling the phase of an incoming analog waveform is disclosed. The system comprises an analog to digital converter to convert the incoming analog waveform to a digital representation. The system also includes a clock delay generator, which allows a programmable amount of delay to be introduced into the sample clock for the ADC. The system further comprises a controller to manipulate the delay used by the clock delay generator and store the outputs from the ADC. The controller can then use the digitized representation to determine the frequency of the incoming analog waveform, its phase drift and its phase relative to a master clock. The controller can then modify the output of a RF generator in response to these determinations.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: March 9, 2021
    Assignee: Applied Materials, Inc.
    Inventor: Keith E. Kowal
  • Patent number: 10944408
    Abstract: Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to monitor clock signals associated with the first and second clocking sources and to generate at least one calibration code for adjusting at least one divider ratio of the first or second dividers according to the monitored clock signals.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventor: Amit Kumar Srivastava
  • Patent number: 10924094
    Abstract: A pulse width modulation control circuit and a control method of a pulse width modulation signal are provided. A counter circuit generates a count value according to a phase-locked loop clock, and resets the count value according to a transition point of a synchronization signal. A comparison circuit compares the count value with a duty ratio set value, and sets the pulse width modulation signal to a high level while the count value is less than the duty ratio set value.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: February 16, 2021
    Assignee: Power Forest Technology Corporation
    Inventor: Yueh-Chang Chen
  • Patent number: 10917048
    Abstract: An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: February 9, 2021
    Assignee: Blue Danube Systems, Inc.
    Inventors: Mihai Banu, Yiping Feng
  • Patent number: 10892911
    Abstract: A controller area network receiver includes a measurement circuit, a filter circuit, and a frame detection circuit. The measurement circuit is coupled to a bit stream input terminal, and includes a timer circuit and error calculation circuitry. The timer circuit is coupled to the bit stream input terminal and a reference clock generator circuit. The error calculation circuitry is coupled to the timer circuit. The filter circuit is coupled to the measurement circuit, and includes error clipping control circuitry and clock period adjustment circuitry. The error clipping control circuitry is coupled to the error calculation circuitry. The clock period adjustment circuitry is coupled to the error calculation circuitry and the timer circuit. The frame detection circuit is coupled to the filter circuit and the bit stream input terminal.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: January 12, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Roy David Wojciechowski
  • Patent number: 10868523
    Abstract: An apparatus is provided to improve lock time of a phase locked loop, wherein the apparatus comprises: a ring oscillator including at least two delay stages, wherein each delay stage has a controllable delay; and a multiphase frequency monitor coupled to the ring oscillator to monitor frequency at an output of at least two delay stages of the ring oscillator.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: William Li, Mohsen Nasroullahi, Khoa Nguyen
  • Patent number: 10855293
    Abstract: The present disclosure discloses a quick-start clock system, which includes: a digital subsidiary circuit configured to output a digital control value; a phase-locked loop including a programmable voltage-controlled oscillator circuit and a frequency dividing circuit connected to each other and both connected to the digital subsidiary circuit, the programmable voltage-controlled oscillator circuit obtains the digital control value output, and output a clock signal according to the digital control value, the frequency dividing circuit performs a frequency dividing operation on the clock signal; and a crystal oscillator circuit connected to the phase-locked loop, which includes a crystal and an oscillation injecting circuit connected to the crystal, the oscillation injecting circuit converts the clock signal performed with the frequency dividing operation to a co-frequency fully differential signal, and inject the co-frequency fully differential signal into the crystal.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: December 1, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Mengwen Zhang
  • Patent number: 10855380
    Abstract: Techniques and circuits are proposed to increase averaging in the clock recovery band based on an amount of channel overlap in receivers using excess bandwidth for clock recovery, to mitigate the impact of spectral energy leaking into an active channel of interest from an adjacent active channel and to improve the accuracy of the phase estimate of the received transmitted clock.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: December 1, 2020
    Assignee: Ciena Corporation
    Inventors: Sadok Aouini, Bilal Riaz, Naim Ben-Hamida, Lukas Jakober, Ahmad Abdo
  • Patent number: 10833686
    Abstract: The PLL circuit comprises a phase/frequency detector (302), a loop filter (304, 306), a VCO (308) and a feedback loop (320). The VCO can be electrically disconnected from the PLL and comprises a programmable trimming circuit (316) and a current-controlled oscillator (318). For calibration the VCO is electrically disconnected from the loop filter and from the feedback loop, a constant reference voltage is applied to the voltage input (IN), a center frequency programming code (L) is applied to the trimming circuit, the center frequency programming code is iteratively adjusted until a desired center frequency is obtained, a gain programming code (K) is applied to the trimming circuit while the adjusted code is still applied, and the gain programming code is iteratively adjusted until a desired gain is obtained. Then the VCO is connected to the PLL, which is then ready for normal operation.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: November 10, 2020
    Assignee: ams AG
    Inventors: Jia Sheng Chen, Gregor Schatzberger
  • Patent number: 10826508
    Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: November 3, 2020
    Assignee: Infineon Technologies AG
    Inventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
  • Patent number: 10826504
    Abstract: A time-to-digital converter and a phase difference detection method are disclosed. The time-to-digital converter includes a detection unit and a digital control circuit. The detection unit comprising: a phase detection circuit, a first and a second clock signal are respectively coupled to an identical input terminal of the phase detection circuit and a reference signal is coupled to another input terminal of the phase detection circuit; the phase detection circuit is configured to output a pulse width corresponding to a phase difference between the first or the second clock signal and the reference signal; a filter circuit, coupled to an output terminal of the phase detection circuit; a ring oscillator circuit, coupled to an output terminal of the filter circuit and configured to output an oscillation clock signal corresponding to the pulse width. The digital control circuit is configured to provide the reference signal and receive the oscillation clock signal.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: November 3, 2020
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Pengzhan Zhang, Yong Wang, Yanhong Li, Yaomin Wu, Zhongyuan Chang
  • Patent number: 10819356
    Abstract: A PLL frequency synthesizer includes a voltage controlled oscillator that outputs an oscillation signal having a frequency corresponding to a control voltage value, a phase comparison unit that outputs a phase difference signal representing a phase difference between a feedback oscillation signal and a reference oscillation signal, a charge pump that outputs a charge and discharge current according to the phase difference, a loop filter that outputs the control voltage value, which is increased or decreased according to a charge and discharge amount of a capacitive element, to the voltage controlled oscillator, a detection unit that detects a change rate of the control voltage value, and a control unit that adjusts the charge and discharge current, a characteristic of the loop filter, or a characteristic of the voltage controlled oscillator based on a detection result of the detection unit.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: October 27, 2020
    Assignee: THINE ELECTRONICS, INC.
    Inventor: Shunichi Kubo
  • Patent number: 10809669
    Abstract: Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by a delay. Gate circuitry generates a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired delay.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Gil Horovitz, Aryeh Farber, Nisim Machluf, Evgeny Shumaker, Igal Kushnir
  • Patent number: 10771010
    Abstract: A circuit device includes a processing circuit and an oscillation signal generation circuit. The processing circuit performs Kalman filter processing for a result of phase comparison between an input signal based on an oscillation signal and a reference signal and performs loop filter processing for the result of phase comparison. The oscillation signal generation circuit generates the oscillation signal of an oscillation frequency set by frequency control data which is output data of the loop filter processing by using the frequency control data and a resonator. The processing circuit estimates a truth value for an observed value of the result of phase comparison by using the Kalman filter processing.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: September 8, 2020
    Assignee: Seiko Epson Corporation
    Inventor: Yasuhiro Sudo
  • Patent number: 10768580
    Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: September 8, 2020
    Assignee: Intel IP Corporation
    Inventors: Yair Dgani, Michael Kerner, Elan Banin, Evgeny Shumaker, Gil Horovitz, Ofir Degani, Rotem Banin, Aryeh Farber, Rotem Avivi, Eshel Gordon, Tami Sela
  • Patent number: 10761136
    Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: September 1, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert G. Gerowitz, Sarah B. Higgins, Joseph A. Iadanza
  • Patent number: 10727749
    Abstract: A dual rail power supply system and a method for providing a first voltage and a second voltage to a load are presented. The power supply system draws a load current from the dual rail power supply system. The system has a first voltage rail for coupling to a first terminal of the load, a second voltage rail for coupling to a second terminal of the load, a first power converter to provide the first voltage at the first voltage rail, a second power converter to provide the second voltage at the second voltage rail, a third power converter comprising a first output coupled to the first voltage rail and a second output coupled to the second voltage rail. The third power converter generates a slave current and provides the slave current to the load such that the load current comprises the slave current, during a first mode.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: July 28, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Cheng-Teng Chen, Ruei-Hong Peng, Yuan Wen Hsiao, Alan Somerville
  • Patent number: 10715154
    Abstract: A digitally controlled oscillator, including: a frequency divider chain, configured to perform frequency division on an input clock signal to produce K basic clock signals, wherein frequencies and periods of the K basic dock signals are the same and a time difference between two adjacent basic clock signals is a basic time unit; and a frequency synthesizer, configured to receive the K basic clock signals from the frequency divider chain, determine a first period and a second period according to the basic time unit and a frequency control word, and generate a synthetic clock signal based on the K basic clock signals, wherein the synthetic clock signal uses the first period and the second period in an alternate manner.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 14, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Liming Xiu
  • Patent number: 10659096
    Abstract: A method of performing a frequency scan at a radio includes placing the radio in an active mode and, while maintaining the radio in the active mode, for each of a plurality of target frequencies determining a coarse frequency tuning value based on the target frequency. The radio places a phase locked loop (PLL) in an open-loop configuration and while the PLL is in the open-loop configuration, programs the VCO with the coarse frequency tuning value. The radio programs the divider with a feedback adjustment based on the target frequency, places the PLL in a closed-loop configuration, and in response to the PLL reaching a settled state, performs an operation based on an output signal of the PLL.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: May 19, 2020
    Assignee: NXP USA, Inc.
    Inventors: Khurram Waheed, Carlos Alberto Neri Castellanos
  • Patent number: 10659024
    Abstract: Methods and apparatuses for communicating information are described. In some embodiments, a first integrated circuit (IC) provides a clock signal and a data signal to a second IC, wherein the data bits of the data signal are timed according to the clock signal, and wherein the frequency of the clock signal is capable of being changed even when the data signal is valid.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: May 19, 2020
    Assignee: Rambus Inc.
    Inventors: Brian Hing-Kit Tsang, Jared L. Zerbe
  • Patent number: 10644868
    Abstract: A circuit includes a phase and frequency detector circuit to generate a first phase detect signal indicative of whether a polarity of a first clock is the same as a polarity of a second clock upon occurrence of an edge of a data signal. The second clock being 90 degrees out of phase with respect to the first clock. A lock detect circuit determines, based on the first phase detect signal, that a third clock is one of frequency and phase locked to the data signal, frequency and quadrature locked to the data signal, and not frequency locked to the data signal.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: May 5, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abishek Manian, Michael Gerald Vrazel
  • Patent number: 10637484
    Abstract: A circuit device includes an oscillation signal generation circuit that generates an oscillation signal by using a resonator and a processing circuit that estimates an aging characteristic of the oscillation frequency of the resonator based on the result of comparison between the phase of a reference signal based on a satellite signal transmitted from a navigation satellite and the phase of a clock signal based on the oscillation signal. The processing circuit estimates the aging characteristic based on an index value representing the reliability of the state of the received satellite signal and the result of the phase comparison.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: April 28, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Yasuhiro Sudo