With Choice Between Multiple Delayed Clocks Patents (Class 327/152)
-
Patent number: 11456749Abstract: A timing margin detecting circuit is provided. The timing margin detecting circuit comprises a delay element, receiving a first data signal and a first clock signal, configured to generate a second data signal and a second clock signal, wherein the second clock signal has a delay relative to the second data signal; a controller, configured to generate the control signal to control the delay of the second clock signal relative to the second data signal; a sampler, coupled to the delay element, configured to generate a sampled data signal according to the second data signal and the second clock signal; and a bit error rate determination circuit, coupled to the sampler, configured to determine whether the sampled data signal is the same as a predefined test pattern and generate a determination result accordingly; wherein the controller determines a timing margin according to the determination result.Type: GrantFiled: July 2, 2020Date of Patent: September 27, 2022Assignee: NOVATEK Microelectronics Corp.Inventors: Hao-Wei Hung, Wei-Sheng Tseng
-
Patent number: 11385282Abstract: A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.Type: GrantFiled: November 15, 2018Date of Patent: July 12, 2022Assignee: PROTEANTECS LTD.Inventors: Evelyn Landman, Shai Cohen, Yahel David, Eyal Fayneh, Inbar Weintrob
-
Patent number: 11275401Abstract: Various implementations described herein are directed to a device having alarm circuitry that receives a clock signal and provides alarm chain signals based on the clock signal. The device may include delay chain circuitry that receives the alarm chain signals from the alarm circuitry and provides delay chain signals. The device may include output circuitry that receives the delay chain signals from the delay chain circuitry and provides an alarm control signal based on the delay chain signals.Type: GrantFiled: January 15, 2020Date of Patent: March 15, 2022Assignee: Arm LimitedInventor: Ivan Michael Lowe
-
Patent number: 11228318Abstract: Exemplary aspects of the present disclosure involve a system and related method of PLL circuitry in a chirp signaling FMCW system having a variable PLL bandwidth (BW). To adjust the BW, the PLL circuitry may provide for variable capacitance in the circuitry. This capacitance change may allow for a bandwidth for one slope, as used for the acquisition period. The capacitance may then be adjusted to allow for a different bandwidth for another slope which is used to reset the circuitry in preparation for another frequency sweep. Adjusting the PLL BW, via variable capacitance, may be used to mitigate phase noise which can adversely the PLL.Type: GrantFiled: October 29, 2020Date of Patent: January 18, 2022Assignee: NXP B.V.Inventors: Tarik Saric, Piotr Gibas, Zhirui Zong
-
Patent number: 11146275Abstract: A signal generation circuit includes a synchronization circuit, a pulse width control circuit, and an output circuit. The synchronization circuit synchronizes an input signal with a clock signal to generate a synchronization signal. The pulse width control circuit generates a start signal from the synchronization signal and generate an end signal by delaying the synchronization signal by a time corresponding to an off control signal in synchronization with the clock signal. The output circuit generates an output signal based on the start signal and the end signal.Type: GrantFiled: April 27, 2020Date of Patent: October 12, 2021Assignee: SK hynix Inc.Inventors: Gyu Tae Park, Jin Il Chung
-
Patent number: 10990555Abstract: Embodiments herein describe an interface between PL fabric and a hardened block that includes a programmable pipeline. This pipeline includes at least a sequential element and a bypass path. For time critical nets in a netlist, the programmable IC routes a net through the sequential element. Doing so mitigates or eliminates the uncertainty associated with routing the net from the hardened block through PL fabric. Also, the sequential element can increase the available time for capturing the data. For less time critical nets, the net can route through the bypass path. This means the route from the hardened block to the PL fabric is determined on the fly by a routing algorithm rather than being fixed.Type: GrantFiled: January 6, 2020Date of Patent: April 27, 2021Assignee: XILINX, INC.Inventors: Aashish Tripathi, Sundeep Ram Gopal Agarwal
-
Patent number: 10965442Abstract: A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into a delayed clock signal by a delay that is responsive to a difference between the phase-difference code and a unit interval for the clock signal. The delayed clock signal clocks a flip-flop to register the received data signal.Type: GrantFiled: October 2, 2018Date of Patent: March 30, 2021Assignee: QUALCOMM INCORPORATEDInventors: Eskinder Hailu, Bupesh Pandita, Jon Boyette, Hadi Goudarzi, Yong Suk Jun, Zhi Zhu, Minhan Chen
-
Patent number: 10944387Abstract: A delay line includes a delay chain, a pulse generator generating a pulse based on a received input signal, and a delay chain control circuit. The delay chain control circuit has a first input receiving the pulse, a second input receiving output from a last element of the delay chain, and a selection input receiving a delayed version of the received input signal. The delay chain control circuit has an output coupled to provide input to a first element of the delay chain in response to the delayed version of the received input signal. An output selection circuit receives outputs from each element of the delay chain, counts assertions of the output of the last element of the delay chain and, in response to the count being equal to a desired count, passes a desired one of the outputs of the elements of the delay chain as output.Type: GrantFiled: June 9, 2020Date of Patent: March 9, 2021Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Jeet Narayan Tiwari
-
Patent number: 10581416Abstract: Aspects of the present disclosure provide for a method. In some examples, the method includes receiving a synchronization signal, dividing the synchronization signal to form a first divided signal and a second divided signal, generating a first ramp signal and a second ramp signal, setting a latch output to a logical high value when the first divided signal has a logical high value or a value of the first ramp signal exceeds a value of a reference signal, setting the latch output to a logical low value when the second divided signal has a logical high value or a value of the second ramp signal exceeds the value of the reference signal, generating a synchronization clock according to the latch output and an inverse of the latch output, and outputting the latch output or the synchronization clock as a clock signal based on a value of a synchronization active signal.Type: GrantFiled: March 21, 2019Date of Patent: March 3, 2020Assignee: Texas Instruments IncorporatedInventors: Junhong Zhang, Angelo Pereira, Pinar Korkmaz, Sujan Manohar, Michael Munroe
-
Patent number: 10439615Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.Type: GrantFiled: January 14, 2019Date of Patent: October 8, 2019Assignee: Altera CorporationInventors: Dinesh Patil, Kok Hong Chan, Wai Tat Wong, Chuan Thim Khor
-
Patent number: 10218360Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.Type: GrantFiled: August 2, 2016Date of Patent: February 26, 2019Assignee: Altera CorporationInventors: Dinesh Patil, Kok Hong Chan, Wai Tat Wong, Chuan Thim Khor
-
Patent number: 10134463Abstract: Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.Type: GrantFiled: October 9, 2017Date of Patent: November 20, 2018Assignee: Intel CorporationInventors: Mozhgan Mansuri, Aaron Martin, James A. McCall
-
Patent number: 9935542Abstract: A method for implementing a Semiconductor Integrated Circuit device using Near/Sub-threshold technology with SOFTWARE programmable Adaptive Dynamic Voltage Control (ADVC) algorithm using different sensors inside the chip in order to improve the target speed and reduce the energy per operation of the final product. This method achieves the best power per performance for a given solution operating at a required speed.Type: GrantFiled: March 4, 2016Date of Patent: April 3, 2018Assignee: PLSense Ltd.Inventors: Uzi Zangi, Neil Feldman
-
Patent number: 9853635Abstract: A double frequency-shift keying modulating device includes a modulation module. The modulation module receives an oscillating signal and a digital signal, and generates a modulation output signal that has a first frequency. The first frequency is associated with a frequency of the oscillating signal and varies periodically at a second frequency. The second frequency is associated with the digital signal and the frequency of the oscillating signal.Type: GrantFiled: August 21, 2016Date of Patent: December 26, 2017Assignee: NATIONAL CHI NAN UNIVERSITYInventors: Yo-Sheng Lin, Chien-Chu Chi, Ching-Hung Peng
-
Patent number: 9800234Abstract: A clock and data recovery circuit and a phase interpolator therefor are provided. The clock and data recovery circuit includes a phase-locked loop, a control unit and the phase interpolator, a receiving circuit, a serial-to-parallel conversion circuit. The phase interpolator is connected with the control unit of the clock and data recovery circuit, and the phase interpolator includes: an encoding circuit, two multiplexers, a clock mixer, and two differential to single-ended amplifiers. The control unit is configured to further control the encoding circuit to change a delay position for a clock outputted by the phase interpolator in a case that the data sampled in the current clock position is not the optimal sampled data, to lead or lag the clock, thereby forming a stable state in which the clock follows the data dynamically.Type: GrantFiled: July 27, 2016Date of Patent: October 24, 2017Assignee: LONTIUM SEMICONDUCTOR CORPORATIONInventors: Lianliang Tai, Hongfeng Xia, Xi Xu, Diansheng Ren, Cheng Tao, Feng Chen
-
Patent number: 9768809Abstract: This application discusses, among other things, apparatus and methods for improving spurious frequency performance of digital-to-time converters (DTCs). In an example, a method can include receiving a code at selection logic of a digital-to-time converter at a first instant, selecting a first delay path of the DTC to provide a delay associated with the code, associating a second delay path with the code, receiving the code at the selection logic at a second instant, and selecting the second delay path of the DTC to provide the delay associated with the code.Type: GrantFiled: June 30, 2014Date of Patent: September 19, 2017Assignee: Intel IP CorporationInventors: Stefan Tertinek, Peter Preyler, Thomas Mayer
-
Patent number: 9722537Abstract: A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit.Type: GrantFiled: August 20, 2015Date of Patent: August 1, 2017Assignee: Short Circuit Technologies LLCInventors: Gerasimos S. Vlachogiannakis, Augusto Ronchini Ximenes, Robert Bogdan Staszewski
-
Patent number: 9672008Abstract: A system, method, and computer program product are provided for a pausible bisynchronous FIFO. Data is written synchronously with a first clock signal of a first clock domain to an entry of a dual-port memory array and an increment signal is generated in the first clock domain. The increment signal is determined to transition near an edge of a second dock signal, where the second clock signal is a pausible clock signal. A next edge of the second clock signal of the second clock domain is delayed and the increment signal to the second clock domain and is transmitted.Type: GrantFiled: November 20, 2015Date of Patent: June 6, 2017Assignee: NVIDIA CorporationInventors: Benjamin Andrew Keller, Matthew Rudolph Fojtik, Brucek Kurdo Khailany
-
Patent number: 9600018Abstract: Methods and circuits for performing a clock-stop process of a circuit are disclosed. For example, a circuit includes a clock group having a first clock domain, a first clock multiplexer, a first synchronizer and a controller. The controller is configured to initiate a clock stop process of the circuit by sending an alternative mode signal to the first synchronizer. The first synchronizer is configured to synchronize the alternative mode signal to a clock of the first clock domain and is further configured to output, to a select line of the first clock multiplexer, the alternative mode signal that is synchronized to the clock of the first clock domain. The select line of the first clock multiplexer is for selecting from between an input of the first clock multiplexer for the clock of the first clock domain and an alternative clock input of the first clock multiplexer for an alternative clock signal from the controller.Type: GrantFiled: June 9, 2014Date of Patent: March 21, 2017Assignee: XILINX, INC.Inventors: Amitava Majumdar, Balakrishna Jayadev, Ismed D. Hartanto
-
Patent number: 9577625Abstract: A semiconductor device including a common delay circuit configured to delay an input signal in response to a delay control code to output a first delayed input signal and a second delayed input signal; a first delay circuit configured to delay the first delayed input signal in response to the delay control code and to output a first output signal; and a second delay circuit configured to delay the second delayed input signal in response to the delay control code and to output a second output signal.Type: GrantFiled: March 10, 2015Date of Patent: February 21, 2017Assignee: SK Hynix Inc.Inventors: Yong-Hoon Kim, Hyun-Woo Lee
-
Patent number: 9484955Abstract: A semiconductor memory apparatus may include a cyclic redundancy check (CRC) circuit block electrically coupled with a first pad, and configured to generate internal CRC information from data received from the first pad. The semiconductor memory apparatus may also include a comparison unit configured to compare external CRC information received from outside the semiconductor memory apparatus with the internal CRC information, and generate a read training result signal.Type: GrantFiled: September 17, 2014Date of Patent: November 1, 2016Assignee: SK HYNIX INC.Inventor: Ha Jun Jeong
-
Patent number: 9363069Abstract: A clock generating device is disclosed. The clock generating device includes a clock generating unit, for counting a synchronization period of a synchronization signal, generating a first interrupt signal according to the synchronization signal, generating a pulse-width modulation signal according a control signal, counting a phase difference between the synchronization signal and the pulse-width modulation signal, and generating a second interrupt signal according to the pulse-width modulation signal; and a computing unit, for acquiring the synchronization period according to the first interrupt signal, acquiring the phase difference according to the second interrupt signal, and adjusting the control signal according to the synchronization period, a modulation period of the pulse-width modulation signal and the phase difference.Type: GrantFiled: April 28, 2015Date of Patent: June 7, 2016Assignee: NOVATEK Microelectronics Corp.Inventors: Chieh-Hao Wang, Wei-Jen Lo, Sen-Lin Kuo, Pao-Chen Shih
-
Patent number: 9276464Abstract: A voltage generation circuit is provided, which includes a pumping unit generating a high voltage and a voltage regulation unit controlling the pumping unit to generate a target voltage in a first mode and controlling the pumping unit to generate a reserve voltage and generating the target voltage through down conversion of the reserve voltage in a second mode.Type: GrantFiled: March 18, 2013Date of Patent: March 1, 2016Assignee: SK HYNIX INC.Inventor: Gyo-Soo Chu
-
Patent number: 9246497Abstract: Circuits and techniques for operating an integrated circuit (IC) are disclosed. A disclosed circuit includes a divider circuit that is operable to receive a first signal at a first speed and output a second signal at a second speed based on the first signal. A recovery circuit is coupled to the divider circuit. The recovery circuit is operable to determine the frequency of the second signal and is further operable to generate a first ready signal and a recovered clock signal based on the second signal. A phase aligner circuit, operable to align a phase of the second signal with a phase of the recovered clocks signal based on the first ready signal, is coupled to the recovery circuit.Type: GrantFiled: May 23, 2014Date of Patent: January 26, 2016Assignee: Altera CorporationInventor: Han Hua Leong
-
Patent number: 9235537Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.Type: GrantFiled: October 19, 2012Date of Patent: January 12, 2016Assignee: Rambus Inc.Inventors: Jun Kim, Pak Shing Chau, Wayne S. Richardson
-
Patent number: 9112516Abstract: According to one embodiment, a semiconductor device is provided with first to third circuits. The first circuit generates first information that indicates a corresponding relationship between a period of a reference clock and a delay amount per delay element. The second circuit generates second information that indicates the number of stages of delay elements corresponding to a set phase difference based on the first information. The third circuit generates a delayed clock by delaying the reference clock just a delay amount of stages of the delay elements indicating the second information.Type: GrantFiled: September 10, 2013Date of Patent: August 18, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Natsuki Kushiyama
-
Patent number: 9112646Abstract: One embodiment relates to an interpolator-based clock and data recovery (iCDR) circuit. The iCDR circuit includes an automatic gain control circuit arranged to generate an interpolation jump size signal when a targeted sampling detection signal is asserted. The targeted sampling detection signal may be asserted when sampling by the phase detector of the iCDR circuit is within a targeted range. The interpolation jump size signal may indicate a number of phase steps to shift an interpolation state signal if a jump is indicated by a filtered feedback signal. Other embodiments and features are also disclosed.Type: GrantFiled: February 11, 2014Date of Patent: August 18, 2015Assignee: Altera CorporationInventors: Chuan Thim Khor, Chuan Khye Chai
-
Patent number: 9018990Abstract: A duty cycle tuning circuit and a method thereof are provided, in which the duty cycle tuning circuit includes multiple interpolation circuits, an edge detection circuit, and a delay chain. Each interpolation circuit receives multiple phase clocks, and interpolates an interpolation clock from two of the phase clocks. The phase clocks have the same frequency but different phases. The edge detection circuit is connected electrically to the delay chain, and generates an output clock according to an edge of the interpolation clock.Type: GrantFiled: March 14, 2013Date of Patent: April 28, 2015Assignee: Realtek Semiconductor Corp.Inventor: Ye Liu
-
Patent number: 8994419Abstract: A semiconductor device may include first to fourth output lines, an input signal latch unit suitable for latching first to fourth input signals that are sequentially inputted in response to first to fourth clocks having sequential phases, respectively, a valid signal latch unit suitable for latching a valid signal in response to one clock among the first to fourth clocks, where the valid signal corresponds to one input signal among the first to fourth input signals and represents whether the corresponding input signal is valid or not, and a signal transfer unit suitable for transferring the latched input signals, which are obtained by latching the input signals in response to the first to fourth clocks, to the first to fourth output lines based on a correspondence relationship that is decided based on a valid signal latch result of the valid signal latch unit.Type: GrantFiled: December 17, 2013Date of Patent: March 31, 2015Assignee: SK Hynix Inc.Inventor: Young-Jun Ku
-
Patent number: 8983012Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.Type: GrantFiled: January 25, 2012Date of Patent: March 17, 2015Assignee: Texas Instruments IncorporatedInventors: Denis Roland Beaudoin, Ritesh Dhirajlal Sojitra, Gregory Lee Christison
-
Patent number: 8976054Abstract: A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to generate two output signals includes: a phase comparator configured to compare phases of the two input signals with each other to generate the digital value; a phase selector configured to output one of the two input signals which has a leading phase as a first signal, and the other of the two input signals which has a lagging phase as a second signal; and a delay unit configured to output the first signal with a delay, wherein the time-to-digital conversion circuit outputs the signal output from the delay unit and the second signal as the two output signals.Type: GrantFiled: July 15, 2013Date of Patent: March 10, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Shiro Dosho, Masao Takayama, Takuji Miki
-
Publication number: 20150048870Abstract: A semiconductor device may include first to fourth output lines, an input signal latch unit suitable for latching first to fourth input signals that are sequentially inputted in response to first to fourth clocks having sequential phases, respectively, a valid signal latch unit suitable for latching a valid signal in response to one clock among the first to fourth clocks, where the valid signal corresponds to one input signal among the first to fourth input signals and represents whether the corresponding input signal is valid or not, and a signal transfer unit suitable for transferring the latched input signals, which are obtained by latching the input signals in response to the first to fourth clocks, to the first to fourth output lines based on a correspondence relationship that is decided based on a valid signal latch result of the valid signal latch unit.Type: ApplicationFiled: December 17, 2013Publication date: February 19, 2015Applicant: SK hynix Inc.Inventor: Young-Jun KU
-
Patent number: 8957714Abstract: A master measure circuit is disclosed that may select from various nodes on a delay path carrying a signal. The master measure circuit measures the delay for propagation of the signal from one selected node to another selected node and controls an adjustable delay circuit in the delay path accordingly.Type: GrantFiled: March 14, 2013Date of Patent: February 17, 2015Assignee: QUALCOMM IncorporatedInventors: Vaishnav Srinivas, Jan Christian Diffenderfer, Philip Michael Clovis, David Ian West
-
Patent number: 8957713Abstract: Methods and devices provide for determining whether to operate a radio frequency synthesizer in a first mode of operation or a second mode of operation based on a reference frequency signal. The radio frequency synthesizer includes a digitally-controlled oscillator configured to generate an oscillator signal having an output frequency. A digital frequency locked-loop is configured to control the output frequency of the oscillator signal in a first mode of operation based on a first control signal. A digital phase locked-loop is configured to control the output frequency of the oscillator signal in a second mode of operation based on a second control signal. A controller determines whether to operate in the first mode or second mode based on a reference frequency signal. The controller generates the first or second control signal based on the determination of operating in the first or second mode, respectively.Type: GrantFiled: April 3, 2014Date of Patent: February 17, 2015Assignee: Marvell World Trade Ltd.Inventors: Olivier Burg, Cao-Thong Tu
-
Patent number: 8917123Abstract: An integrated circuit includes an N number of functional logic blocks, with N being greater than or equal to two, and clock staggering test circuitry. When the clock staggering test circuitry is in a shift mode, N staggered shift clock signals are generated for respective ones of the N functional logic blocks. Each of the N staggered shift clock signals has a frequency equal to a frequency of an external test clock signal divided by M, where M is greater than or equal to N. The peak power of the integrated circuit is reduced during the shift mode as a result of the staggered shift clock signals.Type: GrantFiled: March 29, 2013Date of Patent: December 23, 2014Assignee: STMicroelectronics International N.V.Inventors: Swapnil Bahl, Shray Khullar
-
Patent number: 8816729Abstract: Methods and systems for synchronizing an electric grid having unbalanced voltages are provided. A voltage vector may be filtered in a quadrature tracking filter (QTF) to generate a quadrature signal. The inputs to the QTF may be either single input, multiple outputs, or alternatively, multiple inputs, multiple outputs. Furthermore, the second state of either of the two QTF transformations may be either positive or negative. A phase-locked-loop (PLL) operation may be performed on the quadrature signal to monitor a voltage vector between the grid and a connected power converter. The QTF and PLL methods are suitable for either single-phase applications or n-phase (any number of phases) applications.Type: GrantFiled: May 10, 2012Date of Patent: August 26, 2014Assignee: Rockwell Automation Technologies, Inc.Inventors: Russel J. Kerkman, Ahmed Mohamed Sayed Ahmed, Brian J. Seibel, Carlos Rodriguez Valdez
-
Publication number: 20140210526Abstract: A rotational synchronizer for metastability resolution is disclosed. A synchronizer includes a plurality of M+1 latches each coupled to receive data through a common data input. The synchronizer further includes a multiplexer having a N inputs each coupled to receive data from an output of a corresponding one of the M+1 latches, and an output, wherein the multiplexer is configured to select one of its inputs to be coupled to the output. A control circuit is configured to cause the multiplexer to sequentially select outputs of the M+1 latches responsive to N successive clock pulses, and further configured to cause the M+1 latches to sequentially latch data received through the common data input.Type: ApplicationFiled: January 31, 2013Publication date: July 31, 2014Applicant: Oracle International CorporationInventors: Robert P. Masleid, Ali Vahidsafa
-
Patent number: 8766680Abstract: A voltage translation circuit (116) provides an output analog voltage signal that has a translated voltage of the voltage of an input analog voltage signal over a range of values of the input analog voltage signal. The voltage translation circuit includes an input stage (202) having a circuit node and an input transistor (210) coupled between the circuit node and a power supply terminal, wherein a gate of the input transistor is coupled to receive the input analog voltage signal; a current path circuit (204) in parallel with the input transistor, wherein the current path includes a first transistor coupled between the circuit node and the power supply terminal; and a circuit coupled to provide a variable body bias voltage to a body of the first transistor.Type: GrantFiled: September 26, 2012Date of Patent: July 1, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Xinghai Tang, Gayathri A. Bhagavatheeswaran, Hector Sanchez
-
Patent number: 8742807Abstract: An apparatus comprising a first phase circuit, a second phase circuit, and a current steering circuit. The first phase circuit may be configured to generate a first portion of a phase interpolated clock signal in response to (i) a control signal, (ii) a first bias signal, and (iii) a feedback of said phase interpolated clock signal. The second phase circuit may be configured to generate a second portion of the phase interpolated clock signal in response to (i) the control signal, (ii) a second bias signal, and (iii) the feedback of the phase interpolated clock signal. The current steering circuit may be configured to generate the first bias signal and the second bias signal in response to a reference bias signal.Type: GrantFiled: May 24, 2012Date of Patent: June 3, 2014Assignee: Ambarella, Inc.Inventor: Harish S. Muthali
-
Publication number: 20140139275Abstract: A method and a system are provided for variation-tolerant synchronization. A phase value representing a phase of a second clock signal relative to a first clock signal and a period value representing a relative period between the second clock signal and the first clock signal are received. An extrapolated phase value of the second clock signal relative to the first clock signal corresponding to a next transition of the first clock signal is computed based on the phase value and the period value.Type: ApplicationFiled: November 20, 2012Publication date: May 22, 2014Applicant: NVIDIA CORPORATIONInventors: William J. Dally, Stephen G. Tell
-
Patent number: 8724677Abstract: Provided are a method and apparatus (receiver) of receiving and processing a radio signal in a transmitter-receiver environment. The radio signals are transmitted across a wireless interface using Ultra Wideband (UWB) pulses. A transmitted reference approach is utilized. The radio signal include pairs of UWB pulses with each pair of pulses separated by a fixed time delay. The two pulses are then combined to provide for improved noise immunity.Type: GrantFiled: October 17, 2013Date of Patent: May 13, 2014Assignee: University of South FloridaInventor: James L. Tucker
-
Patent number: 8704562Abstract: An apparatus and method for providing an output signal. The apparatus comprises an input for receiving a reference signal, an oscillator for providing an output signal, and an offset signal generator for frequency multiplying the reference signal to generate an offset signal that has a plurality of frequency products in a plurality of frequency bands. The apparatus further includes a mixer for mixing the offset signal with the output signal to produce a combined signal, an offset frequency selector for controllably selecting a frequency band of the offset signal, and a difference detector for detecting a difference between the reference signal and the combined signal and for providing a control signal to the oscillator based on the detected difference.Type: GrantFiled: July 16, 2012Date of Patent: April 22, 2014Assignee: Nanowave Technologies Inc.Inventors: Charles William Tremlett Nicholls, Walid Hamdane
-
Patent number: 8704560Abstract: A multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, a clock generator generates quadrature signals including those having 90, 180, 270 and 360 degrees phase difference with a first signal. The rising edge of an intermediate signal is compared with the rising edges of two of the other signals to generate an UP and DN pulse signal, respectively. The UP and DN signals are used to adjust the delay of a delay line producing the signals to synchronize the signals. In some embodiments, a reset signal generator is used to truncate the UP or DN signal pulse.Type: GrantFiled: March 16, 2011Date of Patent: April 22, 2014Assignee: Micron Technology, Inc.Inventor: Yantao Ma
-
Patent number: 8704565Abstract: According to one embodiment, a lock detection circuit includes an initial state response circuit. The initial state response circuit is configured to output a third control signal to delay lines and cause a charge pump to stop an output of a second control signal when a pulse width modulation signal is not input, the third control signal is configured to control a delay amount to cause a delay amount of an entire delay circuit to be within one selected from a range in which an OVER signal generation circuit is operable, a range in which an UNDER signal generation circuit is operable, and a range that is greater than an UNDER threshold and less than an OVER threshold.Type: GrantFiled: August 31, 2012Date of Patent: April 22, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Toyoaki Uo
-
Patent number: 8638137Abstract: A semiconductor device includes a delay unit configured to delay an inputted clock to generate a delay clock, a selection unit configured to select and output one of the inputted clock and the delay clock, a delay locked loop configured to perform a delay locking operation using a signal delivered from the selection unit, and a selection control unit configured to control the selection unit in response to a comparison of one period of the inputted clock and a maximum delay value of the delay locked loop.Type: GrantFiled: April 17, 2012Date of Patent: January 28, 2014Assignee: Hynix Semiconductor Inc.Inventor: Jin Il Chung
-
Patent number: 8588270Abstract: The invention includes a method for transmitting and detecting high speed Ultra Wideband pulses across a wireless interface. The transmitter includes a serializer and pulse generator. The receiver comprises a fixed delay line, multiplier, local serializer (with a sequence matching the transmitter), digital delay lines, low noise amplifier and logic fan-out buffer along with an array of D flip-flop pairs. Each flip-flop pair is enabled, at fixed time increments, to detect signals at a precise time; the timing is controlled by the pseudo-random sequence generated by the local serializer. A local tunable oscillator is controlled by detecting the phase change of the incoming signal and applying compensation to maintain the phase alignment and clock synchronization of the receiver to the clock reference of the transmitter. The invention uses a pair of pulses with a fixed delay and then relies on mixing the two to provide better noise immunity.Type: GrantFiled: December 4, 2012Date of Patent: November 19, 2013Assignee: University of South FloridaInventor: James L. Tucker
-
Patent number: 8559581Abstract: Disclosed herein is a CDR circuit including delay elements, including: a divider having a delay element and configured to extract a clock by using, as a trigger, a data input with a signal transition regularly inserted; and a latch configured to latch an input data signal in synchronization with the clock extracted by the divider.Type: GrantFiled: June 7, 2011Date of Patent: October 15, 2013Assignee: Sony CorporationInventors: Tomokazu Tanaka, Hidekazu Kikuchi
-
Patent number: 8514995Abstract: A circuit includes a receiver circuit, a data valid monitor circuit, a clock signal generation circuit, and a phase shift circuit. The receiver circuit is operable to generate a first periodic signal, a sampled data signal based on an input data signal, and a data valid signal based on a predefined number of bits in the sampled data signal. The data valid monitor circuit is operable to generate a count value by counting periods of the first periodic signal. The data valid monitor circuit is operable to generate a phase error signal based on the data valid signal and the count value. The clock signal generation circuit is operable to generate a second periodic signal. The phase shift circuit is operable to generate a third periodic signal based on the second periodic signal and to adjust a phase of the third periodic signal based on the phase error signal.Type: GrantFiled: April 7, 2011Date of Patent: August 20, 2013Assignee: Altera CorporationInventors: Boon Hong Oh, Peter Schepers, Da Hai Tang
-
Patent number: 8514005Abstract: A circuit for generating multiphase clock signals and corresponding indication signals is provided. The circuit includes a multiphase clock generation circuit, a DLL circuit, a timing circuit, and a phase comparison circuit. The multiphase clock generation circuit receives an external clock to provide a plurality of first clock signals, phases of which differ from one another. The DLL circuit receives the external clock signal to provide a second clock signal. The timing circuit receives the second clock signal and a comparison signal to provide a plurality of indication signals. Each of the plurality of indication signals has rising edges which lead the rising edges of a corresponding one of the first clock signals. The phase comparison provides the comparison signal if a delayed phase of the corresponding one of the indication signals is within a phase of one of the first clock signals.Type: GrantFiled: April 20, 2012Date of Patent: August 20, 2013Assignee: Elite Semiconductor Memory Technology, Inc.Inventors: Ming-Chien Huang, Chien-Yi Chang
-
Patent number: 8415996Abstract: Methods, circuits, and apparatus for correcting the phase of a clock signal are presented. In one method, an operation is included for receiving, from a plurality of input lines, a plurality of input clock signals with respective input clock phases. The input clock phases form an ordered sequence of clock phases. The method further includes an operation for transmitting, over a plurality of output lines, a plurality of output clock signals with respective output clock phases. The input and output lines are coupled to a serially coupled ring of resistors, where each resistor in the ring has a terminal coupled to an input line and the other terminal coupled to an output line. Further, each output clock phase has a value that is between successive input clock phases of the ordered sequence of clock phases.Type: GrantFiled: June 24, 2011Date of Patent: April 9, 2013Assignee: Altera CorporationInventor: Wai Tat Wong