Abstract: A novel and useful system and method of generating quantum unitary noise using silicon based quantum dot arrays. Unitary noise is derived from a probability of detecting a particle within a quantum dot array structure comprising position based charge qubits with two time independent basis states |0> and |1>. A two level electron tunneling device such as an interface device, qubit or other quantum structure is used to generate quantum noise. The electron tunneling device includes a reservoir of particles, a quantum dot, and a barrier that is used to control tunneling between the reservoir and the quantum dot. A detector circuit connected to the device outputs a digital stream corresponding to the probability of a particle of being detected. Controlling the bias applied to the barrier controls the probability of detection. Thus, the probability density function (PDF) of the output unitary noise can be controlled to correspond to a desired probability.

Abstract: A random number generating device includes a particle detector, a pulse generator, a clock counter, and a random number converter. The particle detector detects particles emitted from a radioactive isotope. The pulse generator generates pulses corresponding to the particles. The clock counter counts the number of clock cycles during time intervals between the pulses and generates a plurality of count values. The random number converter adjusts a clock frequency, based on a minimum value and a maximum value of the plurality of count values and converts a target count value generated depending on the adjusted clock frequency into a random number.

Abstract: Random number generator (GL) comprising adjustable speed ring oscillators (GPRS, GPRS?), which have outputs (o-GPRS, o-GPRS?) connected to inputs (i1-UM, i2-UM) of a metastability circuit (UM) and inputs (i1-DF, i2-DF) of a phase detector (DF), which outputs (o-UM, o-DF) are connected to inputs (r-US?, i-US?) of a control circuit (US?), having output (o-US?) connected to control inputs (s-GPRS, s-GPRS?) of the adjustable speed ring oscillators (GPRS, GPRS?). The outputs (o-UM, o-DF) of the metastability circuit (UM) and the phase detector (DF) are being outputs (o-GL, o2-GL) of the random number generator (GL).

Abstract: A switch interface adapter allowing a simple open/close switch to be adapted to a digital and analog diagnostic switch interface includes: at least one coil having a first terminal and a second terminal, wherein the switch is electrically connected to the first terminal or the second terminal, and the at least one coil is activated or deactivated via the switch; a first contact switch comprising a digital line, wherein the at least one coil controls opening and closing of the first contact switch to break and complete the digital line respectively, the digital line is electrically connected to the ECU, and a digital signal is generated from the digital line as a digital input for the ECU; a second contact switch comprising an analog line, wherein the at least one coil controls opening and closing of the second contact switch to break and complete the analog line respectively, the analog line is electrically connected to the ECU, an analog signal is generated from the analog line as an analog input for the ECU

Abstract: A light-emitting device comprises a first light-emitting semiconductor stack comprising a first active layer; a second light-emitting semiconductor stack below the first light-emitting semiconductor stack, wherein the second light-emitting semiconductor stack comprises a second active layer; a reflector between the first light-emitting semiconductor stack and the second light-emitting semiconductor stack; a protecting layer between the reflector and the second light-emitting semiconductor stack; and wherein the first light-emitting semiconductor stack further comprises a first semiconductor layer and a second semiconductor layer sandwiching the first active layer, the second light-emitting semiconductor stack further comprises a third semiconductor layer and a fourth semiconductor layer sandwiching the second active layer, wherein the second semiconductor layer has a first band gap, the third semiconductor layer has a second band gap, and the protecting layer has a third band gap between the first band gap an

Abstract: An adder adds a noise signal, an input signal, and a feedback signal. A threshold determination unit compares an addition signal output from the adder with a predetermined threshold, and outputs an ignition pulse signal. A transient response unit causes transient response of the ignition pulse signal, and generates an output signal. An intensity adjustment unit is formed of a variable resistor provided on a feedback loop, adjusts intensity of the feedback signal, and inputs the feedback signal to the adder.

Abstract: It is often desirable to transmit data between circuits or components operating at a relatively high voltage and circuits operating at a relatively low voltage. Such a task can be performed by use of an isolator. Some isolator designs use magnetic coupling to transfer the data as this is more robust against inadvertently transmitting high voltage transients than capacitor based isolators. However it is often desirable to encode the data for exchange across the transformer of the isolator and decode after transmission across the transformer. This requires power for the encoding and decoding circuits. To ensure both sides are powered, power may be transferred by another transformer. The transformer primary is driven by an oscillating signal. The system disclosed in some embodiments herein varies the frequency of the oscillating signal to mitigate the risk of it interfering with other circuits or systems associated with the isolator.

Abstract: In one form, a spread spectrum clock generator includes an oscillator and a digital modulator. The oscillator has a control input for setting an output frequency, and an output for providing a clock output signal. The digital modulator is responsive to the clock output signal to provide a control code to the control input of the oscillator as a periodic signal with a plurality of discrete steps, wherein the digital modulator provides said control code at each of said plurality of discrete steps for substantially a predetermined time.

Abstract: An apparatus is presented for generating a true random number generator (TRNG). The apparatus includes a magnetic tunnel junction (MTJ) device including a first layer, a second layer, and third layer, as well as a bias circuit to bias the MTJ device along with a pulse height discriminator and a time-to-amplitude convertor to generate random bit-streams. The second layer is a barrier layer with an energy barrier height in the order of 20 kT, where k is the Boltzmann constant and T is the absolute temperature. Random flipping of an orientation of magnetization of the third layer is induced by thermal fluctuations in the MTJ device.

Abstract: A plurality of antenna elements may receive a plurality of signals. Each of the plurality of antenna elements may correspond to at least one of a plurality of sectors of a sectorized antenna. A receiver may process each of the plurality of signals in parallel, including decoding one or more messages from the plurality of signals. The receiver may output at least one of the one or more messages.

Abstract: A memory controller has a first variable delay circuit that delays a data strobe signal received from a memory, and a second variable delay circuit that variably delays a data signal which is received from the memory and is synchronous with the data strobe signal, and that is set a second delay amount which is different from a first delay amount of the first variable delay circuit.

Abstract: Memristor-based nano-crossbar computing is a revolutionary computing paradigm that does away with the traditional Von Neumann architectural separation of memory and computation units. The computation of Boolean formulas using memristor circuits has been a subject of several recent investigations. Crossbar computing, in general, has also been a topic of active interest, but sneak paths have posed a hurdle in the design of pervasive general-purpose crossbar computing paradigms. Various embodiments are disclosed which demonstrate that sneak paths in nano-crossbar computing can be exploited to design a Boolean-formula evaluation strategy. Such nano-crossbar designs are also an effective approach for synthesizing high performance customized arithmetic and logic circuits.

Abstract: A optical control sensor system includes a driver controlling an operation of a light source coupled to an end of an optical fiber, an orthogonal signal generator, generating a set of different orthogonal signals controlling the driver, a terminal sensor coupled to another end of the optical fiber selecting a predetermined set of input orthogonal signals for converting them into component combinations, constituting output signals, and directing the output signals back to the optical fiber, a device coupled to the light sources and to the first end of the optical fiber for extracting output signals that have passed through a return path in the optical fiber, a detector converting optical output signals into electrical signals, and a selector and a decoder connected to the orthogonal signal generator indicating a current state of the optical control sensor system based on an analysis of the selected combinations of components in the output signals.

Abstract: A mechanism is provided for a circuit for generation of a random output. A bistable circuit has two stable states as an output and a clock signal as an input. The bistable circuit includes a first logic circuit and a second logic circuit cross-coupled connected together, which transition into a metastable state before resolving to the two stable states. The second logic circuit resolves to a stable state at a resolution time. A digitization circuit is configured to generate random bits corresponding to a variance of the resolution time of the second logic circuit resolving from the metastable state to the stable state for cycles of the clock signal. The resolution time randomly varies according to noise. An actual value of the stable state is eliminated as factor in generating the random bits.

Abstract: Disclosed is a method for producing, in an electronic circuit, a varying digital output in response to edges of a received clock signal. The method includes generating, within circuitry of the electronic circuit, an unbalanced, pseudo-random binary output of the circuitry. The method also includes generating, within the electronic circuit and from the received clock, a sub-rate clock version of the received clock. The method also includes carrying out, within the electronic circuit, an exclusive OR operation between the sub-rate clock and the pseudo-random binary output of the circuitry to produce a balanced, pseudo-random binary output.

Abstract: An oscillator generates a clock signal according to a voltage, a current and a capacitance, and a frequency jitter circuit and method use a random number to modulate the voltage, the current or the capacitance, or a count value to modulate the capacitance, to jitter the frequency of the clock signal.

Abstract: In accordance with an embodiment, a method of generating noise includes generating, using a hardware-based noise generator, a plurality of periodic waveforms having different frequencies, weighting, using the hardware-based noise generator, amplitudes of the plurality of periodic waveforms based on a predetermined spectral shape to form a plurality of weighted waveforms, and summing the plurality of plurality of weighted waveforms to form an output random noise signal.

Abstract: A self-feedback random generator comprises a digital-to-analog converter, a digital oscillator, a frequency-modulating unit and a first D-type flip-flop. The digital-to-analog converter receives a digital random-code signal and the digital random-code signal is converted to corresponding analog random signal. The frequency-modulating unit modulates frequency of first digital oscillating signal so as to increase random of frequency of first digital oscillating signal according to voltage value of the analog random signal, and accordingly outputs a second digital oscillating signal.

Abstract: A self-feedback random generator comprises a digital-to -analog converter, a digital oscillator, a frequency-modulating unit and a first D-type flip-flop. The digital-to-analog converter receives a digital random-code signal and the digital random-code signal is converted to corresponding analog random signal. The frequency-modulating unit modulates frequency of first digital oscillating signal so as to increase random of frequency of first digital oscillating signal according to voltage value of the analog random signal, and accordingly outputs a second digital oscillating signal.

Abstract: Various embodiments are directed to systems and methods for combining a plurality of codes. The plurality of codes may be binary codes having possible logical values of ?1 and +1 and may comprise an even number of codes. An output of the combining v0,k may be given by: v0=sgn(vi), where vi is the sum of the first plurality of codes at the first time. Embodiments for allocating different power levels among various codes are presented.

Abstract: A receiver for decoding a communication signal is disclosed. The receiver includes an input port and a filter. The input port receives the communication signal from a communication medium. The communication signal comprises a sequence of symbols. Each symbol of the symbol sequence is an analog pulse that has a leading edge of exponential shape. The exponential shape has an exponential growth parameter value that has been selected from values ?0 and ?1, which are distinct positive values. For each symbol of the symbol sequence, the exponential growth parameter value for the leading edge of the symbol has been selected based on a corresponding bit from a stream of information bits. The filter receives the communication signal from the input port and filters the communication signal to obtain an output signal. The transfer function of the filter has one or more zeros at ?0.

Abstract: Methods and apparatus for wireless communication in a wireless communication network that includes receiving a synchronization channel (SCH) signal (including a primary synchronization channel (PSCH) signal, a secondary synchronization channel (SSCH) signal, and a primary scrambling code (PCH) signal) and a part of a common pilot channel (CPICH) signal in the same portion of the slot of the frame. The aspects include determining and summing the PSCH signal, SSCH signal, and PCH signal corresponding to the portion of the slot of the frame. The aspects also include de-spreading the pilot symbol over the portion of the slot of the frame based on the summed PSCH signal, the SSCH signal, and the PCH signal and estimating an estimated pilot symbol for the portion of the slot of the frame, where the estimated pilot symbol is a sum of the de-spread PSCH signal, de-spread SSCH signal, and de-spread PCH signal.

Abstract: A multiple-phase clock generator includes at least one stage of dividers. A clock signal is supplied as a first stage clock input to dividers in a first stage of dividers. An N-th stage includes 2N dividers, where N is a positive integer number. Each divider in the first stage is configured to divide a first clock frequency of the first stage clock input by 2 to provide a first stage output. Each divider in the N-th stage is configured to divide an N-th clock frequency of an N-th stage clock input by 2 to provide an N-th stage output. The N-th stage outputs from the dividers in the N-th stage provide 2N-phase clock signals that are equally distributed with a same phase difference between adjacent phase clock signals.

Abstract: An edge alignment apparatus includes: a signal source, for generating a first and a second square wave signals; a phase delay circuit, for receiving the first and the second square wave signals to generate a delayed first and a delayed second square wave signals; a data circuit, for generating a third square wave signal according to the delayed second square wave signal; and a phase calibrating circuit, for receiving the third square wave signal and the delayed first squared wave signal to generate at least one phase tuning signal to the phase delay circuit for tuning a phase difference between the delayed first and the delayed second square wave signals, such that a signal edge of the third square wave signal aligns with that of the first square wave signal. The first, second and third square wave signals have a same frequency.

Abstract: A first transmitter transmits symbols. The leading edge of each symbol has the form Djexp{?jt}, where Dj is real, where ?j is selected from N possible values based on a current group of bits. The receiver has N filters whose transfer functions correspond respectively to the N possible values. The filter outputs are used to recover the group of bits. A second transmitter transmits an exponential symbol or a zero symbol depending on a current bit to be transmitted. The zero symbol has zero amplitude over the symbol period. The corresponding receiver applies threshold detection to estimate the transmitted bits. A third transmitter transmits a sequence of analog pulses with known interpulse time separation(s). The pulse sequence reflects from a moving object. A receiver captures the reflected pulse sequence. The interpulse separation(s) of the reflect pulse sequence is used to determine the radial velocity of the object.

Abstract: A voltage pulse train generator which may find application to control of an ultrasound piezoelectric injector, and including a voltage source providing a DC initial voltage, a DC/DC converter supplied with the initial voltage and configured to charge a capacitor according to an intermediate DC voltage greater than the initial voltage, a DC/AC converter operating by switching, by alternating active phases and inactive phases, which is configured to transform the intermediate voltage from the capacitor into a final voltage pulse train, and a control unit provided for driving the converters. The DC/DC converter is configured to operate to charge the capacitor at a same time as the DC/AC converter, at most during the inactive phases of the switching of the DC/AC converter.

Abstract: The present specification provides a method, apparatus and system for sensing a signal with automatic adjustments for changing signal levels. A novel fractional peak discriminator circuit is provided which can be incorporated into a system for measuring periodic signals from moving elements. The circuit can be used regardless of whether the periodic signals are detected using optics, magnetic detector or other methods.

Abstract: A method and apparatus for measuring the duration of a transient signal with high precision.

Abstract: A device for bit-demultiplexing in a multicarrier MIMO communication system (e.g. precoded spatial multiplexing MIMO communication systems using adaptive OFDM), including a multicarrier MIMO transmitter and a multicarrier MIMO receiver. The multicarrier MIMO transmitter includes a demultiplexer and symbol mapper unit receiving an input bit stream and generating a plurality of symbol streams, each symbol stream being associated with a different transmission channel and including a plurality of data symbols, each data symbol being attributed to a different carrier; one or more multicarrier modulators generating at least two multicarrier modulated signals based on the symbol streams; and at least two transmit ports respectively transmitting the at least two multicarrier modulated signals, wherein a data throughput rate of each transmission channel is separately variable.

Abstract: A frequency multiplier in accordance with some embodiments of the inventive concept may include a pulse generator receiving a differential clock signal from a delay locked loop having a plurality of delay cells to generate a pulse signal for generation of a multiplication clock signal. The pulse generator comprises an intermediate pulse signal generation unit receiving the differential clock signal to generate intermediate pulse signals; and an overlap correction unit correcting an overlap between the intermediate pulse signals to generate correction pulse signals.

Abstract: Apparatus for generating a truly random binary bit value in which the resistance of memristive devices serve as the analogue bit values. Resistance values and the randomness by which they are generated stems from the inherently non-uniform, irreproducible variations in the materials of which the system is composed.

Abstract: A waveform generator has a waveform generation circuit storing waveform data for an analog waveform signals having dead time periods without the need for storing data on the dead time. A sequencer having a sequence memory stores sequence data that controls the sequencing of one or more signal components and associated dead times of the analog waveform signal. The timing of the dead time is controlled by a sampling clock and a wait time counter. The generation of the signal components is controlled by the sampling clock controlling the generation of addresses for a waveform memory storing digital data of the sampling components. The waveform memory digital data is converted to an analog waveform signal.

Abstract: A dither circuit yielding a variable resistance.

Abstract: Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit.

Abstract: Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit.

Abstract: The present invention firstly relates to a device for generating noise signals. Said device comprises at least one avalanche diode which is arranged in such a way that it is reverse-biased during intended operation of the device. Moreover, the invention relates a method for generating a noise signal by means of such a device and to a use of said device and to a method for evaluating a type of an avalanche diode or of an avalanche transistor.

Abstract: Determining a frequency offset of a received signal utilizing two or more multipath components of the received signal is provided herein. By way of example, the received signal can be correlated with a synchronization sequence in a time domain or a frequency domain, resulting in separation of the two or more multipath components of the received signal. Analysis of at least one of the multipath components can provide a frequency offset of the received signal. Furthermore, by analyzing the multipath components, estimation of the frequency offset can be improved as compared with single-signal analysis techniques.

Abstract: A latch integrated circuit has synchronous data loading and self-timed asynchronous data capture characteristics. The integrated circuit may include a latch, a pulse generator and a comparator. The latch can be responsive to a data signal and a write enable signal. The pulse generator may be configured to generate the write enable signal as a pulse. This pulse may have a leading edge synchronized with a first edge of a clock signal and a self-timed trailing edge synchronized with an edge of a comparison signal. The comparator may be configured to generate the comparison signal in response to comparing logic levels of at least two nodes within the integrated circuit.

Abstract: The present invention provides a signal input device of a digital-RF converter including: a phase-modulated signal input unit configured to input a phase-modulated carrier signal to an LO switch of a digital-RF converter; and a digital signal input unit configured to correct a digital signal to correspond to the phase-modulated carrier signal, and input the corrected digital signal to a data switch of the digital-RF converter.

Abstract: A control device (1) and a triggering device (2) are coupled to one another for data processing. The control device and the triggering device (2) are electronic devices. The control device (1) determines a respective desired position value (p*) for at least one shaft with an interpolation cycle (T) and transmits a time delay (t) to the triggering device (2). The triggering device (2) monitors when the time delay (t) expires from transmission of the time delay (t) and then outputs a trigger pulse (I).

Abstract: Method, circuitry and device for spreading a clock signal in which the clock signal is received at an input of a variable delay line, the clock signal having been generated by a clock signal generator. In one embodiment, for each edge of the clock signal, the delay introduced by the variable delay line is set in accordance with a stored delay value. For each of a plurality of consecutive edges of the clock signal, the stored delay value is either incremented or decremented based on a randomly generated value for that edge. A spread version of the clock signal is output from the variable delay line, wherein each edge of the spread version of the clock signal is delayed by the respective delay that is set for that edge of the clock signal.

Abstract: An integrated circuit device includes a first rectangular wave signal generation section that outputs a first rectangular wave signal when an amplitude of an oscillation signal inputted is greater than a first amplitude, and a second rectangular wave signal generation section that outputs a second rectangular wave signal when the amplitude of the oscillation signal is greater than a second amplitude that is greater than the first amplitude, and that controls the power supply voltage of an oscillation circuit by the first and second rectangular wave signals so as to maintain an appropriate potential difference with respect to a stop voltage against changes in the oscillation stop voltage associated with changes in a temperature condition.

Abstract: A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.

Abstract: An internal clock generating circuit and a method for generating an internal clock signal are disclosed. The internal clock generating circuit includes a transition detecting block for detecting transitions in a data signal and generating data transition information, and an internal clock generating block for generating and storing a period digital data while detecting the unit period of the data signal in a period confirming mode. In the internal clock generating circuit, the internal clock signal can be generated without the external clock signal, so that the internal clock generating circuit can be implemented with a simple constitution. Additionally, an extra locking time is not required for locking the extra clock signal, so that the operating speed of the internal clock generating circuit is improved. The internal clock signal is dependent on the data signal, so that it is easy to control the set-up and hold for data.

Abstract: A sampling frequency offset estimation apparatus of an orthogonal frequency division multiplexing (OFDM) system includes a first differential operation unit performing complex conjugate multiplication of scattered pilots of complex symbols subjected to a fast Fourier transform (FFT) in an OFDM receiver, an interpolation unit repeating an operation of obtaining a median complex symbol between two consecutive symbols among complex symbols having first phase difference information from the first differential operation unit by a predetermined number, a second differential operation unit performing complex conjugate multiplication of two consecutive median complex symbols among median complex symbols from the interpolation unit, and a sampling frequency offset estimation unit estimating sampling frequency offset using complex symbols having second phase difference information from the second differential operation unit.

Abstract: A nonlinear filter includes: a determination unit that determines, based on I and Q signals inputted into the determination unit, whether or not to perform pulse insertion; a rotation detector that detects a rotation direction of the I and Q signals on an IQ plane with respect to the origin of the IQ plane; a pulse generator that generates, when the determination unit determines to perform the pulse insertion, a pulse of which at least one of the direction and the magnitude is determined in accordance with at least the detected rotation direction; and an adder that inserts the pulse into the I and Q signals and outputs resultant I and Q signals.

Abstract: In an example embodiment, the semiconductor device includes a clock signal generation circuit. The clock signal generation circuit is configured to generate at least one control clock signal in response to an external clock signal and a read command signal. The clock signal generation circuit includes a plurality of delay circuits, and the clock signal generation circuit is configured to selectively disable at least one of the plurality of delay circuits to reduce power consumption.

Abstract: The present invention realizes low power consumption at the time of an automatic frequency control circuit operation. An automatic frequency control circuit includes a mixing unit that generates a modulated signal from a reception signal according to a frequency of a local signal, a demodulation unit that demodulates the modulated signal supplied by the mixing unit, an error evaluation unit that generates a frequency error signal according to a duty of the demodulated signal supplied by the demodulation unit, a holding unit that holds a frequency setting of the local signal and updates the frequency setting according to the frequency error signal supplied by the error evaluation unit, and an oscillation unit that controls a frequency of the local signal according to the frequency setting supplied by the holding unit.

Abstract: A multi-port circuit and corresponding method for simultaneous shaping of sub-nanosecond pulses (MCS3P). The MCS3P includes a coupled-line coupler, a Schottky detector diode, and circuitry for compressing the rising and falling edges of a waveform. The MCS3P simultaneously produces square wave, Gaussian, and monocycle waveforms by differentiating a sinusoidal source. The method includes the steps of compressing the rising edge of a sinusoidal source waveform, differentiating the resulting waveform to form a square waveform and a Gaussian waveform, filtering out the positive going Gaussian to produce a negative going Gaussian, differentiating the Gaussian waveform to form a monocycle waveform, and compressing the falling edge of the square waveform to produce a square wave form with both edges compressed.

Abstract: A circuit breaker having break contacts for disconnecting an electric grid or network in a predetermined manner includes a trigger unit which triggers actuation of the break contacts in response to signals received from a detector which detects aperiodic, substantially step-like changes in the amplitude of at least one electric parameter in the electric network. The trigger unit is operatively connected with the detector. The disclosed circuit breaker reduces the likelihood of a fire caused by faults in electric networks.