Abstract: Systems and methods are disclosed for playback of detected timing events with detected phase variations. Disclosed signal generation embodiments can be used to generate digital signals having desired phase variation. Disclosed event detection circuitry can be used to generate event timing data representing one or more phase variations in detected events. The disclosed signal generation embodiments can utilize the event timing data to playback detect events along with the measured phase variations. Further, the signal generation circuitry and the event detection circuitry can be implemented in different devices or can be implemented in the same device.

Abstract: A deskewing apparatus includes a power supply connector, a oscillator, a first switch unit, a second switch unit, a first logic member, a second logic member, a clock generator and a plurality of output channels. The oscillator generates an electrical signal with a predetermined frequency and sinusoidal waveform. The first switch unit and the second switch unit each generates on/off signals by controlling power on/off. The first logic member and the second logic member generate logic signals according to the corresponding on/off signals from the first switch unit and the second switch unit. The clock generator multiplies the frequency of the electrical signal based on the combination of the logic signals and converting the electrical signal from sinusoidal waveform into rectangular waveform. The output channels output the converted electrical signal.

Abstract: A signal generating circuit and method are disclosed that do not require a phase-locked-loop and a low frequency temperature-stable oscillator. The method may include generating an oscillating output signal responsive to a feedback signal, where the feedback signal controls a frequency of the oscillating output signal, generating a current output signal having a magnitude corresponding to the frequency of the oscillating output signal, and then comparing the current output signal to a reference signal to generate the feedback signal. The signal generating circuit may include an oscillator circuit responsive to a feedback signal and a frequency-to-current conversion circuit configured to generate a frequency dependent current signal that is compared to a reference current to generate an output signal corresponding to the frequency of the oscillating output signal. A feedback conversion circuit compares the output signal with a reference signal to generate the feedback signal to the oscillator circuit.

Abstract: A picosecond pulse generator apparatus and methodology is disclosed. A pulse generator is provided by forming a transmission line and a switching element on a common semiconductor substrate or semiconductor chip. The transmission line and the switching element can be provided on the common CMOS semiconductor substrate using standard CMOS technology. A voltage is applied to the transmission line to charge the transmission line. An input pulse is applied to the switching device to trigger the switching device to cause the transmission line to discharge an output pulse across a load resistor. The pulse width of the output pulse depends in major part on the length of the transmission line. Additional components can be provided on the common semiconductor substrate or chip to shape the input pulse to the switching device to ensure a fast rise time.

Abstract: A system is provided for generating a plurality of different voltage level clock signals. The system comprises an electrical energy storage pack having a plurality of series coupled electrical energy storage cells that provide a plurality of different output voltage level, a reference oscillator that provides a reference clock signal and a plurality of voltage clamps that receive the plurality of different output voltage levels and output the plurality of different voltage level clock signals at respective output nodes. The plurality of voltage clamps are configured to clamp each of a given output node to a respective high-side voltage level in response to pulling up of the given output node toward a respective high output voltage level and to clamp each of the given output node to a respective low-side voltage level in response to pulling down of the output node toward a low output voltage level.

Abstract: A multi-port circuit and corresponding method for simultaneous shaping of sub-nanosecond pulses (MCS3P). The MCS3P includes a coupled-line coupler, a Schottky detector diode, and circuitry for compressing the rising and falling edges of a waveform. The MCS3P simultaneously produces square wave, Gaussian, and monocycle waveforms by differentiating a sinusoidal source. The method includes the steps of compressing the rising edge of a sinusoidal source waveform, differentiating the resulting waveform to form a square waveform and a Gaussian waveform, filtering out the positive going Gaussian to produce a negative going Gaussian, differentiating the Gaussian waveform to form a monocycle waveform, and compressing the falling edge of the square waveform to produce a square wave form with both edges compressed.

Abstract: A signal generator includes: an adjusting circuit arranged to adjust a first amplitude of an oscillating signal to generate an adjusted oscillating signal; and a resistor ladder circuit arranged to receive the adjusted oscillating signal to generate a plurality of candidate output oscillating signals having a plurality of different amplitudes respectively and output an output oscillating signal selected from the candidate output oscillating signals.

Abstract: A first signal processor performs predetermined signal processing on an input signal to provide a change to at least one of the characteristic values thereof. A second signal processor is provided in the subsequent stage of the first signal processor and performs predetermined signal processing on an output signal from the first signal processor to provide a change to a characteristic value thereof. An amount of change provided to the characteristic value of the signal by the second signal processor is dependent on a power supply voltage. An amount of change provided to the characteristic value of the signal by the first signal processor is configured to be adjustable. A control circuit monitors a power supply voltage supplied to the second signal processor and adjusts in accordance with the power supply voltage the amount of change provided to the characteristic value of the signal by the first signal processor.

Abstract: An impulse waveform generating apparatus comprises an oscillator for generating a reference signal having a center frequency in a frequency band of an impulse to generate, a timing matching circuit for shifting a phase of the reference signal by 90 degrees, a frequency demultiplier for dividing a frequency of the phase shift signal and obtaining a timing signal having a frequency component having a frequency width of an impulse to generate, a memory storing a waveform shape table, a waveform forming section for forming a waveform in synchronism with the timing signal, according to information of a shape table having a predetermined waveform, a low-pass filter for obtaining an envelope signal from an output signal of the waveform forming section, and a waveform generating section for changing an amplitude of the reference signal according to a value of the envelope signal.

Abstract: A system and method for altering the properties of a material by exposure of the material to a magnetic field is described herein. The method comprises generating a magnetic field; exposing a material to the magnetic field, and determining the optimum settings of the magnetic field parameters for the particular material. The magnetic field may be time varying or time invariant. Various properties of the magnetic field can be altered to determine the optimum settings for altering the material properties, including the amplitude, frequency, and waveform. In one embodiment, a method for improving the conductivity of a transmission line is provided, comprising: providing a high voltage electrical transmission line; temporarily installing a magnetic field generator along at least a portion of the transmission line; and generating a pulsed magnetic field around at least a portion of the transmission line using the magnetic field generator and simultaneously running a current through the transmission line.

Abstract: A semiconductor device includes a latency signal generating circuit for generating a latency signal corresponding CAS latency by measuring a delay amount reflected at a delay locked loop and reflecting the measured delay amount at a read command signal, and a delay locked loop for controlling an internal clock signal applied to the latency signal generating circuit corresponding to the read command and the latency signal. The semiconductor device includes an internal clock signal generating block configured to generate an internal clock signal, a latency generating block configured to generate a latency signal by synchronizing a read command signal with the internal clock signal at a time corresponding to a CAS latency value and a measured delay value, and an input controlling block configured to activate the reference clock signal using an external clock signal in response to the read command signal and the latency signal.

Abstract: A duty cycle correction circuit comprises first and second pulse generators, a clock dividing unit, a detecting unit, and a pulse width control unit. The first pulse generator is configured to generate a first edge of a first pulse signal in synchronization with a first edge of a first clock signal, and the second pulse generator is configured to generate a first edge of a second pulse signal in synchronization with a second edge of the first pulse signal. The clock dividing unit is configured to generate a second clock signal by dividing the frequency of the first clock signal. The detecting unit is configured to generate a detecting signal according to the second clock signal and a time interval between the first edge of the first pulse signal and a second edge of the second pulse signal. In particular, pulse widths of the first and second pulse signals are the same and are adjustable according to a control signal from the pulse width control unit.

Abstract: Apparatus and methods for providing multi-mode clock signals are disclosed. In some embodiments, a multi-mode driver configured to receive a first clock signal, and to selectively output a different clock signal in response to one or more signals from a controller is provided. The driver can include an H-bridge circuit without substantial increases in the size of the design area. Advantageously, lower jitter and improved impedance matching can be accomplished.

Abstract: A semiconductor integrated circuit includes a clock generator for generating a second clock signal having a frequency that varies over time by using a first clock signal having a fixed frequency, a test circuit for generating a digital signal according to a difference between a first frequency corresponding to the first clock signal and a second frequency corresponding to the second clock signal by a digital logic operation based on the first clock signal and the second clock signal, and a signal path for outputting the digital signal generated by the test circuit.

Abstract: There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original clock signal, with the original clock signal and to select a signal based on the proximity of the phase characteristic of the three signals to the original signal. The selection of a clock signal that most closely approximates the original significantly reduces lock time when attempting to synchronize an internal clock with an external clock. Additionally, there is provided a method for comparing three clock signals with an original clock signal and selecting from the three clock signals one that is approximately in phase with the original clock signal.

Abstract: Timing setting data include an arbitrary combination of a set timing signal indicating a positive edge timing and a reset timing signal indicating a negative edge timing. A sort unit sorts n pieces of the timing setting data in accordance with timing orders indicated by each of the timing setting data. With reference to the sorted timing setting data an open processor detects continuation of the set timing signals or continuation of the reset timing signals, and invalidates one of the continuous set timing signals or one of the continuous reset timing signals. An edge assigning unit sequentially assigns the set/reset timing signals remaining without being invalidated to, among the m variable delay circuits for setting/resetting, the variable delay circuits for setting/resetting in the ascending order of the frequencies of use thereof by then.

Abstract: A clock generation circuit for a semiconductor memory apparatus includes an internal clock generation unit that receives a clock and generates an internal clock, and a clock selection unit that selectively outputs the clock or the internal clock in response to a selection signal.

Abstract: A relay and a controller for the same are disclosed. The relay includes an isolated power supply configured to receive a voltage input and generate a voltage output based upon the voltage input, an isolator configured to receive an input signal and generate an isolated output signal based upon the input signal, at least one switch, and a driver in electrical communication with the isolated power supply, the isolator, and the at least one switch for controlling the at least one switch in response to the isolated output signal, wherein the driver receives the voltage output from the isolated power supply as an operating voltage. The controller is in signal communication with the isolator to generate and transmit the input signal thereto.

Abstract: A generator of synchronization pulses intended for at least two registers, including a first input intended to receive a clock signal and at least one output intended to deliver the pulses on the clock input of said registers, and at least one second input intended to receive a signal for forcing the output, independently from the clock signal, to make said registers transparent.

Abstract: A digitally controlled LC-tank oscillator is constructed by connecting different tuning circuits to a LC tank. The tuning circuit includes a single bank of tuning cells, a dual bank of tuning cells, or a fractional tuning circuit. Each of said tuning cells in the tuning circuit includes a tuning circuit element and a memory cell.

Abstract: According to an embodiment, a circuit includes an amplifier and an open-loop control system. The amplifier has an output stage for amplifying a signal, a power supply for driving a supply voltage of the output stage to different voltage levels responsive to being modulated and a pulse width modulator for modulating the power supply responsive to a mask input. The open-loop control system includes a mask generator and a detector. The mask generator is configured to generate the mask input as a function of the envelope of the signal. The detector is configured to detect discontinuities in the mask input and compensate for the discontinuities.

Abstract: A method for controlling pulsed power that includes measuring a first pulse of power from a power amplifier to obtain data. The method also includes generating a first signal to adjust a second pulse of delivered power, the first signal correlated to the data to minimize a power difference between a power set point and a substantially stable portion of the second pulse. The method also includes generating a second signal to adjust the second pulse of delivered power, the second signal correlated to the data to minimize an amplitude difference between a peak of the second pulse and the substantially stable portion of the second pulse.

Abstract: A voltage pulse train generator which may find application to control of an ultrasound piezoelectric injector, and including a voltage source providing a DC initial voltage, a DC/DC converter supplied with the initial voltage and configured to charge a capacitor according to an intermediate DC voltage greater than the initial voltage, a DC/AC converter operating by switching, by alternating active phases and inactive phases, which is configured to transform the intermediate voltage from the capacitor into a final voltage pulse train, and a control unit provided for driving the converters. The DC/DC converter is configured to operate to charge the capacitor at a same time as the DC/AC converter, at most during the inactive phases of the switching of the DC/AC converter.

Abstract: The present invention discloses a cooperation circuit, comprising: a first control module, capable of generating a first control signal and a second control signal, the pulse width of the first control signal being determined by the pulse width of the second control signal; and a second control module, coupled to the first control module to receive the first control signal and the second control signal and generate a third control signal according to the first control signal and the second control signal; wherein, according to the first control signal and the second control signal, the second control module enables the third control signal and the second control signal to exhibit the same frequency and the same duty cycle with a phase delay.

Abstract: An apparatus and method for generation of a noise signal are provided. The apparatus includes a noise synthesizing module and a noise signal transfer module. The noise synthesizing module includes a voltage controlled oscillator, a phase frequency detector, a phase locked loop filter, and a reference generator which form a phase locked loop. An output signal of the reference generator is provided to a first phase-frequency input of the phase-frequency detector, and an output signal of the voltage controlled oscillator is provided to a second input of the phase-frequency detector. An output signal of the phase-frequency detector is provided to an input of the phase locked loop filter, and an output of the phase locked loop filter is provided to a frequency control input of the voltage controlled oscillator.

Abstract: A circuit breaker having break contacts for disconnecting an electric grid or network in a predetermined manner includes a trigger unit which triggers actuation of the break contacts in response to signals received from a detector which detects aperiodic, substantially step-like changes in the amplitude of at least one electric parameter in the electric network. The trigger unit is operatively connected with the detector. The disclosed circuit breaker reduces the likelihood of a fire caused by faults in electric networks.

Abstract: A random number generating apparatus and method for generating a metastable state signal by using logic gates include a metastable state generating unit generating and outputting a metastable state signal; an amplifying unit receiving the metastable state signal from the metastable state generating unit, amplifying the received metastable state signal, and outputting the amplified metastable state signal; and a sampling unit receiving the amplified metastable state signal and a sampling clock, and sampling and outputting the amplified metastable state signal according to the sampling clock.

Abstract: Timing setting data include an arbitrary combination of a set timing signal indicating a positive edge timing and a reset timing signal indicating a negative edge timing. A sort unit sorts n pieces of the timing setting data in accordance with timing orders indicated by each of the timing setting data. With reference to the sorted timing setting data an open processor detects continuation of the set timing signals or continuation of the reset timing signals, and invalidates one of the continuous set timing signals or one of the continuous reset timing signals. An edge assigning unit sequentially assigns the set/reset timing signals remaining without being invalidated to, among the m variable delay circuits for setting/resetting, the variable delay circuits for setting/resetting in the ascending order of the frequencies of use thereof by then.

Abstract: A clock signal generator including: a signal generation unit that outputs a first clock signal composed of a single frequency component; and a phase angle detection unit that detects phase angles of the first clock signal by comparing a plurality of threshold values set within the amplitude of the first clock signal with instantaneous values of the first clock signal by using window comparators, and generates a second clock signal by determining rising and/or falling edges of the signal according to the detected phase angles.

Abstract: This invention relates to a pulse generator circuit for delivering a short high current pulse to a load. This pulse generator comprises a junction recovery diode, a switch, a first resonant circuit and a second resonant circuit. The diode may be configured to store charges in its depletion layer when there is a forward flow of a current and to rapidly switch open after the depletion layer is discharged by a reverse flow of a current. After the diode rapidly switch opens, the pulse generator may provide a reverse current to the load. This pulse generator may be configured to generate at least one pulse that is having a length of no more than 100 nanoseconds at the full-width-at-half-maximum and an amplitude of at least 1 kilovolt. Electrodes may be connected to the pulse generator to deliver one pulse or plurality of pulses to biological cells such as tumor cells.

Abstract: An amplitude, phase and frequency modulator circuit is provided with the circuit containing a periodically driven switch. The circuit connects a DC power source and a resistive load. Periodic operation of the switch generates a square-wave of voltage across the load. A transistor used as a switch is embedded in a switch driver that controls base current and base-emitter reverse bias voltage. The modulator DC input resistance is approximately equal to the load resistance when the switch ON-state period and OFF-state period are approximately equal. The modulator efficiency is nearly one hundred percent. The frequency response of the square-wave modulator system is high-pass with a lower cutoff frequency determined by element values.

Abstract: The impulse generator comprises a nonlinear transmission line capable of obtaining an impulse with a small half value width and a large amplitude, in which a plurality of transmission line units having a unit line unit and a diode are connected in series, a pulse generator connected to the transmission terminal of the nonlinear transmission line, and a bias-dependent element connected to the reception terminal of the nonlinear line, wherein the anode of the diode of the transmission line unit is connected to the transmission line and the cathode is connected to the ground, and one end of the bias-dependent element is connected to the reception terminal of the transmission line and the other end is biased to a negative potential.

Abstract: This invention relates to a pulse generator circuit for delivering a short high current pulse to a load. This pulse generator comprises a junction recovery diode, a switch, a first resonant circuit and a second resonant circuit. The diode may be configured to store charges in its depletion layer when there is a forward flow of a current and to rapidly switch open after the depletion layer is discharged by a reverse flow of a current. After the diode rapidly switch opens, the pulse generator may provide a reverse current to the load. This pulse generator may be configured to generate at least one pulse that is having a length of no more than 100 nanoseconds at the full-width-at-half-maximum and an amplitude of at least 1 kilovolt. Electrodes may be connected to the pulse generator to deliver one pulse or plurality of pulses to biological cells such as tumor cells.

Abstract: The present invention is a microwave generating apparatus comprising: a switch signal generator that generates a square wave switch signal having a fundamental frequency of a microwave band; a switching power amplifier that performs a switching power amplification based on the switch signal so as to output an amplified signal; a variable voltage supplier that is capable of variably supplying a driving voltage for amplification to the switching power amplifier; a microwave selector that extracts from the amplified signal a sine wave signal of the same frequency as the fundamental frequency of the switch signal so as to output the same as a microwave; an output signal detector that detects the microwave; and a driving voltage controller that controls the variable voltage supplier based on a result detected by the output signal detector.

Abstract: A pseudo random clock generator includes a clock generator for generating a clock signal. A pseudo random code generator receives the clock signal and thereby generating a pseudo random code. A code limiter enables the value of the pseudo random code being unchanged for at least two periods of the clock signal. A logic gate applies a logic operation to the pseudo random code and the clock signal and thereby outputting a pseudo random clock.

Abstract: A method for manufacturing a quartz crystal unit comprises the steps of adjusting an oscillation frequency of a quartz crystal tuning fork resonator that is vibratable in a flexural mode of an inverse phrase and that has first and second quartz crystal tuning fork tines, forming at least one groove in each of two of opposite main surfaces of each of first and second quartz crystal tuning fork tines, disposing an electrode on a surface of the at least one groove formed in each of two of the opposite main surfaces and each of two of opposite side surfaces of each of the first and second quartz crystal tuning fork tines so that the electrodes of the grooves of the first quartz crystal tuning fork tine are connected to the electrodes of the side surfaces of the second quartz crystal tuning fork tine and the electrodes of the grooves of the second quartz crystal tuning fork tine are connected to the electrodes of the side surfaces of the first quartz crystal tuning fork tine, the quartz crystal tuning fork resonat

Abstract: A method for manufacturing a quartz crystal unit comprises the steps of forming a quartz crystal tuning fork resonator vibratable in a flexural mode of an inverse phase and having a quartz crystal tuning fork base and first and second quartz crystal tuning fork tines connected to the quartz crystal tuning fork base, forming at least one groove having at least three stepped portions in at least one of opposite main surfaces of each of first and second quartz crystal tuning fork tines, disposing an electrode on a surface of one of the at least three stepped portions of the at least one groove and an electrode on one of opposite side surfaces of each of the first and second quartz crystal tuning fork tines, mounting the quartz crystal tuning fork resonator on a mounting portion of a case, and connecting a lid to the case to cover an open end of the case, wherein the step of forming the quartz crystal tuning fork base and the first and second quartz crystal tuning fork tines is performed before the step of formin

Abstract: Provided is a pulse modulation circuit capable of generating a pulse modulation signal with a steep rise and a desired pulse width at a desired timing not depending on a transmission signal sequence. In this circuit, a control signal generation unit (110) generates a first control signal if transmission data (S11) is “1” and a second control signal if the transmission data (S11) is “0.” The control signal generation unit (110) controls an oscillator (1200) of an intermittently operating circuit (120) to be at an oscillation state for outputting a desired first oscillation signal while the first control signal is turned ON and controls the oscillator (1200) to be at an idling state for outputting a second oscillation signal having a lower amplitude than the first oscillation signal while the second control signal is turned ON.

Abstract: A time period control unit controls a time length “TU” of each of unit terms “U” in a variable manner. A pulse-width modulating unit is arranged by a holding unit, a counting unit, and a waveform generating unit. The holding unit holds thereinto a plurality of data “XD” every unit term “U”, which are sequentially supplied, as data “XE.” The counting unit changes a count value “X” during each of the unit terms “U.” The waveform generating unit generates such a pulse-width modulating signal “S” that pulses “P” have been arranged every unit term “U”, while time points when a large/small relationship between the count value “C” and a numeral value of the data “XE” held by the holding unit is inverted are defined as edge portions of the pulses.

Abstract: An electronic pulse-generating device (100) includes an input circuit (10) and an output circuit (20). The input circuit includes an input connector (11), a first resistor (R1) and a capacitor (12). The capacitor has one lead electronically connected to the input connector and another lead electronically connected to the first resistor. The output circuit includes a transistor (21) and an output connector (22) electronically connected to a collector of the transistor. The first resistor is connected to a base of the transistor, and an emitter of the transistor is grounded.

Abstract: A random number generator. The random number generator includes a noise source, a circuit controlling random current consumption, and a circuit generating random bits. A noise voltage output from the noise source drives the circuit controlling random current consumption, which also generates a random control signal. The circuit generating random bits also includes a voltage-controlled oscillator, a plurality of frequency dividers, and a plurality of flip-flops. The voltage-controlled oscillator is controlled by both the noise voltage and the random control signal. The output of the voltage-controlled oscillator is input to the frequency dividers and the flip-flops to generate a random number.

Abstract: There is provided a control circuit of a switch mode power supply including a random number generator configured to form an optimized n-degree polynomial based on the minimum power-on cycle time in order to form a uniform distribution of output signals, a switch control block configured to control output signals of the switch control block such that the complementary output stages of the switch control block conduct at different times on the basis of the output signals received from the random number generator and a dither control block configured to generate a synchronized dither current by minimizing glitches at each differential stage of a default reference current based on the output signals received from the switch control block, and to combine the generated synchronized dither current with a reference current of a voltage ramp generator.

Abstract: A common voltage generating circuit includes a square wave generating unit, a diode, a NOT gate, a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor, and an output terminal. The square wave generating unit includes an output terminal, which is coupled to the output terminal of the common voltage generating circuit via the first resistor, a positive terminal of the diode, a negative terminal of the diode, and the second resistor in series. The output terminal of the square wave generating unit is coupled to the negative terminal of the diode via the NOT gate and the first capacitor. The positive terminal of the diode is grounded via the second capacitor, and the output terminal of the common voltage generating circuit is grounded via the third capacitor. A duty ratio of the output square wave generating unit is capable of being modulated.

Abstract: A random clock generator for a spread spectrum modulating device includes a random number generator for generating a plurality of random number signals according to a first square wave signal and a control signal, a reference wave generator coupled to the random number generator for generating a triangular signal and a second square wave signal according to the plurality of random number signals, and a trigger signal generator coupled to the random number generator and the reference wave generator, for generating the first square wave signal according to the second square wave signal.

Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).

Abstract: A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a time-varying duty-cycle value. The programmable modulator may comprise a first circuit, called a period modulation circuit, that generates a time-varying digital period value, and a second circuit, called a duty-cycle modulation circuit, that generates a time-varying digital duty-cycle value. The time-varying period values and time-varying duty cycle values are processed to produce a digital edge position value that specifies an edge position for a clock signal.

Abstract: Apparatuses and methods comprise a phase shifter, an adjustable capacitance configured to adjust a phase shift of said phase shifter, an arbitrary waveform generator configured to adjust the adjustable capacitance, and a pulse pattern generator coupled to the phase shifter, the phase shifter is configured to control the pulse pattern generator. In one aspect, an adjustable capacitance is at least one varactor diode. In another, a pair of varactor diodes are separated by ?/4 lines, an input and an output of the adjustable capacitance is AC-coupled, and the arbitrary waveform generator is configured to adjust the adjustable capacitance through a gaussian noise signal input to the pair of varactor diodes. A deterministic jitter generator may be coupled to the pulse pattern generator. An open-circuited stub line may be input to the pattern generator, a deterministic jitter content number adjustable varying stub line length.

Abstract: A random signal generator circuit includes a thermal noise generator circuit and a self-biased inverter having an input coupled to the thermal noise generator circuit and to a feedback resistor coupled to an output of the self-biased inverter, the self-biased inverter configured to produce a sensed noise signal at the output responsive to thermal noise generated by the thermal noise generator circuit. An amplifier circuit is coupled to the output of the self-biased inverter and configured to amplify the sensed noise signal to produce a saturated random signal. The saturate random signal may be sampled, e.g., with a flip-flop, to generate a random binary signal that may be used for random number generation.

Abstract: A waveform generator for generating a desired waveform is provided, including a noise kernel configured to store a plurality of samples from a predetermined waveform, the plurality of samples being assigned to a plurality of memory blocks; and an address arrangement configured to randomly select a selected one of the plurality of memory blocks; wherein the noise kernel is configured to communicate the plurality of samples assigned to the selected memory block.

Abstract: A waveform generator includes a plurality of delay elements such as in a delay line circuit of a free-running oscillator, phase locked loop (PLL) circuit or delay locked loop (DLL) circuit, an algebra module, a switching module and an output module. The oscillator includes a plurality of delay elements and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module includes an algebra data input port, a clock input port and an algebra data output port. The algebra module generates a signal at the algebra data output port indicating a first rising edge of the arbitrary waveform in response to a signal received at the algebra data input port. The switching module includes a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication oscillator taps and switch output port.