Abstract: This invention relates to an electrical device for generating a multi-rate pseudo random noise (PN) sequence comprising sequence generation means adapted to output a plurality of sequence values on the basis of a step control signal (St), said device further comprising selection means adapted to select one of said plurality of sequence values on the basis of a select value (Mt), and step control means adapted to provide said step control signal (St).

Abstract: A waveform generator for generating a waveform in a dual mode wireless device includes a first waveform generator portion (106) and a second waveform generator portion (108). The first waveform generator portion includes a first register (86) connected in series with a second register (84) and a first feedback selector (88), and the second waveform generator portion includes a third register (102) connected in series with a fourth register (100) and a second feedback selector (104).

Abstract: An apparatus having a white noise source which is coupled to a gain stage having an amplifier. The gain stage is coupled to a noise shaping stage which is also coupled to a decision circuit. Another apparatus having a white noise source which is differentially coupled to a gain stage that has a cascade of open loop amplifiers. The gain stage is differentially coupled to a noise shaping stage which is also differentially coupled to a decision circuit. A method that involves differentially coupling white noise into a gain stage. The white noise is differentially amplified with an amplifier which produces a first white noise signal. 1/f noise and offset voltage is substantially removed from said first white noise signal to produce a second white noise signal. A random sequence signal is produced by deciding whether the second white noise signal is a 1 or 0.

Abstract: An improved chopper stabilized operational amplifier is disclosed, along with an improved method of timing the switchings of chopper switches in such an amplifier. The disclosure includes an integrated circuit and method for generating a true random voltage signal having a truly random RMS voltage value within a selected range. The true random voltage signal is obtained by amplifying and bandpass filtering random white noise voltages generated by a component of the circuit. The white noise voltages include shot noise voltages generated by bipolar transistors in an input amplifier stage. The random signal generator circuit and method is employed with an oscillator to form a random clock signal generator on the integrated circuit chip. The amount of time between each clocking pulse output by the random clock signal generator truly randomly varies within a selected range of time, and repeats only by random chance.

Abstract: A phase-enable circuit clocks a first functional unit at a first frequency and a second functional unit at a second frequency. Each of the first and second functional units is provided with a first clock signal of the first frequency. A phase-enable generator then uses the first clock signal and a second clock signal of a second frequency lower than the first frequency to develop a phase-enable signal that periodically disables a clock input terminal of the second functional unit so that the second functional unit is clocked at the second frequency. Changing the frequency of the second clock to zero switches the phase-enable circuit into another mode of operation. In that mode, the clock input terminal of the second functional unit is constantly enabled and the first and second functional units are each clocked at the first frequency.

Abstract: A pseudo-random noise series generator which can change the timing of generation of a PN series arbitrarily and with no instantaneous cut-off of the output. At the time of system start, the whole period or a certain beginning length of a PN series generated by a tapped shift register is stored into a RAM. The stored PN series is output from a position designated by an address signal. An address generator for generating the address signal on an externally applied timing control signal increments an address by one for each step from an initial value set by the timing control signal. In the case where a new timing different from the old timing is set by the timing control signal, the address is incremented or decremented instantaneously by a difference between the old timing and the new timing and a normal incrementing operation is thereafter started again.

Abstract: A chopper stabilized operational amplifier implemented on a single integrated circuit chip is disclosed. The disclosure includes a symmetrical random signal generator circuit that produces a true random voltage signal upon application of a DC bias current. The true random voltage signal is obtained by amplifying and bandpass filtering random white noise voltages generated by a component on the chip. The random signal generator circuit is employed with a symmetrical oscillator to form a random clock signal generator on the same chip. The amount of time between each clocking pulse output by the random clock signal generator randomly varies within a selected range of time. The random clock signal generator is used to control the amount of time between each switching of a chopper switch in the chopper-stabilized operational amplifier, so that the chopping frequency is truly random.

Abstract: An inventive pulse driver transmits a pulse signal in a high speed when the pulse signal is coupled thereto. For the purpose, the pulse driver comprises a first and a second CMOS inverters connected in series, a first inverting delay unit for delaying and phase-shifting an input signal coupled to the first CMOS inverter, a first regulating device, connected to an output terminal of the first CMOS inverter, for adjusting the output signal of the first CMOS inverter in response to an output signal of the first inverting delay unit, a second inverting delay unit for delaying and phase-shifting a signal which is outputted from the first CMOS inverter and inputted to the second CMOS inverter and a second regulating device, connected to the output terminal of the second CMOS inverter, for adjusting the output signal of the second CMOS inverter responsive to an output signal of the second inverting delay unit.

Abstract: A pseudo random pulse generator that creates a series of pulses having randomly separated intervals is described. A pseudo random pulse generator has a pseudo random number generator create a series of pseudo random binary numbers. An enable input initiates creating the series of pseudo random binary numbers and a clock input is connected to a clock signal that synchronizes creating the series of pseudo random binary numbers. A hold input prevents the generation of the pseudo random binary numbers. The pseudo random pulse generator has an interval selector to select one of a plurality of timing signals. Each timing signal is a power of two frequency division of the clock. The interval selector has select signal terminals to select one of the plurality of timing signals, and a trigger output to hold a selected timing signal. The pseudo random pulse generator further has a select buffer connected to a low order digits of the pseudo random number generator.

Abstract: Generating a clock signal having a desired frequency is accomplished by generating a pulse each time a stored accumulator value is found to be greater than or equal to a stored trigger value The seored accumulator value is incremented by a first iterative value n (r) until the stored accumulator value is greater than or equal to the stored trigger value. Subsequently, the stored accumulator value is decremented by a second iterative value until the stored accumulator value is less than the stored trigger value. During each iteration incrementing the stored accumulator value, a current frequency of the clock spinal is compared to a desired frequency value, and if the two values are different, the first iterative value (r) is corrected by a predetermined rate over one or more subsequent iterations until the frequency of the generator clock signal corresponds to the detected value of the desired frequency.

Abstract: A method and apparatus for sequencing an integrated circuit which receives an external clock signal consists of the use of an internally generated random clock signal and of the use of either of these clock signals depending on the instruction to be performed.

Abstract: An improved chopper stabilized operational amplifier is disclosed, along with an improved method of timing the switchings of chopper switches in such an amplifier. The disclosure includes an integrated circuit and method for generating a true random voltage signal having a truly random RMS voltage value within a selected range. The true random voltage signal is obtained by amplifying and bandpass filtering random white noise voltages generated by a component of the circuit. The white noise voltages include shot noise voltages generated by bipolar transistors in an input amplifier stage. The random signal generator circuit and method is employed with an oscillator to form a random clock signal generator on the integrated circuit chip. The amount of time between each clocking pulse output by the random clock signal generator truly randomly varies within a selected range of time, and repeats only by random chance.

Abstract: A timing generating circuit formed as an LSI of CMOS.FETs is provided which enables correction of the variations of delay amount caused by the heat generated in the CMOS.FETs due to the propagation of pulses through the CMOS.FETs. A sub delay element 22 is connected in series to a main delay element 21 in which a timing is set and placed in the vicinity of the element 21. Both delay elements are connected in the same cell structure and arrangement. The sum of initial values of the delay amounts of respective delay elements is made to be a constant value. An input pulse to the main delay element is also supplied to a reference signal generator part 27 which outputs a reference signal using a reference clock after the lapse of the constant value from the time the input pulse is inputted. A time difference between this reference signal and the output from the sub delay element 22 is detected by a time difference detection part 29.

Abstract: A low noise clock oscillator in modular form to plug into a standard 14 or 8 pin DIP clock oscillator socket on the motherboard of a host device to retrofit the host device without redesign of the host device motherboard so that the host device can reduce its EMC emissions sufficiently to pass EMC emission tests. The oscillator is characterized by use of a spread spectrum clock generator, EMC filters between the clock generator and the Vcc, ground and clock bus coupling points to the motherboard and a single point ground connection to the motherboard. This oscillator module allows an easy retrofit to a host device that has already been designed to substantially lower EMC emissions that can be traced to the clock by as much as 20 dB without expensive, time consuming redesign efforts to add shielding, more grounds and possibly reroute the motherboard traces.

Abstract: A clock signal providing circuit with enable and pulse generator with enable for use in a block clock circuit of a programmable logic device (PLD), the block clock circuit for allocating multiple clock signals to each macrocell of the PLD. The clock signal providing circuit includes circuitry which functions to change states in response to a pin clock signal when an enable signal is active, and to maintain its current state when the enable signal is inactive. The pulse generator includes circuitry which functions to provide a pulse at a first edge of a pin clock signal if an enable signal remains active from prior to receipt of the first edge of the pin clock signal.

Abstract: A method and circuit spreads the narrow band emitted EMI of a clock signal. A first, high frequency, clock signal is received, for example, from an oscillator. The first clock signal is modulated, to produce a second clock signal, by inverting the first clock signal x times per L transitions of the first clock signal, where x and L are integers and x<L. Each inversion removes one transition of the first clock signal. The modulated clock signal has reduced EMI spectral density and may be utilized as a microprocessor high frequency master clock signal. Significantly, the modulated clock signal is synchronous with the first clock so that other circuitry which synchronizes to the modulated clock signal is also synchronized to the first clock signal clock. If needed by a particular system (e.g.

Abstract: A power short pulse generator for generating a pulse on a rising edge and falling edge of an input signal according to the present invention comprises an input node for receiving the input signal and an output node for supplying an output signal. A first pulldown circuit and a second pulldown circuit are connected in series between the output node and a first supply voltage potential, the first pulldown circuit and the second pulldown circuit each having an input. A third pulldown circuit and a fourth pulldown circuit are connected in series between the output node and the first supply voltage potential, the third pulldown circuit and the fourth pulldown circuit each having an input. A pullup circuit is connected between the output node and a second supply voltage potential, the pullup circuit having an input. A leakage current circuit is connected between the output node and the second supply voltage potential.

Abstract: An architecture and system for the implementation of an all digital frequency synthesizing system is described. The frequency synthesizing system has a count series retention table that contains a series of count integers that are selected by a count signal that chooses which series of the integers are to be linked to a periodic input reference frequency counter. The periodic input reference frequency counter will count a number of periods of a periodic input reference frequency and when the counter has reached the number of counts that is equal to the number of the count integer, the periodic output frequency will be toggled from logic level to another logic level. A new periodic output frequency period can be chosen by selecting a new series of count integers in the count retention table. This architecture is structured such that it can be implemented in an automated logic design system.

Abstract: In a variable delay circuit for delaying an input signal by a variable delay time from a rising edge or a falling edge of the input signal to a rising edge or a falling edge of an output signal in a digital circuit, a data signal input terminal; a first signal input terminal to which a low-level signal of a logic gate is applied; n selector circuits (n=integer larger than 0) selecting either the signal at the data signal input terminal or the signal at the first signal input terminal in response to signals applied to first selector signal input terminals; and an (n+1)-input NOR circuit to which the signal at the data signal input terminal and output signals from the selector circuits are applied. In this variable delay circuit, a delay time shorter than the delay time of a single-stage buffer circuit can be controlled using only digital circuits.

Abstract: In order to sample high-frequency signals, it is necessary to have a needle pulse train and a needle pulse train which is inverted with respect thereto. By means of a switch (T) which is controlled by a clock signal (U), a positive operating voltage (U.sub.B+) is applied for a limited period of time to a first conductor (L.sub.1) and a negative operating voltage (U.sub.B-) is applied for a limited period of time to a second conductor (L.sub.2). The two conductors (L.sub.1, L.sub.2) are connected via a respective diode (D.sub.1, D.sub.2), which are biased differently, to a respective resistor (RV.sub.1, RV.sub.2), which is connected to ground, and to a respective capacitor (C.sub.1, C.sub.2). The respective capacitors connected to a respective further resistors (RL.sub.1, RL.sub.2), which is connected to ground, the needle pulse train being present at one resistor and the needle pulse train which is inverted with respect to the first being present at the other resistor.

Abstract: A phase-to-frequency converter uses a triangular waveform synthesizer to generate a triangular wave using both PDM and a DC modulation scheme. A 4-bit PDM and associated logic generates the PDM output waveform with polarity information and two switching waveforms that encode the DC level information to provide a resultant sum. The resulting waveform, after filtering, is the multiple phases of the triangular waveform. The generated multiple phases of the triangular wave are then modified by reducing the ramp rate at appropriate points to suppress the third harmonic and its multiples. The ramp rate is proportional to the pulse density output of the Pulse Density Modulator. In one embodiment, the rate of the PDM output is reduced by one half during appropriate periods by gating the output by its clock, thereby reducing its density by one half during those periods.

Abstract: A feedback shift register for generating digital signals representing pseudo-random number sequences has n-stages and exclusive OR-circuits in the feedback logic, as well as a clock-pulse generator. To be able to generate digital signals, which are well suited for a further digital processing, the clock-pulse generator (17) is linked with the n-stages (11, 12, 13, 14, 15) of the shift register (10) via a controllable gate circuit (18), which blocks one clock pulse of 2.sup.n clock pulses (CLK) of the clock-pulse generator (17) in each case.

Abstract: A digital controller provides digital signals to audio modules; the digital signals include both clock signals and data. All of the logic circuits of the controller and of the modules are clocked on the receipt of a rising edge. However, to avoid interference from regular clock pulses, the clock pulses are altered to have a variable mark-space ratio which means that the clock pulses arrive at random times and have random widths and thus appear to be randomized. Use of randomized clock signals can avoid tones appearing in an audio system, and also avoids interference effects in other electrical systems. The use of randomized clock signals is particularly helpful when designing digital circuits which meet current regulations controlling electromagnetic emissions.

Abstract: An oscillator generates a signal that is applied to one input of a phase shifter circuit. The other input of the phase shifter is connected to a source of a phase modulation signal. In response to the phase modulationsignal, the phase shifter provides a clock signal with a spread spectrum.

Abstract: A system for storing an arbitrary waveform on non-volatile random access ory (NVRAM) device and generating an analog signal using the NVRAM device. A central processing unit is used to synthesize an arbitrary waveform and create a digital representation of the waveform and transfer the digital representation to a microprocessor which, in turn, writes the digital data into an NVRAM device which has been mapped into a portion of the microprocessor address space. The NVRAM device is removed address space and placed into an independent waveform generation unit. In the waveform generation unit, an address clock provides an address timing signal and a cycle clock provides a transmit signal. Both signals are applied to an address generator. When both signals are present, the address generator generates and transmits to the NVRAM device a new address for each cycle of the address timing signal.

Abstract: Adaptive clock generator including a master clock. A control means detects the current operating mode and, in response, provides a corresponding integer output N. A programmable pulse generator provides an output clock signal comprising a "high" pulse having a predetermined width followed by a "low" pulse having a width of N master clock periods. A dithered clock signal may be provided when the control means provides an integer output N selected from a set of integer values. Preferably, N is selected in a random or pseudo-random manner.