Abstract: The present invention discloses a clock generator circuit for generating an output clock signal. The clock generator circuit includes: a random frequency code generator for generating a frequency code randomly, wherein the random frequency code generator is clocked by a first clock signal; an accumulator electrically connected to the random frequency code generator, for generating a selection code by accumulating the frequency code, wherein the accumulator is clocked by the first clock signal; a first multiplexer electrically connected to the accumulator, for selecting one of a plurality of reference clock signals as the first clock signal according to the selection code; and a toggle circuit electrically connected to the first multiplexer, being clocked by the first clock signal for generating the output clock signal.

Abstract: A multiphase resonant pulse generator (74) has N groups of N?1 switches (44,46,48) which, when activated, form N paths from a power supply (Vdc) to ground or a reference voltage. Here N is a positive integer greater than 2. Each of the paths includes an inductance (38,40,42) and N?1 switches. The signal outputs (X1,X2,X3) from each of the N paths are cross coupled to switches belonging to the other N?1 paths to active or deactivate the groups of switches.

Abstract: A method and apparatus are described. The method comprises generating a clock signal comprising regularly spaced clock-timing transitions between a signal high and a signal low to provide timing for a circuit coupled to the clock signal, and periodicity-disrupting transitions between the signal high and signal low, randomly inserted between the clock-timing transitions to disrupt a periodicity of the regularly spaced clock-timing transitions; and transmitting the clock signal to the circuit.

Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).

Abstract: A waveform generator includes a plurality of delay elements such as in a delay line circuit of a free-running oscillator, phase locked loop (PLL) circuit or delay locked loop (DLL) circuit, an algebra module, a switching module and an output module. The oscillator includes a plurality of delay elements and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module includes an algebra data input port, a clock input port and an algebra data output port. The algebra module generates a signal at the algebra data output port indicating a first rising edge of the arbitrary waveform in response to a signal received at the algebra data input port. The switching module includes a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication oscillator taps and switch output port.

Abstract: A transmission circuit includes a baseband circuit, spreading section, multiplier, digital modulator, quadrature modulator, and antenna. The baseband circuit generates and outputs at least one transmission data constituted by first and second channel data. The spreading section spreads the transmission data with a spreading code that differs for each transmission channel. The multiplier respectively weights the amplitudes of the first and second channel data by using a combination of two gain factors determined by a transmission data rate. The digital modulator digitally modulates the first and second channel data whose amplitudes are weighted by the multiplier. The quadrature modulator quadrature-modulates the digitally modulated first and second channel data and outputs the data as a transmission signal. The antenna emits the transmission signal output from the quadrature modulator as a radio wave.

Abstract: A method for assigning codes in an uplink of a synchronous code division multiple access (CDMA) telecommunication system is disclosed. The method for assigning a code in a reverse channel of a synchronous wireless telecommunication system, comprising the steps of: a) at a mobile station, receiving time matching information of a scrambling code from a base station; b) at the mobile station, spreading data frame to be transmitted by an orthogonal code, thereby generating a spread data; and c) at the mobile station, multiplying the spread data by a scrambling code based on the time matching information of the scrambling code, thereby generating an encoded data.

Abstract: A pulse modulator comprises a delay arrangement for receiving a first sequence of pulses and for delaying each received pulse several times to obtain a plurality of sequences of pulses having different phases. The pulse modulator further comprises a selection component for receiving from the delay arrangement a plurality of sequences of pulses having different phases, for receiving a modulating signal, wherein each possible value of the modulating signal is associated to one of the different phases, for selecting for each pulse of the first sequence of pulses a pulse of the respective sequence of pulses which sequence of pulses has a phase associated to a current value of the modulating signal, and for outputting the selected pulse as part of a pulse position modulated sequence of pulses. The invention relates equally to a modulating system comprising such a phase modulator and to a corresponding method.

Abstract: A spreading system according to an embodiment of the invention spreads two data signals. The system produces a filtered signal that is based on one of the data signals and an output signal that is based on both of the data signals. In one example, a spreading system is used to perform QPSK spreading of two data signals, including separate processing of the two data signals, in a practical manner. Such separate control may include filtering and/or gain control.

Abstract: An automatic gain control circuit (3) for a direct sequence spread spectrum receiver. A discrimination unit (10) generates a discrimination signal error from received in-phase and quadrature base band signals, whilst multiplication unit (16) multiplies the discrimination signal error by a first loop gain constant during signal acquisition and a second different loop gain constant during signal tracking. A recursive integrator (22) then acquires an integrated AGC value from the multiplied discrimination signal error. By using two different values of loop gain, the circuit is able to alternate between a “fast mode” during signal acquisition, and a “slow track” mode during signal tracking.

Abstract: A DC—DC converter includes a variable frequency oscillator, a control system and a power train. The DC—DC converter is well suited for use in a cell phone. The control system uses the output of the oscillator to control the power train. The oscillator varies its frequency as a function of a pseudo random number generator, thereby reducing electromagnetic interference caused by ripple in the output of the DC—DC converter.

Abstract: A signal generator (10). The signal generator comprises circuitry (20) for producing at least a first input noise signal (N1), wherein the first input noise signal has a statistically insignificant autocorrelation.

Abstract: An output cycle of a pulse string generated from a pulse generating section (2) is divided by a pulse dividing section (3) and a signal having a cycle which is plural times as great as the cycle of an output pulse is output from the pulse dividing section (3). This signal is input as an interruption request signal to a CPU (1). Consequently, the CPU (1) can execute an interruption processing in a cycle which is plural times as great as the cycle of the output pulse. By the interruption processing, the number of pulses to be output is controlled.

Abstract: An integrated semiconductor circuit having a number of circuit units which are driven by a clock signal and can be operated both in parallel and in series is provided. A connection supplying the clock signal is connected to the clock input of the respective circuit units via respective controllable switching devices. The control inputs of the switching devices are connected to an output of a random signal generator, so that a circuit unit is operated in parallel or in series with one or more of the other circuit units on the basis of the random signal. A method of operating an integrated semiconductor circuit is also provided.

Abstract: A device generating a pulse signal includes at least one first register which stores waveform data therein, a pulse signal generation unit which generates a pulse signal in accordance with the waveform data of the first register, a control unit which is connected to a bus, and is controlled by control signals supplied from the bus, and a signal line which is separate from and independent of the bus, and is connected to the control unit, wherein the control unit updates the waveform data of the first register in response to a signal that is externally supplied through the signal line.

Abstract: A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

Abstract: A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the buffer. An elementary cell is based on the pulse shaper and a timing circuit which gates the output of an integrator connected to the pulse shaper output. A detector readout system is formed of a plurality of elementary cells, each connected to a pixel of a pixel array, or to a microstrip of a plurality of microstrips, or to a detector segment.

Abstract: A physical random number generator has a bi-stable latch that operates to latch a random number bit in response to a reception of a voltage oscillating signal. When a switching device is in a first operating state, the bi-stable latch is deactivated and an oscillator is activated to generate one or more unpredictable voltage oscillation signals, which may provoke the bi-stable latch into a metastable state upon an activation of the bi-stable latch. When the switching device is in a second operating state, the oscillator is deactivated and the bi-stable latch is activated to latch a random number bit as a function of the unpredictable voltage oscillation signals, the randomness of the random number bit being enhanced by any provoking of the bi-stable latch into the metastable state by the voltage oscillating signal(s).

Abstract: A clock and data recovery circuit includes a phase-shift circuit having a switch, which receives multiphase clocks, for selecting and outputting a plurality of clock pairs from among the multiphase clocks, and a plurality of interpolators, which receive the plurality of clock pairs output from the switch, for outputting clock signals in which delay time is stipulated by time obtained by performing interior division of the phase difference between the clocks of the pair; a plurality of latch circuits which receive input data in common; a phase detecting circuit for detecting and outputting phase, with respect to the clock, of a transition point of the input data from the outputs of the plurality of latch circuits; a filter for smoothing the output of the phase detecting circuit; and a control circuit for controlling clock phase by outputting control signals for controlling the interpolators and/or switch of the phase-shift circuit based upon the filter output.

Abstract: A pulse generator. The pulse generator has a pseudo random number generator, a comparator coupled to the pseudo random number generator, and a register coupled comparator. The comparator performs comparisons of values generated by the pseudo random number generator and a value in the register, wherein the comparator outputs a pulse that is modulated according to the comparison. A low-pass filter may coupled to the comparator output and the register may receive samples of a digital signal. Low-pass filtering the comparator output implements a digital-to-analog converter that is less expensive than conventional delta-sigma modulator DACs and has better performance than conventional PWM DACs.

Abstract: A random number generator comprising a counter circuit configured to be supplied with a clock signal and a random signal, and to provide a count value of the clock signal with respect to a transition of the random signal, and a first latch circuit configured to latch the count value with respect to the transition of the random signal, and to provide a first random number signal.

Abstract: A one-shot circuit provides a pulse on receipt of a first edge, and removes the pulse after a delay generated by a delay chain. However, a second, opposite edge resets the circuit without an intervening delay chain delay. The delay chain can be implemented using a chain of AND circuits (one-shot high) or OR circuits (one-shot low), each driven by the preceding circuit in the chain and by the input signal. In some embodiments, an output circuit includes a pass gate coupled between the one-shot input and output terminals and a pulldown (one-shot high) or pullup (one-shot low) that provides an inactive value when the pulse is not being applied. The pass gate and pullup or pulldown are controlled by the output of the daisy chain. Other embodiments offer programmable capabilities, such as the ability to correct for process shift by altering the effective delay of the delay chain.

Abstract: A frequency to frequency de-randomizer circuit having means for smoothing a current which comprises a diode filter configured so as to have a time constant which changes in response to changes in the current thus providing a rapidly responding, real time, fluctuation free signal which is optimised for measurement and display from a very low power circuit.

Abstract: A physical random number generator has a bi-stable latch that operates to latch a random number bit in response to a reception of a voltage oscillating signal. When a switching device is in a first operating state, the bi-stable latch is deactivated and an oscillator is activated to generate one or more unpredictable voltage oscillation signals, which may provoke the bi-stable latch into a metastable state upon an activation of the bi-stable latch. When the switching device is in a second operating state, the oscillator is deactivated and the bi-stable latch is activated to latch a random number bit as a function of the unpredictable voltage oscillation signals, the randomness of the random number bit being enhanced by any provoking of the bi-stable latch into the metastable state by the voltage oscillating signal(s).

Abstract: A random number generator on an integrated circuit has a first clock generator circuit with a first voltage supply for generating a first signal of a first frequency or of a first frequency range. A second clock generator circuit has a second voltage supply for generating a second signal of a second frequency or of a second frequency range, such that the second frequency or a mean value of the second frequency range is lower than the first frequency. A generator samples the first signal with the second signal and-generates at least one random number in dependence on the result of the sampling. The clock generator circuits are located as far away from one another as possible on the integrated circuit and/or the two voltage supplies are isolated from one another and/or at least one guard ring is placed around each of the clock generator circuits.

Abstract: The waveform generator includes a free-running ring oscillator, an algebra module, a switching module and an output module. The free-running ring oscillator includes a plurality of delay elements connected in a loop and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module generates an output signal indicating a first rising edge of the arbitrary waveform in response to an input signal. The switching module includes a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication with the free-running ring oscillator taps and switch output port. At the switch output port, the switch module provides a first transition signal selected from one of the plurality of free-running ring oscillator taps in response to the signal indicative of a first rising edge received at the switch input port.

Abstract: A pulse generation circuit delivers an output pulse whose width is tailored to the load. The pulse generation circuit comprises the following components. A drive circuit has an input coupled to receive a clock signal and an output coupled to drive a load. A comparator has an input coupled to the output of the drive circuit. Another input of the comparator is supplied by a reference voltage. A feedback circuit comprises logic gates and is coupled between the output of the comparator and the input of the drive circuit. The feedback circuit terminates a pulse output from the drive circuit when the pulse voltage output from the drive circuit exceeds the reference voltage. The reference voltage is higher than a voltage required to trigger the logic gates and a voltage required to drive the load. This ensures that the load is driven adequately over a wide range of load currents and capacitances.

Abstract: A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

Abstract: A random signal generator (1) has at least two functional groups (2a, 2b, 2c) each of them having one random sequence generators (3a, 3b, 3c), one exclusive-or gate (4a, 4b, 4c) and one memory element (5a, 5b, 5c). One of the two inputs (6a, 6b, 6c) of the exclusive-or gate (4a, 4b, 4c) of each functional group (2a, 2b, 2c) is connected to a random sequence signal output (7a, 7b, 7c) of the random sequence generator (3a, 3b, 3c) of the functional group (2a, 2b, 2c) and the other input (8a, 8b, 8c) to a data output (9a, 9b, 9c) of the memory element (5a, 5b, 5c) of the functional group (2a, 2b, 2c). The output (10a, 10b, 10c) of the exclusive-or gate (4a, 4b, 4c) of each functional group (2a, 2b, 2c) is connected to the data input (11a, 11b, 11c) of the memory element (5a, 5b, 4c) of the functional group (2a, 2b, 2c). The memory elements (5a, 5b, 5c) of the functional groups (2a, 2b, 2c) are connected to one another via data lines (13) for the purpose of shifting their memory contents.

Abstract: A random number generator has a simple configuration using known inexpensive electronic parts and can generate the tine physical random numbers at a required generator speed. Such a random number generator can provide the true physical random numbers to any sectors of society at dramatically low cost A random pulse generator comprises a thermal noise generating element (2) having a resistor, a conductor or a semiconductor such as a diode adapted to generate thermal noises when no electric current is supplied to them, an analog-amplifier circuit for amplifying the irregular potential generated from the thermal noise generating element and a waveform shaping circuit (6) adapted to take out the output of the amplifier circuit as random rectangular pulse signals.

Abstract: In a telecommunication system where a plurality of user channels are processed in a time-slotted manner, a transmitter and receiver can perform bit error rate measurements for a plurality of user channels by only using one PN-generator (T-PN) and one state memory (ISM). Whenever the beginning of a new time-slot is detected, a last-stored phase state is read out from the state memory (ISM). When detecting the end of the respective time-slot, the phase state then present in the PN-generator (T-PN) is stored into the state memory (ISM) to be used for re-initialization of the PN-generator (T-PN) for the same time-slot in a succeeding frame. Thus, one PN-generator (T-PN) is enough for generating PN-sequences for a great number of user channels.

Abstract: One embodiment of the present invention provides a system for generating a pseudo-random non-periodic digital sequence. The system operates by receiving a non-periodic signal at a data input of a flip-flop. This non-periodic signal is sampled at the flip-flop with a clock signal, thereby producing the pseudo-random non-periodic digital sequence at the output of the flip-flop.

Abstract: One embodiment of the present invention provides a system for generating a pseudo-random non-periodic digital sequence. The system operates by receiving a non-periodic signal at a data input of a flip-flop. This non-periodic signal is sampled at the flip-flop with a clock signal, thereby producing the pseudo-random non-periodic digital sequence at the output of the flip-flop.

Abstract: A random number generator has a simple configuration using know inexpensive electronic parts and can generate the true physical random numbers at a required generation speed. Such a random number generator can provide the true physical random numbers to any sectors of society at dramatically low cost A random pulse generator comprises a thermal noise generating element (2) having a resistor, a conductor or a semiconductor such as a diode adapted to generate thermal noises Hen no electric current is supplied to them, an analog-amplifier circuit for amplifying the irregular potential generated from the thermal noise generating element and a waveform shaping circuit (6) adapted to take out the output of the amplifier circuit as random rectangular pulse signals.

Abstract: In a control system, with a defined clock rate C—a method and apparatus for generating a train of pulses whose mean level is proportional to a given number V, having N equispaced possible values, the pulses to be applied to a given low-pass process, the method comprising generating a train of constant-amplitude pulses at a rate that is considerably greater than C/N, when the width of each pulse is an integer multiple of a clock period, 1/C, and the widths of all pulses are not necessarily equal.

Abstract: A hardware-based random number generator is provided for incorporation within an integrated circuit. The apparatus has a first variable frequency oscillator, a second variable frequency oscillator, and a variable bias generator. The first variable frequency oscillator generates a first oscillatory signal at a first frequency. The a second variable frequency oscillator generates a second oscillatory signal that is asynchronous to the first oscillatory signal and has a second frequency less than the first frequency, where bits of the random number are configured from samples of the first oscillatory signal taken at the second frequency. The variable bias generator is coupled to the first and second variable frequency oscillators, and generates an analog bias signal. The first and second frequencies vary according to the analog bias signal, and the analog bias signal varies based upon logic states of a plurality of bits of the random number.

Abstract: Disclosed herein are circuits in which a plurality of clock signals are generated by corresponding clock generators from one or more common clock references. The clock generators accept control values that specify the phases of the individual clocks. The actual phase of each clock signal potentially varies during operation, and the phases of the various clock signal are generally independent of each other. To detect or measure phase relationships, the disclosed circuits evaluate or compare the control values using arithmetic logic.

Abstract: An improved random number generator for micro-controllers is provided with multiple free running oscillators. These oscillators may be ring oscillators. They run at different frequencies. A phase difference between at least two of the oscillators provides the random number. The determination of a phase difference can be done by sampling the high speed oscillator using the lower speed oscillator. This sampling of the oscillators for the determination of a phase difference can be controlled by an oscillators as well. The random number is picked up from a shift register which provides feedback to a control circuit which can alter the frequency of one or more (including all) of the oscillators so that an increased randomness can be achieved. The random number from the shift register is loaded into a linear feedback shift register (LFSR) to generate independent uniform random data.

Abstract: What is disclosed is a system and method of generating a random frequency. First a fundamental noise signal from a fundamental noise source is detected. Then the fundamental noise signal is amplified. The amplified fundamental noise signal is then mixed with an oscillator signal. For one embodiment, the system is carried out in a single integrated circuit.

Abstract: A semiconductor device according to the invention is composed of a counter which outputs intermediate carry signals (CARRY 0, 1, 2) and the final carry signal (CARRY END) for determining the end of a delay output signal in a period starting from a delay pulse-generating trigger signal (DPT) and continuing for a predetermined time, and a delay circuit which outputs count up signals (COUNT UP) for counting up the counter on the basis of pulse signals generated in accordance with the intermediate carry signals and the DPT. According to the aforementioned semiconductor device, the delay output signal can be outputted without using an external clock signal.

Abstract: In the process for converting a frequency signal to a DC voltage according to the invention a first and a second output voltage signal (UA1, UA2) are generated from the frequency signal. Each of the output voltage signals is a sequence of rectangular pulses the pulse sequence frequency of which is equal to a frequency f of the frequency signal. These are converted with a first and a second lowpass filter to a first DC voltage signal and a second DC voltage signal, respectively, with the second DC voltage signal being used to influence the pulse width T0 of the rectangular pulses of at least the first output voltage signal. This makes it possible to build a simple frequency-to-voltage converter using cost-effective standard monoflops in which a largely linear correlation between frequency f of the frequency signal and the magnitude of the first DC voltage signal is realized in a simple manner.

Abstract: An apparatus is described comprising a noise source coupled to an input of a gain stage. The apparatus also includes a noise shaping stage that forms a shaped noise signal by reducing 1/f noise introduced by the gain stage. The noise shaping stage has an input coupled to an output of the gain stage. The apparatus also has a decision circuit that decides whether the shaped noise signal, or a signal derived from the shaped noise signal corresponds to a 1 or a 0. A method is described that amplifies a first noise signal to produce a second noise signal. A shaped noise signal is formed by reducing 1/f noise introduced to the second noise signal by the amplifying. A random sequence is generated by comparing, against a reference, the shaped noise signal or a signal derived from the shaped noise signal.

Abstract: A reset pulse signal generating circuit includes an output node with an output circuit connected thereto that outputs the reset pulse signal, and a first MOS transistor having a first conductivity type connected between a first power supply and the output node. The first MOS transistor is turned on responsive to a write signal. The circuit further includes a second MOS transistor having a second conductivity type connected between the output node and a second power supply, and a power supply transition detector connected to the first and second power supplies and the second MOS transistor. The power supply transition detector outputs a transfer signal having a level determined by a level of the power supplies when the write signal is in an inactive state. The power supply transition detector outputs the transfer signal having a predetermined level when the write signal is in the active state.

Abstract: A method is disclosed including generating a digital control signal having a duty cycle which varies randomly or pseudo-randomly between a number of cycles, and is substantially fixed when averaged over the cycles. A target signal such as a digital clock signal may be passed selectively, in accordance with the control signal. A particular application of the method is power management in computers and other electronic systems that feature high performance processor and memory configurations that involve synchronous accesses of the memory by the processor.

Abstract: The waveform generator includes a free-running ring oscillator, an algebra module, a switching module and an output module. The free-running ring oscillator includes a plurality of delay elements connected in a loop and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module generates an output signal indicating a first rising edge of the arbitrary waveform in response to an input signal. The switching module includes a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication with the free-running ring oscillator taps and switch output port. At the switch output port, the switch module provides a first transition signal selected from one of the plurality of free-running ring oscillator taps in response to the signal indicative of a first rising edge received at the switch input port.

Abstract: The invention provides methods and apparatus for performing RMS-to-DC conversion in which the input signal is sampled using circuitry that includes a clock signal. The clock signal is dithered, however, to account for various problems that may occur, such as aliasing. The dithering may occur during the sampling prior to the conversion, such as when the input signal is converted to a digital signal prior to the conversion. Alternately, the dithering may occur as part of the RMS-to-DC conversion.

Abstract: A dual mode wireless device in which a coefficient generator (42) generates parameter values for a GSM waveform, based on transmitted sequences of digital data values from a GSM unit (34), using a multiplierless operation, and a waveform generator 44 generating the GSM waveform using the generated parameter values. The coefficient generator includes adder sections (132, 134, 136), each having corresponding adders (142, 144, 146) and multipliers (148, 150, 152), register sections (154, 156, 158), each containing parameters corresponding to a modulator (48), and transmit data registers (TXDATA[5]-TXDATA[0]) sequentially receiving the digital data values from the GSM unit.

Abstract: An apparatus and method for treating exhaust gases. In this apparatus, a plurality of stages of reactor chambers (R1, R2, . . . Rn) are connected in series in the direction of an exhaust gas flow. Further, high-voltage power supplies (V1, V2, . . . and Vn) are connected to the reactor chambers (R1, R2, . . . and Rn), respectively. Moreover, in each of these reactor chambers, a streamer discharger plasma is generated. Furthermore, the more downstream a reactor chamber of a stage is placed, the lower energy to be cast into the reactor chamber becomes. The density of electrons generated in a gas decomposition unit is high in a portion thereof on the upstream side of the exhaust gas flow and the electron density is low in a portion thereof on the downstream side. Additionally, the present invention further provides a pulse generator in which a high voltage, which is an output voltage of a D.C.

Abstract: A technique for modulating and demodulating CPM spread spectrum signals and variations of CPM spread spectrum signals uses a set of codes or multiple sets of codes that reduce cross-correlation interference. A transmitter divides a signal data stream into I and Q data streams, independently modulates the I and Q data streams using CPM or a related technique, and superposes the plurality of resultants for transmission. A receiver receives the superposed spread spectrum signal, simultaneously attempts to correlate for I and Q chip sequences, and interleaves the correlated I and Q data streams into a unified signal data stream. In one embodiment the receiver separates the received spread spectrum signal into real and imaginary parts, attempts to correlate both real and imaginary parts for a plurality of chip sequences, and combines separate correlation signals into a unified signal data stream.

Abstract: An apparatus for correcting imperfectly equalized bipolar signals includes a delay line having a reset control, an AND gate, and a one-shot multivibrator. The apparatus is used in conjunction with an adaptive equalizer with the output of the adaptive equalizer being coupled to the input of the apparatus of the invention. More particularly, the output of the equalizer is coupled to the input and reset of the delay as well as to one input of the AND gate. The output of the delay line is coupled to the other input of the AND gate. The output of the AND gate is coupled to the input of the one-shot multivibrator and the output of the one-shot multivibrator is the corrected signal. The delay line is approximately equal to the pulse width of an erroneous pulse which is expected from over-equalization. When the delayed signal is compared to the original signal via the AND gate, narrow pulses are removed from the signal.