Abstract: Apparatus and method for establishing a stable operating point of a H-bridge with a center shunt switch. The stable operating point lets a circuit connected to the H-bridge outputs work in a more ideal condition. As such, an H-bridge with a stable operating point will yield a higher performance and/or save power. Since common mode is one of the biggest sources of electromagnetic interference, a stable operating point in an H-bridge also suppresses EMI.

Abstract: A device monitors a turn-off capability of an electrical load connected to a first current path connected to an external power supply. The first current path includes a first electrical actuating element, the operating state of the first actuating element being characterized by a first electrical quantity, which is a first capacitance resulting in a first voltage. The device includes a second current path including a second actuating element, the operating state of the second actuating element being characterized by a second capacitance resulting in a second voltage. The first capacitance and the second capacitance are connected in series. A control device drives the second actuating element and evaluates values of the first electrical quantity for recognition of a malfunction for the turning-off of the first actuating element. The process includes comparing the values of the first electrical quantity with a preset reference value.

Abstract: A pulsed signal generator generates a pulsed signal having a pulse width configured to be equal to a given fraction of a pulse width of a reference clock. A reference current source outputs current having a reference magnitude, and a comparison current source outputs current having a magnitude that is a function of the reference magnitude and the given fraction. A comparison circuit compares a total current output by one of the reference current source and the comparison current source during pulses of the reference clock to a total current output by the other of the reference current source and the comparison current source during pulses of the pulsed signal equal in number to the pulses of the reference clock in order to determine whether the pulse width of the pulse signal is less than or equal to the given fraction of the pulse width of the reference clock.

Abstract: Techniques are disclosed to allow for a switched capacitor digital power amplifier (PA) that operates using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg.

Abstract: In a transmitter circuit, an impedance calibration circuit is configured to generate an impedance code for impedance matching, an encoder is configured to receive the impedance code and to generate a delay compensation signal based on the impedance code. A delay circuit is configured to output delay data that are delayed from input data by a delay value determined based on the delay compensation signal. A feed-forward equalizer is configured to receive the input data and the delay data, and to equalize the input data based on a main coefficient used for the input data and an equalization coefficient used for the delay data to generate transmission data.

Abstract: An electronic control device includes a receiving unit that receives a data signal from an external device via a transmission line, a determination criterion selection unit that determines a determination criterion based on transition information of a waveform in the data signal, and a condition determination unit that determines a condition of a communication system including the external device, the receiving unit, and the transmission line based on a transmission waveform characteristic in the data signal and the determination criterion.

Abstract: The disclosure provides a digital-to-analog conversion device and an operation method thereof. The digital-to-analog conversion device includes a digital-to-analog conversion circuit and a slew rate enhancement circuit. The digital-to-analog conversion circuit is configured to convert a digital code into an analog voltage. An output terminal of the digital-to-analog conversion circuit outputs the analog voltage to a load circuit. A control terminal of the slew rate enhancement circuit is coupled to the digital-to-analog conversion circuit to receive a control voltage following the analog voltage. The slew rate enhancement circuit is coupled to the output terminal of the digital-to-analog conversion circuit. The slew rate enhancement circuit enhances the slew rate at the output terminal of the digital-to-analog conversion circuit based on the control voltage.

Abstract: The slew rate control circuit includes a slew rate control unit, a capacitive delay unit, a delay unit, a first output unit, a second output unit, and a third output unit. The slew rate control unit is used for receiving a plurality of control voltages. The capacitive delay unit is coupled to the slew rate control unit for receiving an input signal. The delay unit is coupled to the capacitive delay unit. The first output unit and the second output unit are coupled to the capacitive delay unit. The third output unit is coupled to the delay unit. The first output signal and the second output signal are two signals without controllable slew rates. A slew rate of the third output signal is controlled by the capacitive delay unit. A slew rate of the fourth output signal is controlled by the capacitive delay unit and the delay unit.

Abstract: A switching apparatus for electric power distribution grids including: a withdrawable first switching unit having one or more first electric poles; a withdrawable second switching unit having one or more second electric poles and electrically connected ins series with said first switching unit; wherein said second switching unit includes an emergency control arrangement activatable by a user to make said second switching unit to carry out an opening manoeuvre.

Abstract: A drive circuit configured to apply a slew rate controlled drive signal to the control terminal of a power transistor. The drive circuit may be part of a system that includes one or more sub-circuits in which each sub-circuit includes a regulation loop, a matched replica of the power transistor and regulated voltage node. The voltage reference voltage for each sub-circuit connects to the control terminal of the power switch through a buffer circuit to apply a sequence of voltages to the control terminal of the power switch. A switching controller circuit may manage the operation of the one or more sub-circuits so that the drive circuit may output a precisely controlled voltage profile to the control terminal of the power transistor. The circuit may include a second buffer under the control of the switching controller circuit to further manage the operation of the power transistor.

Abstract: An integrated circuit comprises a signal transmitter and a sampling circuit coupled to the signal transmitter, wherein the sampling circuit is to sample output voltage levels of an output of the signal transmitter at different respective times. The integrated circuit further comprises a measurement circuit coupled to the sampling circuit, wherein the measurement circuit is to compare the output voltage levels of the output of the signal transmitter to corresponding reference voltages to identify a first time when a first output voltage level equals a first reference voltage and a second time when a second output voltage level equals a second reference voltage. A time difference between the first time and the second time is used to configure a slew rate adjustment control of the signal transmitter.

Abstract: An apparatus for regulating a slew time of an output voltage of a motor driver system includes a gate current control circuit which has a first input coupled to receive a target slew time and a second input coupled to receive a slew time. The gate current control circuit provides an incremented gate current if the slew time is greater than the target slew time and provides a decremented gate current if the slew time is less than the target slew time. The apparatus includes a gate driver which has a first input coupled to receive a PWM signal and a second input coupled to receive the gate current. The gate driver provides a gate drive signal.

Abstract: A semiconductor device may include one or more output drivers. An output driver may be adjusted for impedance matching by applying a body voltage to one or more transistors of the output driver. In some examples, the body voltage applied may be based on a comparison between a reference voltage and a voltage at an external terminal. In some examples, the semiconductor device may include a calibration circuit that includes a comparator and an up/down counter that, based on a signal from the comparator, generates a code indicating the body voltage to be applied. The body voltage may be applied by a voltage generator in some examples.

Abstract: A post driver and a chip with overdrive capability are shown. A first bias circuit is configured to provide a first voltage shift between the output terminal of the post driver and the gate terminal of the first p-channel metal-oxide-semiconductor (PMOS) transistor of a pull-up circuit when the pull-down circuit is enabled. A second bias circuit is configured to provide a second voltage shift between the output terminal of the post driver and the gate terminal of the first n-channel metal-oxide-semiconductor (NMOS) transistor of the pull-down circuit when the pull-up circuit is enabled. Accordingly, the PMOS transistors in the pull-up circuit and the NMOS transistors in the pull-down circuit are all well protected although they are powered by an overdrive voltage.

Abstract: A drive circuit for a power switching transistor includes a first pull-up drive transistor connected in parallel with a second pull-up drive transistor, a first pull-down drive transistor coupled to the first and second pull-up drive transistors in series to drive the power switching transistor. When control signal is at a high level, the first pull-up driver is turned on, and the first pull-down driver is turned off. The second pull-up drive transistor being in turn-on or turn-off state is determined by comparing voltage of the power supply with the threshold value. When voltage of the power supply is lower than the threshold value, the first and second pull-up drive transistor are driven together. When voltage of the power supply is higher than the threshold value, the second pull-up driving transistor is turned on only after the driving output is slightly larger than the Miller plateau voltage.

Abstract: Circuits and methods that control a rate of change of a drain voltage as a function of time in a transistor are disclosed. In one aspect, the circuit includes a transistor having a gate terminal that controls operation of the transistor, and a control circuit coupled to the gate terminal and arranged to change a voltage at the gate terminal at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and further arranged to change the voltage at the gate terminal at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage, where the first rate is different than the second rate.

Abstract: Disclosed embodiments relate to sensing states and changes of states of a signal and sensors for the same, including but not limited to, autonomous sensors. Such sensor may include an analog signal threshold detection circuit, a state detection circuit, and a measurement circuit. The analog signal threshold detection circuit may be configured to alternately assert and de-assert a threshold detected indication in response to an input signal and a state thereof. The state detection circuit may be configured to generate a signal state indication about a state of the input signal. The measurement circuit may be configured to generate a measurement in response to assertions of the threshold detected indication and the signal state indication, such as a count, a slew rate, or a frequency. In some embodiments, disclosed sensors may have programmable thresholds for sensing the signal states and changes therein.

Abstract: A semiconductor device includes a delay compensation circuit and a bias control circuit. The delay compensation circuit includes a variable delay circuit configured to generate an output signal by delaying an input signal and configured to compensate, according to a first bias control signal, for delay fluctuation caused by fluctuation of a power supply voltage between a first power source and a second power source. The bias control circuit is configured to generate the first bias control signal to compensate for the delay fluctuation.

Abstract: In an embodiment, a digital output driver circuit comprises an output stage having first and second transistors. A drive stage is configured to drive control terminals of the first and second transistors and comprising switching circuitry and current generator circuitry. In a first configuration, the driver circuit is configured to connect a control terminal of the second transistor to the reference node to turn off the second transistor; and connect a first capacitance to the current generator circuitry and to a control terminal of the first transistor to turn on the first transistor. In a second configuration, the driver circuit is configured to turn off the first transistor and connect the control terminal of the second transistor to the current generator circuitry and to the second capacitance to turn on the second transistor.

Abstract: A high-speed voltage clamping circuit includes p-type field effect transistor (PFET) biasing circuit, an n-type field effect transistor (NFET) biasing circuit, and a field effect transistor (FET) clamp circuit. The PFET biasing circuit is configured to generate a PFET biasing voltage. The NFET biasing circuit is configured to generate a NFET biasing voltage. The FET clamp circuit is in signal communication with the PFET biasing circuit and the NFET biasing circuit. The PFET biasing circuit controls operation of the clamping circuit in response to a voltage overshoot event and the NFET biasing circuit controls operation of the clamping circuit in response to a voltage undershoot event.

Abstract: A circuit includes first to third transistors. The first transistor includes a first terminal coupled to a first voltage, and a second terminal coupled to a connection. The second transistor includes a gate terminal coupled to the gate terminal of the first transistor, a first terminal coupled to a second voltage, and a second terminal coupled to the connection. The third transistor includes a first terminal coupled to the connection, a second terminal coupled to a node between the second terminals of the first and second transistors. The third transistor is controlled to be turned ON at a beginning of a first edge of a driving signal on the connection to pull a voltage of the driving signal on the first edge toward a threshold voltage, and be turned OFF in response to and after the voltage of the driving signal on the first edge reaching the threshold voltage.

Abstract: A system for improvement of waveform transmission and event detection includes a first transducer configured to receive acoustic waveforms, and a first transducer processor and transmitter configured to invert the phase of the received waveforms of the first transducer and transmit the inverted waveforms via light to a second transducer. The second transducer is configured to receive light waveforms from the first transducer processor and transmitter, receive acoustic waveforms from the second transducer, convert the first transducer light waveforms and the second transducer acoustic waveforms into electrical waveforms, and transmit a combined electrical waveform onwards.

Abstract: A transceiver device for a bus system and a method for reducing conducted emissions. The transceiver device has a transmitting stage for transmitting a transmit signal to a first bus wire of a bus of the bus system, in which bus system an exclusive, collision-free access of a user station to the bus of the bus system is at least temporarily ensured, and for transmitting the transmit signal to a second bus wire of the bus, a receiving stage for receiving the bus signal transmitted on the bus wires, and an emission reduction unit for controlling a switch-on path of a first stand-off device in the transmitting stage as a function of whether or not a dominant stage of the transmit signal occurs.

Abstract: A circuit is configured to drive a switch mode regulator and to control the slew rate at a switching terminal of the regulator. The circuit includes first and second transistors coupled between a voltage supply terminal and a switching terminal, and includes third and fourth transistors coupled between the voltage supply terminal and the switching terminal. The circuit includes a fifth transistor coupled to the fourth transistor in a current mirror configuration and a sixth transistor coupled between the voltage supply terminal and the third transistor. The circuit includes a first resistor coupled between the voltage supply terminal and the fifth transistor, and includes a second resistor coupled between the sixth transistor and the second transistor.

Abstract: Some aspects of this disclosure are directed to implementing formal gated clock conversion for field programmable gate array (FPGA) synthesis. For example, some aspects of this disclosure relate to a method, including receiving network representation of a circuit design, determining a gated clock function corresponding to a target component of the network representation, and constructing an edge function based at least in part on the gated clock function. The method further includes performing a minimization of the edge function, and in response to a determination that the minimization of the edge function comprises a first term and a second term, providing a clock enable signal to the target component based on the first term, and providing a clock signal to the target component based on the second term.

Abstract: An output buffer circuit includes an operational amplifier configured to generate an amplifier output voltage signal based on an input voltage signal and on a compensation current, a slew rate compensating circuit configured to generate the compensation current to increase a slew rate of the amplifier output voltage signal based on a difference between the input voltage signal and a feedback voltage signal, an output path circuit connected between the operational amplifier and an output pad, the output path circuit configured to transfer the amplifier output voltage signal to generate a pad output voltage signal through the output pad, and a feedback path circuit, the feedback path circuit connected between the slew rate compensating circuit and a feedback input node that is on the output path circuit, the feedback path circuit configured to generate the feedback voltage signal.

Abstract: In a power converter, a regulator that receives a first voltage couples to a switched-capacitor converter that provides a second voltage. Slew-control circuitry controls slew rate within the switched-capacitor converter during operation thereof. A controller controls the operation of both the regulator and the switched-capacitor converter.

Abstract: A pulsed signal generator generates a pulsed signal having a pulse width intended to be equal to a given fraction of a pulse width of a reference clock. A reference current source outputs current having a reference magnitude, and a comparison current source outputs current having a magnitude that is a function of the reference magnitude and the given fraction. A comparison circuit compares a total current output by one of the reference current source and the comparison current source during pulses of the reference clock to a total current output by the other of the reference current source and the comparison current source during pulses of the pulsed signal equal in number to the pulses of the reference clock in order to determine whether the pulse width of the pulse signal is less than or equal to the given fraction of the pulse width of the reference clock.

Abstract: A novel delay circuit for quadrature clock generation with insensitivity to process, voltage, temperature (PVT) variations and equal rising/falling edges is disclosed. In one implementation, the delay circuit includes a first N-substage having a sinking current source, configured to receive an input signal and to generate a rising edge of an output signal of the delay circuit, wherein the output signal is a delayed version of the input signal. The delay circuit further includes a first P-substage having a sourcing current source, configured to receive the input signal and to generate a falling edge of the output signal, where the sinking current source and the sourcing current source are variable in response to respective ones of a plurality of bias voltages.

Abstract: A buffer circuit configured to receive first and second input signals through first and second input transistors coupled to a first power voltage node, output a first output signal through a first output node and a second output signal through a second output node based on the first and second input signals. A load circuit is coupled among the first output node, the second output node, and a second power voltage node and a resistance value is adjusted based on at least one of the first and second output signals.

Abstract: A high voltage driving circuit for driving a load receives a low voltage input signal and generates a high voltage output signal. A short circuit protection circuit including a first electronic switch operated by the low voltage input signal and a second electronic switch operated by a low voltage signal obtained by a voltage division of the output high voltage signal. The first electronic switch causing a first pull-up current to be sent to a capacitive element whose voltage controls an input of a threshold comparator. A second electronic switch causes a second pull-down current to be drawn from the capacitive element whose voltage controls the input of the threshold comparator. A short circuit detection signal is generated at an output of said threshold comparator, indicating a short circuit and capable of inhibiting operation of the driving circuit.

Abstract: Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line. The offset values are based on individual transition threshold voltages biases of sample circuits of the receiver circuit. The example apparatus may further include an input/output (I/O) circuit comprising a driver circuit. The driver circuit configured to receive a logic signal and the offset values and to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values.

Abstract: Disclosed herein is an apparatus that includes an output signal line, and first and second tristate buffer circuits each having an output node connected to the output signal line in common. The output signal line includes a first section having first and second connection points, a second section having third and fourth connection points, a third section connected between the first and third connection points, and a fourth section connected between second and fourth connection points. At least a part of the first section of the output signal line is located on the first tristate buffer circuit, and at least a part of the second section of the output signal line is located on the second tristate buffer circuit.

Abstract: The present disclosure provides an integrated circuit (IC) device and a circuitry. The IC includes a measurement circuit and a classifier circuit. The measurement circuit is configured to acquire a practical voltage. The classifier circuit is configured to: generate an information on an immature classification by comparing a default voltage and the practical voltage; receive an information on a reference classification, wherein the reference classification is acquired by manually comparing the default voltage and the practical voltage; update the default voltage to a learned voltage based on the immature classification and the reference classification; and generate a prediction, based on the learned voltage, for adjusting a slew rate.

Abstract: A display device includes a driving controller sensing a pattern of first image signals from a source external to the driving controller and outputting a compensation selection signal corresponding to the sensed pattern. A voltage generator generates a driving power voltage in response to the compensation selection signal. The voltage generator includes a power converter generating the driving power voltage in response to a power control signal, a comparator comparing the driving power voltage with a reference voltage to output a feedback signal to a first node, and a compensation circuit including a plurality of compensation units. A selected compensation unit is connected to the first node, and a power control circuit outputs the power control signal in response to the feedback signal. The slew rate of the feedback signal may be controlled by a compensation circuit to remove a ripple component from the driving power voltage.

Abstract: A failsafe pulsed laser driver and method for using the same are disclosed. In one embodiment, an apparatus comprises a laser array having a plurality of lasers; and a laser driver coupled to the laser array, wherein the laser driver comprises a current limiter to provide a maximum current at or below a threshold current of lasers in the laser array or at a current level to meet laser safety requirements under circuit failure conditions; one or more capacitors coupled to current limiter and the laser array, the one or more capacitors to be charged in response to current from the current limiter; and a switch coupled to the one or more capacitors operable to cause current from the one or more capacitors to flow through the laser array.

Abstract: A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.

Abstract: An image sensing device includes: a pixel array suitable for generating a plurality of pixel signals corresponding to incident light; a comparison block suitable for comparing the pixel signals with a ramp signal to generate a plurality of comparison signals; a logic block suitable for adjusting slew rates of the respective comparison signals to generate a plurality of logic signals; a global count block suitable for generating a global count signal; and a storing block suitable for storing counted values of the global count signal based on the logic signals received from the logic block.

Abstract: A multi-output gate driver system comprises a power device having a gate node; a first driver having an input and an output coupled to the gate node; a second driver having an input and an output coupled to the gate node; a first comparator having a first input coupled to the output of the second driver, a second input coupled to a first reference voltage, and an output; a second comparator having a first input coupled to the output of the second driver, a second input coupled to a second reference voltage, and an output; and a logic circuit having an input for receiving a control signal, a first output coupled to the input of the first driver, and a second output coupled to the input of the second driver.

Abstract: The present invention provides a clock signal controller structure. The invention allows for the large-skew clock signals to be converted into small-skew clock signals. The technical solution of the present invention may be adopted to synchronize two large-skew clock signals.

Abstract: A driver circuit has pre-driver and transistor pairs coupled in parallel paths with different delays in different paths allowing the driver to automatically adjust to load conditions, providing a moderate driver with low output ringing for low capacitive loads, while the added delay in the different paths is negligible when driving heavy capacitive loads. The driver circuit automatically scales drive strength of the output driver during switching transients to the load capacitance, providing a good trade-off between fast transient and low output ringing for a variety of different capacitive loads.

Abstract: A gate driver integrated circuit (IC) and a method of operating the same is provided. The gate driver IC is configured to drive a transistor between switching states in a power circuit, and includes a memory configured to store at least one measurement window parameter that defines a measurement interval; measurement circuitry configured to measure, over the measurement interval, a value corresponding to an operation of the power circuit, the measured value being proportional to an input capacitance of the transistor; processing circuitry configured to determine a correction factor based on the measured value, the correction factor being proportional to the input capacitance of the transistor; and a gate controller configured to control a gate current of the transistor based on the switching states and the correction factor.

Abstract: A dynamic bus communication apparatus for an electrosurgical system includes a data wire, a clock wire, a first variable resistor coupled to the data wire, a second variable resistor coupled to the clock wire, an analog to digital converter (ADC), and a controller. The data wire is configured to transmit a data signal between a battery and an instrument powered by the battery. The clock wire is configured to transmit a clock signal between a battery and an instrument. The ADC is configured to sample the data signal and the clock signal at a substantially higher frequency than a frequency of the clock signal. The controller is configured to control a resistance of the first variable resistor and a resistance of the second variable resistor based on the digitally sampled data signal and the digitally sampled clock signal.

Abstract: A digital regulator at least includes a comparator, a hysteresis comparator, a first control circuit, a second control circuit, a first transistor, and a second transistor. The comparator compares a reference voltage with an internal voltage, so as to generate a first control voltage. The hysteresis comparator compares the reference voltage with the internal voltage, so as to generate a second control voltage. The first transistor is coupled between a relatively high internal voltage and a control node. The first transistor is controlled by the first control circuit according to the first control voltage and the second control voltage. The second transistor is coupled between the control node and the internal voltage. The second transistor is controlled by the second control circuit according to the first control voltage and the second control voltage.

Abstract: The present invention provides a high-frequency delay-locked loop and a clock processing method for the high-frequency delay-locked loop. The high-frequency delay-locked loop comprises a DLL circuit and a DCC circuit that are sequentially connected in series, and a pulse generating circuit used for generating a clock having a fixed pulse width. The fixed pulse width is a high-level width of the clock having the fixed pulse width and not smaller than a minimum pulse width required by the DLL circuit. The fixed pulse width enables a low-level width of the clock having the fixed pulse width to be not smaller than the minimum pulse width required by the DLL circuit. The clock having the fixed pulse width is input into the DLL circuit.

Abstract: A memory controller adjusts impedance matching of an output terminal and outputs a control signal that controls a memory through the output terminal. The memory controller includes a first driving and impedance matching circuit, a second driving and impedance matching circuit, and a logic circuit. The logic circuit, which is coupled to the first driving and impedance matching circuit and the second driving and impedance matching circuit, sets a first impedance and a first driving capability of the first driving and impedance matching circuit, sets a second impedance and a second driving capability of the second driving and impedance matching circuit, and enables the first driving and impedance matching circuit to cause the control signal to have a first level or enables the second driving and impedance matching circuit to cause the control signal to have a second level different from the first level.

Abstract: An image sensing device includes: a pixel array suitable for generating a plurality of pixel signals corresponding to incident light; a comparison block suitable for comparing the pixel signals with a ramp signal to generate a plurality of comparison signals; a logic block suitable for adjusting slew rates of the respective comparison signals to generate a plurality of logic signals; a global count block suitable for generating a global count signal; and a storing block suitable for storing counted values of the global count signal based on the logic signals received from the logic block.

Abstract: Various arrangements for decreasing harmonics of an output digital signal are presented. A programmable current rise-time circuit may be present that controls a rising edge of the output digital signal, wherein the output digital signal is output to an input/output (I/O) pad. A programmable current fall-time circuit may be present that controls a falling edge of the output digital signal. A feedback circuit may be present that monitors a rise-time of the rising edge of the output digital signal and fall-time of the falling edge of the output digital signal. A control circuit may be present that provides a first input to the programmable current rise-time circuit to adjust the rise-time of the rising edge of the output digital signal and a second input to the programmable current fall-time circuit to adjust the fall-time of the falling edge of the output digital signal.

Abstract: A complementary signal path may include an amplifier circuit configured to receive a pair of complementary input signals and a data alignment circuit configured to output a pair of complementary output signals in response to the pair of complementary input signals. A control circuit may detect duty cycle distortion in the pair of complementary output signals and perform a duty cycle correction process to remove the distortion. To do so, the control circuit may search for target current amounts in response to the duty cycle distortion and inject a control current into the amplifier circuit at the target current amounts.

Abstract: An amplifier includes a dynamic bias circuit and an amplification circuit coupled to the dynamic bias circuit. The dynamic bias circuit includes a plurality of transistors coupled to a plurality of resistors. The dynamic bias circuit is configured to generate a bias current with a magnitude that increases in response to the dynamic bias circuit receiving a falling edge of an input signal and decreases in response to the dynamic bias circuit receiving a rising edge of the input signal. The amplification circuit is configured to receive the bias current and amplify the input signal based on the bias current to generate an output signal that has a higher slew rate for a falling signal than for a rising signal.