Slope Control Of Leading Or Trailing Edge Of Rectangular (e.g., Clock, Etc.) Or Pulse Waveform Patents (Class 327/170)
  • Patent number: 10931270
    Abstract: Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line. The offset values are based on individual transition threshold voltages biases of sample circuits of the receiver circuit. The example apparatus may further include an input/output (I/O) circuit comprising a driver circuit. The driver circuit configured to receive a logic signal and the offset values and to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yasuo Satoh, Kazutaka Miyano
  • Patent number: 10825507
    Abstract: Disclosed herein is an apparatus that includes an output signal line, and first and second tristate buffer circuits each having an output node connected to the output signal line in common. The output signal line includes a first section having first and second connection points, a second section having third and fourth connection points, a third section connected between the first and third connection points, and a fourth section connected between second and fourth connection points. At least a part of the first section of the output signal line is located on the first tristate buffer circuit, and at least a part of the second section of the output signal line is located on the second tristate buffer circuit.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kenichi Watanabe
  • Patent number: 10770024
    Abstract: A display device includes a driving controller sensing a pattern of first image signals from a source external to the driving controller and outputting a compensation selection signal corresponding to the sensed pattern. A voltage generator generates a driving power voltage in response to the compensation selection signal. The voltage generator includes a power converter generating the driving power voltage in response to a power control signal, a comparator comparing the driving power voltage with a reference voltage to output a feedback signal to a first node, and a compensation circuit including a plurality of compensation units. A selected compensation unit is connected to the first node, and a power control circuit outputs the power control signal in response to the feedback signal. The slew rate of the feedback signal may be controlled by a compensation circuit to remove a ripple component from the driving power voltage.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: September 8, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Gwangsoo Ahn, Sanghyun Lee, Dongwon Park, Songyi Han
  • Patent number: 10769553
    Abstract: The present disclosure provides an integrated circuit (IC) device and a circuitry. The IC includes a measurement circuit and a classifier circuit. The measurement circuit is configured to acquire a practical voltage. The classifier circuit is configured to: generate an information on an immature classification by comparing a default voltage and the practical voltage; receive an information on a reference classification, wherein the reference classification is acquired by manually comparing the default voltage and the practical voltage; update the default voltage to a learned voltage based on the immature classification and the reference classification; and generate a prediction, based on the learned voltage, for adjusting a slew rate.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: September 8, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chung-Peng Hao
  • Patent number: 10756510
    Abstract: A failsafe pulsed laser driver and method for using the same are disclosed. In one embodiment, an apparatus comprises a laser array having a plurality of lasers; and a laser driver coupled to the laser array, wherein the laser driver comprises a current limiter to provide a maximum current at or below a threshold current of lasers in the laser array or at a current level to meet laser safety requirements under circuit failure conditions; one or more capacitors coupled to current limiter and the laser array, the one or more capacitors to be charged in response to current from the current limiter; and a switch coupled to the one or more capacitors operable to cause current from the one or more capacitors to flow through the laser array.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Paul Winer, Krishna Swaminathan
  • Patent number: 10720221
    Abstract: A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.
    Type: Grant
    Filed: September 2, 2018
    Date of Patent: July 21, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kensuke Yamamoto, Fumiya Watanabe, Shouichi Ozaki
  • Patent number: 10681293
    Abstract: An image sensing device includes: a pixel array suitable for generating a plurality of pixel signals corresponding to incident light; a comparison block suitable for comparing the pixel signals with a ramp signal to generate a plurality of comparison signals; a logic block suitable for adjusting slew rates of the respective comparison signals to generate a plurality of logic signals; a global count block suitable for generating a global count signal; and a storing block suitable for storing counted values of the global count signal based on the logic signals received from the logic block.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventor: Won-Seok Hwang
  • Patent number: 10651723
    Abstract: A multi-output gate driver system comprises a power device having a gate node; a first driver having an input and an output coupled to the gate node; a second driver having an input and an output coupled to the gate node; a first comparator having a first input coupled to the output of the second driver, a second input coupled to a first reference voltage, and an output; a second comparator having a first input coupled to the output of the second driver, a second input coupled to a second reference voltage, and an output; and a logic circuit having an input for receiving a control signal, a first output coupled to the input of the first driver, and a second output coupled to the input of the second driver.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: May 12, 2020
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Wolfgang Frank, Simone Fabbro, Karl Norling
  • Patent number: 10587251
    Abstract: The present invention provides a clock signal controller structure. The invention allows for the large-skew clock signals to be converted into small-skew clock signals. The technical solution of the present invention may be adopted to synchronize two large-skew clock signals.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ou He, Yan S H He, Wei A W Zhao
  • Patent number: 10469057
    Abstract: A gate driver integrated circuit (IC) and a method of operating the same is provided. The gate driver IC is configured to drive a transistor between switching states in a power circuit, and includes a memory configured to store at least one measurement window parameter that defines a measurement interval; measurement circuitry configured to measure, over the measurement interval, a value corresponding to an operation of the power circuit, the measured value being proportional to an input capacitance of the transistor; processing circuitry configured to determine a correction factor based on the measured value, the correction factor being proportional to the input capacitance of the transistor; and a gate controller configured to control a gate current of the transistor based on the switching states and the correction factor.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: November 5, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Wolfgang Frank, Christian Philipp Sandow
  • Patent number: 10469075
    Abstract: A driver circuit has pre-driver and transistor pairs coupled in parallel paths with different delays in different paths allowing the driver to automatically adjust to load conditions, providing a moderate driver with low output ringing for low capacitive loads, while the added delay in the different paths is negligible when driving heavy capacitive loads. The driver circuit automatically scales drive strength of the output driver during switching transients to the load capacitance, providing a good trade-off between fast transient and low output ringing for a variety of different capacitive loads.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: November 5, 2019
    Assignee: Silicon Laboratories Inc.
    Inventor: András V. Horváth
  • Patent number: 10459867
    Abstract: A dynamic bus communication apparatus for an electrosurgical system includes a data wire, a clock wire, a first variable resistor coupled to the data wire, a second variable resistor coupled to the clock wire, an analog to digital converter (ADC), and a controller. The data wire is configured to transmit a data signal between a battery and an instrument powered by the battery. The clock wire is configured to transmit a clock signal between a battery and an instrument. The ADC is configured to sample the data signal and the clock signal at a substantially higher frequency than a frequency of the clock signal. The controller is configured to control a resistance of the first variable resistor and a resistance of the second variable resistor based on the digitally sampled data signal and the digitally sampled clock signal.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: October 29, 2019
    Assignee: COVIDIEN LP
    Inventor: Scott E. M. Frushour
  • Patent number: 10444782
    Abstract: A digital regulator at least includes a comparator, a hysteresis comparator, a first control circuit, a second control circuit, a first transistor, and a second transistor. The comparator compares a reference voltage with an internal voltage, so as to generate a first control voltage. The hysteresis comparator compares the reference voltage with the internal voltage, so as to generate a second control voltage. The first transistor is coupled between a relatively high internal voltage and a control node. The first transistor is controlled by the first control circuit according to the first control voltage and the second control voltage. The second transistor is coupled between the control node and the internal voltage. The second transistor is controlled by the second control circuit according to the first control voltage and the second control voltage.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: October 15, 2019
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Chih-Feng Lin
  • Patent number: 10404247
    Abstract: The present invention provides a high-frequency delay-locked loop and a clock processing method for the high-frequency delay-locked loop. The high-frequency delay-locked loop comprises a DLL circuit and a DCC circuit that are sequentially connected in series, and a pulse generating circuit used for generating a clock having a fixed pulse width. The fixed pulse width is a high-level width of the clock having the fixed pulse width and not smaller than a minimum pulse width required by the DLL circuit. The fixed pulse width enables a low-level width of the clock having the fixed pulse width to be not smaller than the minimum pulse width required by the DLL circuit. The clock having the fixed pulse width is input into the DLL circuit.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: September 3, 2019
    Assignee: XI'AN UNIIC SEMICONDUCTORS CO., LTD.
    Inventor: Alassandro Minzoni
  • Patent number: 10382232
    Abstract: A memory controller adjusts impedance matching of an output terminal and outputs a control signal that controls a memory through the output terminal. The memory controller includes a first driving and impedance matching circuit, a second driving and impedance matching circuit, and a logic circuit. The logic circuit, which is coupled to the first driving and impedance matching circuit and the second driving and impedance matching circuit, sets a first impedance and a first driving capability of the first driving and impedance matching circuit, sets a second impedance and a second driving capability of the second driving and impedance matching circuit, and enables the first driving and impedance matching circuit to cause the control signal to have a first level or enables the second driving and impedance matching circuit to cause the control signal to have a second level different from the first level.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: August 13, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shih-Hung Wang, Shen-Kuo Huang, Gerchih Chou, Wen-Shan Wang
  • Patent number: 10298868
    Abstract: An image sensing device includes: a pixel array suitable for generating a plurality of pixel signals corresponding to incident light; a comparison block suitable for comparing the pixel signals with a ramp signal to generate a plurality of comparison signals; a logic block suitable for adjusting slew rates of the respective comparison signals to generate a plurality of logic signals; a global count block suitable for generating a global count signal; and a storing block suitable for storing counted values of the global count signal based on the logic signals received from the logic block.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: May 21, 2019
    Assignee: SK hynix Inc.
    Inventor: Won-Seok Hwang
  • Patent number: 10291213
    Abstract: Various arrangements for decreasing harmonics of an output digital signal are presented. A programmable current rise-time circuit may be present that controls a rising edge of the output digital signal, wherein the output digital signal is output to an input/output (I/O) pad. A programmable current fall-time circuit may be present that controls a falling edge of the output digital signal. A feedback circuit may be present that monitors a rise-time of the rising edge of the output digital signal and fall-time of the falling edge of the output digital signal. A control circuit may be present that provides a first input to the programmable current rise-time circuit to adjust the rise-time of the rising edge of the output digital signal and a second input to the programmable current fall-time circuit to adjust the fall-time of the falling edge of the output digital signal.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: May 14, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Hassan Elwan
  • Patent number: 10284157
    Abstract: An amplifier includes a dynamic bias circuit and an amplification circuit coupled to the dynamic bias circuit. The dynamic bias circuit includes a plurality of transistors coupled to a plurality of resistors. The dynamic bias circuit is configured to generate a bias current with a magnitude that increases in response to the dynamic bias circuit receiving a falling edge of an input signal and decreases in response to the dynamic bias circuit receiving a rising edge of the input signal. The amplification circuit is configured to receive the bias current and amplify the input signal based on the bias current to generate an output signal that has a higher slew rate for a falling signal than for a rising signal.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: May 7, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Charles Parkhurst
  • Patent number: 10284182
    Abstract: A complementary signal path may include an amplifier circuit configured to receive a pair of complementary input signals and a data alignment circuit configured to output a pair of complementary output signals in response to the pair of complementary input signals. A control circuit may detect duty cycle distortion in the pair of complementary output signals and perform a duty cycle correction process to remove the distortion. To do so, the control circuit may search for target current amounts in response to the duty cycle distortion and inject a control current into the amplifier circuit at the target current amounts.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: May 7, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Primit Modi, Venkatesh Ramachandra, Tianyu Tang, Srinivas Rajendra
  • Patent number: 10276229
    Abstract: Example circuitry to adjust a rise-fall skew in a signal includes: a latch including a first latch input, a second latch input, and a latch output, each of the first latch input and the second latch input being responsive to a rising edge of a version of a signal to provide a predefined logic level at the latch output; a first delay circuit that is controllable to configure a first delay, the first delay circuit being electrically connected to the first latch input and being for adjusting a rise portion of a skew in a first version of the signal; and a second delay circuit that is controllable to configure a second delay, the second delay circuit being electrically connected to the second latch input and being for adjusting a fall portion of the skew in a second version the signal.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: April 30, 2019
    Assignee: Teradyne, Inc.
    Inventor: Jan Paul Antonie van der Wagt
  • Patent number: 10243571
    Abstract: A source-synchronous clocking signal is sampled by an edge sampler triggered by a phase-adjusted version of the clocking signal. The output of the edge sampler is used as a phase-error indicator for a filtered feedback loop that aligns the phase-adjusted clocking signal to minimize, on average, the difference between the received source-synchronous clocking signal and the phase-adjusted version of the clocking signal minus the setup time of the sampler. This forms a delay-locked loop configuration. The phase adjustment information used to produce the aligned phase-adjusted clocking signal is then to produce a receiver clocking signal that is used to sample the source-synchronous data signal.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: March 26, 2019
    Assignee: Rambus Inc.
    Inventor: Reza Navid
  • Patent number: 10175297
    Abstract: A method, apparatus, and computer program product for measuring a slew rate of a digital high speed repeating signal on-chip including, transforming the rising and the falling edges of the signal into a digital pulse signal each; and selecting the digital pulse signals corresponding either to the rising edge or to the falling edge of the signal. Further the method including converting the selected digital pulse signals into an average DC voltage equivalent to the pulse width of the respective digital pulse signal; as well as converting each DC voltage into a binary value.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Fatih Cilek, Guenther Hutzl, Michael Koch, Christian I. Menolfi, Dieter Nissler, Matthias Ringe
  • Patent number: 10171268
    Abstract: An apparatus comprises a plurality of driver circuits and a control registers block. The plurality of driver circuits may be configured to drive a read line in response to a memory signal and a reference voltage. The control registers block generally configures the plurality of driver circuits to implement an asymmetric voltage swing of the read line about a voltage level that is half of the reference voltage.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: January 1, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Yue Yu, Craig DeSimone, Al Xuefeng Fang, Yanbo Wang
  • Patent number: 10141931
    Abstract: A memory device includes a main driver and a pre-driver. The main driver provides an output signal to a host based on a plurality of driving signals. The pre-driver provides the main driver with the plurality of driving signals in order to calibrate a slew rate of the output signal based on an output resistance value of the main driver and a resistance value of an on-die termination circuit of the host. The pre-driver is configured to generate a first driving signal of the plurality of driving signals in response to an input signal regardless of a control signal, and to generate a second driving signal of the plurality of driving signals in response to the input signal and the control signal.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: November 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hun-Dae Choi
  • Patent number: 10103711
    Abstract: A constant impedance switch dynamically manages switch impedance to eliminate or substantially reduce impedance glitches during switching events by stepping variable impedances through sequences of impedance values. As a result, VSWR may be reduced to or near 1:1, allowing programming and circuitry to be simplified. Switch impedance may be maintained for single and multi-throw switches having variable impedances of any order. Each variable impedance may comprise one or more configurable cells, subcells and elements controlled by thermometer, binary, hybrid or other coding technique.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: October 16, 2018
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Shawn Bawell, Jean-Marc Mourant, Olivier Hubert
  • Patent number: 10097175
    Abstract: According to an embodiment, a semiconductor device includes: a first modulation circuit configured to generate a reference signal based on a first clock signal; a second modulation circuit configured to generate a feedback signal with a phase negative relative to a phase of the reference signal based on a second clock signal with a phase negative relative to a phase of the first clock signal; a comparator configured to compare the reference signal with the feedback signal to determine duty and generate a comparator signal; and a driver configured to output a drive signal.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: October 9, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenichi Wakasugi
  • Patent number: 10015027
    Abstract: Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures are disclosed herein. An example method may include comparing a current channel state of a channel of a multi-level communication bus with a next channel state of the channel. The example method may further include, based on the comparison, applying an offset delay to a control signal configured to control transition of a signal line of the channel from a value associated with the current channel state to a value associated with the next channel state. The example method may further include after application of the offset delay, driving the signal line to the value associated with the next channel state responsive to the control signal.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: July 3, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Bruce W. Schober
  • Patent number: 9941873
    Abstract: A method and apparatus are provided for balancing currents of two or more parallel-connected power semiconductor switches during an on-state of the switches. A control terminal of each switch is driven by a driver unit. The method includes determining ratios between the currents through the switches. For each switch, the method includes controlling the voltage at the control terminal on the basis of the ratios by controlling a level of a supply voltage of the driver unit of the switch, and after a turn-on commutation transient, modulating the output of the driver unit. The duty cycle of the modulation is controlled to minimize the time required for the transition of the voltage at the control terminal from the one voltage level to another.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: April 10, 2018
    Assignee: ABB Oy
    Inventors: Ignacio Lizama, Rodrigo Alonso Alvarez Valenzuela, Steffen Bernet, Matti Laitinen
  • Patent number: 9882529
    Abstract: Methods and devices are disclosed driving one or more P-Intrinsic-N (PIN) diodes by receiving an input and generating a plurality of pulses based on the input, a first pulse of the plurality of pulses controls a rise time of an RF envelope generated by an RF interface and a second pulse of the plurality of pulses controls a fall time of the RF envelope generated by the RF interface. The methods and devices may further be disclosed combining the plurality of pulses to generate a drive signal, delivering the drive signal to the RF interface including one or more PIN diodes, and generating the RF envelope by driving the one or more PIN diodes with the drive signal, and the amplitude or a pulse width of the first pulse is independently adjustable from the amplitude or the pulse width of the second pulse.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: January 30, 2018
    Assignee: Honeywell International Inc.
    Inventor: David Larsen
  • Patent number: 9843325
    Abstract: A level shifter circuit includes a level shifting unit configured to receive signals that may vary in a first range via a positive input terminal and a negative input terminal, respectively and to output signals that may vary in a second range to a positive output terminal and a negative output terminal, respectively, where the second range is larger than the first range, a first pre-charging unit configured to pre-charge the positive output terminal to a predetermined level when a clock is in a first level, and a second pre-charging unit configured to pre-charge the negative output terminal to the predetermined level when the clock is in the first level.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: December 12, 2017
    Assignee: SK Hynix Inc.
    Inventor: Taek-Sang Song
  • Patent number: 9843324
    Abstract: A voltage-mode transmitter includes a calibration circuit having a replica circuit. By adjusting a feedback voltage driving a gate of a replica transistor in the replica circuit so that an impedance of the replica circuit matches an impedance of a variable resistor, the calibration circuit calibrates an output impedance of a single slice driver.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: December 12, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Madjid Hafizi, George Shing
  • Patent number: 9794087
    Abstract: An apparatus comprising a plurality of driver circuits and a plurality of control registers. The plurality of driver circuits may be configured to modify a memory signal that transfers read data across a read line to a memory controller. The plurality of control registers may be configured to enable one or more of the driver circuits. A pull up strength and a pull down strength of the memory signal may be configured in response to how many of the plurality of driver circuits are enabled. The plurality of driver circuits implement an asymmetric pull up and pull down of the memory signal.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: October 17, 2017
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Yue Yu, Craig DeSimone, Al Xuefeng Fang, Yanbo Wang
  • Patent number: 9742387
    Abstract: The present disclosure is applicable to electronic fields, and provides a voltage comparator. The voltage comparator includes a first branch, a second branch and a third branch. The first branch and the second branch both have self-biasing capabilities, and require no dedicated bias circuit. Under the same power voltage, the static power consumption of the voltage comparator is relatively low; fewer the power consuming branches exist in the circuit, and the reliability is high under low power consumption.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: August 22, 2017
    Assignee: Shenzhen Goodix Technologies Co., Ltd.
    Inventor: Chang Zhan
  • Patent number: 9728532
    Abstract: An electro-static discharge (ESD) protection circuit utilizes a gate-drain breakdown characteristic of high electron mobility transistors (HEMTs) in a dual stacked configuration to provide a discharge path for electro-static discharges, while having a minimal effect on the associated circuit which is being protected.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: August 8, 2017
    Assignee: Qorvo US, Inc.
    Inventors: Swaminathan Muthukrishnan, Nathaniel Peachey, Cody Hale, Ralph Williamson
  • Patent number: 9722829
    Abstract: A pulse shaping circuit is configured to shape a waveform of an edge of a signal applied to a switch of a power amplifier included in an on-off keying transmitter.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: August 1, 2017
    Assignees: Samsung Electronics Co., Ltd., Postech Academy-Industry Foundation
    Inventors: Jae Sup Lee, Bum Man Kim, Han-Kyu Lee, Dae Chul Jeong, Tae Young Chung
  • Patent number: 9712257
    Abstract: An apparatus, and method therefor, relates generally to a transmitter. In such an apparatus, a decoder is configured to receive a data input and control signals and to generate state signals responsive to a control signal of the control signals and data polarity the data input. Select circuitry is configured to receive coded signals to replace the data input with a pull-up code and a pull-down code of the coded signals responsive to the state signals and the control signals for propagation of the pull-up code and the pull-down code in place of the data input.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: July 18, 2017
    Assignee: XILINX, INC.
    Inventors: Sing Keng Tan, David S. Smith
  • Patent number: 9673793
    Abstract: Apparatuses and methods for adjusting timing of signals are described herein. An example method may include providing an output clock signal responsive to an input clock signal, and adjusting a slew rate of the output clock signal by a delayed output clock signal.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: June 6, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Yantao Ma
  • Patent number: 9628058
    Abstract: A skew correction circuit includes: a phase-difference detection circuit that generates a phase difference signal indicating a phase difference between an edge of a first signal that is one signal of differential signals and an edge of a second signal that is another signal of the differential signals; and a correction-signal generation circuit that generates a correction signal having an inverted phase of the second signal by combining the phase difference signal and the first signal.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: April 18, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Teruaki Yagoshi
  • Patent number: 9614505
    Abstract: A differential driving circuit according to embodiments of the inventive may include a first driver drives a first pad to a first voltage according to a first driving signal, a second driver drives a second pad to a second voltage according to a second driving signal, a first and second capacitors for receiving a first and second voltage changes of the first and the second pad at one end thereof respectively to transmit the first and the second voltage change to the other end thereof respectively in a transition interval in which voltages of the first and second pads are changed, transition interval voltage adder circuit adds voltages respectively transmitted thereto through the first and second capacitors, and a transition interval asymmetry compensation circuit adjusts a slope of at least one of the first and second driving signals according to the added voltage.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: April 4, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Min-Hyung Cho, Yi-Gyeong Kim, Chun-Gi Lyuh, Young-deuk Jeon
  • Patent number: 9548876
    Abstract: A system includes a first transmitter, a second transmitter, a third transmitter and a controller, where the first transmitter is arranged for transmitting a first signal to a first transmission line, the second transmitter is arranged for transmitting a second signal to a second transmission line, and the third transmitter is arranged for transmitting a third signal to a third transmission line. The controller is coupled to the first transmitter, the second transmitter and the third transmitter, and is arranged for setting impedances of the first transmitter, the second transmitter and the third transmitter according to a coding jitter determination result.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: January 17, 2017
    Assignee: MEDIATEK INC.
    Inventor: Kai-Hui Tseng
  • Patent number: 9543942
    Abstract: The present invention comprises a method and apparatus for controlling an IGBT device. The method comprises, upon receipt of a first and at least one further IGBT control signals, the first IGBT control signal indicating a required change in operating state of the IGBT device, controlling an IGBT driver module for the IGBT device to change an operating state of the IGBT device by applying a first logical state modulation at an input of an IGBT coupling channel, and applying at least one further modulation to the logical state at the input of the IGBT coupling channel in accordance with the at least one further IGBT control signal within a time period from the first logical state modulation, the time period being less than a state change reaction period ?t for the at least one IGBT device.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: January 10, 2017
    Assignee: NXP USA, Inc.
    Inventors: Thierry Sicard, Philippe Perruchoud
  • Patent number: 9466540
    Abstract: Provided is a detection apparatus that detects process variation in a plurality of comparators that each output a comparison result obtained by comparing a signal level of an input signal to a reference level, the detection apparatus comprising a signal input section that inputs the input signal and the reference level in common to the comparators, and sequentially changes the signal level of the input signal; and a detecting section that detects, for each signal level, a number of comparison results that indicate a predetermined result, from among the comparison results of the comparators, and detects the process variation based on a distribution of the number of comparison results that indicate the predetermined result.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: October 11, 2016
    Assignees: ADVANTEST CORPORATION, THE UNIVERSITY OF TOKYO
    Inventors: Takahiro Yamaguchi, Satoshi Komatsu, Kunihiro Asada, James Sumit Tandon
  • Patent number: 9436312
    Abstract: An input apparatus includes: a touch sensor 11; a piezoelectric element 13; a piezoelectric element drive unit 15; a control unit 17 configured to detect a pressure load on the touch sensor 11 based on an output signal of the piezoelectric element 13 and, when the pressure load satisfies a standard to provide a tactile sensation, to control the piezoelectric element drive unit 15 to drive the piezoelectric element 13 such that the tactile sensation is provided to a pressing object; a connection switchover unit 14 configured to selectively connect the piezoelectric element 13 to the control unit 17 or the piezoelectric element drive unit 15; and a discharge circuit 16 configured to discharge electric charge in the piezoelectric element 13.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: September 6, 2016
    Assignee: KYOCERA Corporation
    Inventor: Katsuhiko Shimizu
  • Patent number: 9425786
    Abstract: A gate driver circuit for the power switch is disclosed. The gate driver circuit includes a resistor network coupled to the power switch. The resistor network includes a plurality of resistors and a control unit operatively coupled to the resistor network. The control unit detects an occurrence of a commutation phase and a saturation phase based on an identity of the power switch and corresponding time stamps associated with a start of a delay phase, the commutation phase, and the saturation phase. The control unit further controls the resistor network to provide different resistance values in at least two of a delay phase, a commutation phase, and a saturation phase when the power switch is transitioned to a first state. A method for driving the power switch is also disclosed.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: August 23, 2016
    Assignee: General Electric Company
    Inventors: Thomas Alois Zoels, Alvaro Jorge Mari Curbelo, Miguel Garcia Clemente
  • Patent number: 9386237
    Abstract: An image processing device performs image processing on an image being captured to display the image on a display unit having a resolution lower than a resolution of the image. The image processing device includes an extraction section that extracts an edge component from the image, an edge enhancing section that enhances the edge component by performing low-pass filter processing on the edge component after performing full-wave rectification processing on the edge component, a combining section that combines the enhanced edge component with the image to generate a composite image, and a resolution conversion section that performs resolution conversion of the composite image to match a resolution of the composite image with the resolution of the display unit.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: July 5, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventor: Nana Ohyama
  • Patent number: 9319034
    Abstract: An integrated circuit can include at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; and a counter configured to generate a count value corresponding to a duration of the first pulse.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: April 19, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: David A. Kidd, Edward J. Boling, Vineet Agrawal, Samuel Leshner, Augustine Kuo, Sang-Soo Lee, Chao-Wu Chen
  • Patent number: 9306579
    Abstract: Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: April 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Chang Ki Kwon, Greg A. Blodgett
  • Patent number: 9275707
    Abstract: A memory controller includes a bus driver that allows the controller to support both a semiconductor memory device supporting a low power double data rate 3 (LPDDR3) transmission method and a semiconductor memory device supporting a low power double data rate 4 (LPDDR4) transmission method.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: March 1, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyung-Hoi Koo
  • Patent number: 9270262
    Abstract: A circuit includes a first set of transistors and a second set of transistors. The first set of transistors is configured to be turned on in a sequential manner. The second set of transistors is configured to be turned on in a sequential manner after the first set of transistors is turned on. A transistor of the first set of transistors corresponds to a first time delay. The first set of transistors corresponds to a second time delay that is a multiple of the first time delay.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: February 23, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Yen Tsai, Atul Katoch
  • Patent number: 9231589
    Abstract: A reference output device includes a low side selector configured to select a first voltage level as an output signal. The output signal is a reference voltage. The reference output device also includes a high side selector configured to select a second voltage level as the output signal. The reference output device also includes a slew rate control configured to switch the output signal between the first voltage level and the second voltage level at a constant slew rate.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: January 5, 2016
    Assignee: NXP B.V.
    Inventors: Hok-tung Wong, Yang Zhao, Brad Gunter, Alma Anderson, James Caravella