Abstract: Example circuitry to adjust a rise-fall skew in a signal includes: a latch including a first latch input, a second latch input, and a latch output, each of the first latch input and the second latch input being responsive to a rising edge of a version of a signal to provide a predefined logic level at the latch output; a first delay circuit that is controllable to configure a first delay, the first delay circuit being electrically connected to the first latch input and being for adjusting a rise portion of a skew in a first version of the signal; and a second delay circuit that is controllable to configure a second delay, the second delay circuit being electrically connected to the second latch input and being for adjusting a fall portion of the skew in a second version the signal.

Abstract: A source-synchronous clocking signal is sampled by an edge sampler triggered by a phase-adjusted version of the clocking signal. The output of the edge sampler is used as a phase-error indicator for a filtered feedback loop that aligns the phase-adjusted clocking signal to minimize, on average, the difference between the received source-synchronous clocking signal and the phase-adjusted version of the clocking signal minus the setup time of the sampler. This forms a delay-locked loop configuration. The phase adjustment information used to produce the aligned phase-adjusted clocking signal is then to produce a receiver clocking signal that is used to sample the source-synchronous data signal.

Abstract: A method, apparatus, and computer program product for measuring a slew rate of a digital high speed repeating signal on-chip including, transforming the rising and the falling edges of the signal into a digital pulse signal each; and selecting the digital pulse signals corresponding either to the rising edge or to the falling edge of the signal. Further the method including converting the selected digital pulse signals into an average DC voltage equivalent to the pulse width of the respective digital pulse signal; as well as converting each DC voltage into a binary value.

Abstract: An apparatus comprises a plurality of driver circuits and a control registers block. The plurality of driver circuits may be configured to drive a read line in response to a memory signal and a reference voltage. The control registers block generally configures the plurality of driver circuits to implement an asymmetric voltage swing of the read line about a voltage level that is half of the reference voltage.

Abstract: A memory device includes a main driver and a pre-driver. The main driver provides an output signal to a host based on a plurality of driving signals. The pre-driver provides the main driver with the plurality of driving signals in order to calibrate a slew rate of the output signal based on an output resistance value of the main driver and a resistance value of an on-die termination circuit of the host. The pre-driver is configured to generate a first driving signal of the plurality of driving signals in response to an input signal regardless of a control signal, and to generate a second driving signal of the plurality of driving signals in response to the input signal and the control signal.

Abstract: A constant impedance switch dynamically manages switch impedance to eliminate or substantially reduce impedance glitches during switching events by stepping variable impedances through sequences of impedance values. As a result, VSWR may be reduced to or near 1:1, allowing programming and circuitry to be simplified. Switch impedance may be maintained for single and multi-throw switches having variable impedances of any order. Each variable impedance may comprise one or more configurable cells, subcells and elements controlled by thermometer, binary, hybrid or other coding technique.

Abstract: According to an embodiment, a semiconductor device includes: a first modulation circuit configured to generate a reference signal based on a first clock signal; a second modulation circuit configured to generate a feedback signal with a phase negative relative to a phase of the reference signal based on a second clock signal with a phase negative relative to a phase of the first clock signal; a comparator configured to compare the reference signal with the feedback signal to determine duty and generate a comparator signal; and a driver configured to output a drive signal.

Abstract: Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures are disclosed herein. An example method may include comparing a current channel state of a channel of a multi-level communication bus with a next channel state of the channel. The example method may further include, based on the comparison, applying an offset delay to a control signal configured to control transition of a signal line of the channel from a value associated with the current channel state to a value associated with the next channel state. The example method may further include after application of the offset delay, driving the signal line to the value associated with the next channel state responsive to the control signal.

Abstract: A method and apparatus are provided for balancing currents of two or more parallel-connected power semiconductor switches during an on-state of the switches. A control terminal of each switch is driven by a driver unit. The method includes determining ratios between the currents through the switches. For each switch, the method includes controlling the voltage at the control terminal on the basis of the ratios by controlling a level of a supply voltage of the driver unit of the switch, and after a turn-on commutation transient, modulating the output of the driver unit. The duty cycle of the modulation is controlled to minimize the time required for the transition of the voltage at the control terminal from the one voltage level to another.

Abstract: Methods and devices are disclosed driving one or more P-Intrinsic-N (PIN) diodes by receiving an input and generating a plurality of pulses based on the input, a first pulse of the plurality of pulses controls a rise time of an RF envelope generated by an RF interface and a second pulse of the plurality of pulses controls a fall time of the RF envelope generated by the RF interface. The methods and devices may further be disclosed combining the plurality of pulses to generate a drive signal, delivering the drive signal to the RF interface including one or more PIN diodes, and generating the RF envelope by driving the one or more PIN diodes with the drive signal, and the amplitude or a pulse width of the first pulse is independently adjustable from the amplitude or the pulse width of the second pulse.

Abstract: A voltage-mode transmitter includes a calibration circuit having a replica circuit. By adjusting a feedback voltage driving a gate of a replica transistor in the replica circuit so that an impedance of the replica circuit matches an impedance of a variable resistor, the calibration circuit calibrates an output impedance of a single slice driver.

Abstract: A level shifter circuit includes a level shifting unit configured to receive signals that may vary in a first range via a positive input terminal and a negative input terminal, respectively and to output signals that may vary in a second range to a positive output terminal and a negative output terminal, respectively, where the second range is larger than the first range, a first pre-charging unit configured to pre-charge the positive output terminal to a predetermined level when a clock is in a first level, and a second pre-charging unit configured to pre-charge the negative output terminal to the predetermined level when the clock is in the first level.

Abstract: An apparatus comprising a plurality of driver circuits and a plurality of control registers. The plurality of driver circuits may be configured to modify a memory signal that transfers read data across a read line to a memory controller. The plurality of control registers may be configured to enable one or more of the driver circuits. A pull up strength and a pull down strength of the memory signal may be configured in response to how many of the plurality of driver circuits are enabled. The plurality of driver circuits implement an asymmetric pull up and pull down of the memory signal.

Abstract: The present disclosure is applicable to electronic fields, and provides a voltage comparator. The voltage comparator includes a first branch, a second branch and a third branch. The first branch and the second branch both have self-biasing capabilities, and require no dedicated bias circuit. Under the same power voltage, the static power consumption of the voltage comparator is relatively low; fewer the power consuming branches exist in the circuit, and the reliability is high under low power consumption.

Abstract: An electro-static discharge (ESD) protection circuit utilizes a gate-drain breakdown characteristic of high electron mobility transistors (HEMTs) in a dual stacked configuration to provide a discharge path for electro-static discharges, while having a minimal effect on the associated circuit which is being protected.

Abstract: A pulse shaping circuit is configured to shape a waveform of an edge of a signal applied to a switch of a power amplifier included in an on-off keying transmitter.

Abstract: An apparatus, and method therefor, relates generally to a transmitter. In such an apparatus, a decoder is configured to receive a data input and control signals and to generate state signals responsive to a control signal of the control signals and data polarity the data input. Select circuitry is configured to receive coded signals to replace the data input with a pull-up code and a pull-down code of the coded signals responsive to the state signals and the control signals for propagation of the pull-up code and the pull-down code in place of the data input.

Abstract: Apparatuses and methods for adjusting timing of signals are described herein. An example method may include providing an output clock signal responsive to an input clock signal, and adjusting a slew rate of the output clock signal by a delayed output clock signal.

Abstract: A skew correction circuit includes: a phase-difference detection circuit that generates a phase difference signal indicating a phase difference between an edge of a first signal that is one signal of differential signals and an edge of a second signal that is another signal of the differential signals; and a correction-signal generation circuit that generates a correction signal having an inverted phase of the second signal by combining the phase difference signal and the first signal.

Abstract: A differential driving circuit according to embodiments of the inventive may include a first driver drives a first pad to a first voltage according to a first driving signal, a second driver drives a second pad to a second voltage according to a second driving signal, a first and second capacitors for receiving a first and second voltage changes of the first and the second pad at one end thereof respectively to transmit the first and the second voltage change to the other end thereof respectively in a transition interval in which voltages of the first and second pads are changed, transition interval voltage adder circuit adds voltages respectively transmitted thereto through the first and second capacitors, and a transition interval asymmetry compensation circuit adjusts a slope of at least one of the first and second driving signals according to the added voltage.

Abstract: A system includes a first transmitter, a second transmitter, a third transmitter and a controller, where the first transmitter is arranged for transmitting a first signal to a first transmission line, the second transmitter is arranged for transmitting a second signal to a second transmission line, and the third transmitter is arranged for transmitting a third signal to a third transmission line. The controller is coupled to the first transmitter, the second transmitter and the third transmitter, and is arranged for setting impedances of the first transmitter, the second transmitter and the third transmitter according to a coding jitter determination result.

Abstract: The present invention comprises a method and apparatus for controlling an IGBT device. The method comprises, upon receipt of a first and at least one further IGBT control signals, the first IGBT control signal indicating a required change in operating state of the IGBT device, controlling an IGBT driver module for the IGBT device to change an operating state of the IGBT device by applying a first logical state modulation at an input of an IGBT coupling channel, and applying at least one further modulation to the logical state at the input of the IGBT coupling channel in accordance with the at least one further IGBT control signal within a time period from the first logical state modulation, the time period being less than a state change reaction period ?t for the at least one IGBT device.

Abstract: Provided is a detection apparatus that detects process variation in a plurality of comparators that each output a comparison result obtained by comparing a signal level of an input signal to a reference level, the detection apparatus comprising a signal input section that inputs the input signal and the reference level in common to the comparators, and sequentially changes the signal level of the input signal; and a detecting section that detects, for each signal level, a number of comparison results that indicate a predetermined result, from among the comparison results of the comparators, and detects the process variation based on a distribution of the number of comparison results that indicate the predetermined result.

Abstract: An input apparatus includes: a touch sensor 11; a piezoelectric element 13; a piezoelectric element drive unit 15; a control unit 17 configured to detect a pressure load on the touch sensor 11 based on an output signal of the piezoelectric element 13 and, when the pressure load satisfies a standard to provide a tactile sensation, to control the piezoelectric element drive unit 15 to drive the piezoelectric element 13 such that the tactile sensation is provided to a pressing object; a connection switchover unit 14 configured to selectively connect the piezoelectric element 13 to the control unit 17 or the piezoelectric element drive unit 15; and a discharge circuit 16 configured to discharge electric charge in the piezoelectric element 13.

Abstract: A gate driver circuit for the power switch is disclosed. The gate driver circuit includes a resistor network coupled to the power switch. The resistor network includes a plurality of resistors and a control unit operatively coupled to the resistor network. The control unit detects an occurrence of a commutation phase and a saturation phase based on an identity of the power switch and corresponding time stamps associated with a start of a delay phase, the commutation phase, and the saturation phase. The control unit further controls the resistor network to provide different resistance values in at least two of a delay phase, a commutation phase, and a saturation phase when the power switch is transitioned to a first state. A method for driving the power switch is also disclosed.

Abstract: An image processing device performs image processing on an image being captured to display the image on a display unit having a resolution lower than a resolution of the image. The image processing device includes an extraction section that extracts an edge component from the image, an edge enhancing section that enhances the edge component by performing low-pass filter processing on the edge component after performing full-wave rectification processing on the edge component, a combining section that combines the enhanced edge component with the image to generate a composite image, and a resolution conversion section that performs resolution conversion of the composite image to match a resolution of the composite image with the resolution of the display unit.

Abstract: An integrated circuit can include at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; and a counter configured to generate a count value corresponding to a duration of the first pulse.

Abstract: Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.

Abstract: A memory controller includes a bus driver that allows the controller to support both a semiconductor memory device supporting a low power double data rate 3 (LPDDR3) transmission method and a semiconductor memory device supporting a low power double data rate 4 (LPDDR4) transmission method.

Abstract: A circuit includes a first set of transistors and a second set of transistors. The first set of transistors is configured to be turned on in a sequential manner. The second set of transistors is configured to be turned on in a sequential manner after the first set of transistors is turned on. A transistor of the first set of transistors corresponds to a first time delay. The first set of transistors corresponds to a second time delay that is a multiple of the first time delay.

Abstract: A reference output device includes a low side selector configured to select a first voltage level as an output signal. The output signal is a reference voltage. The reference output device also includes a high side selector configured to select a second voltage level as the output signal. The reference output device also includes a slew rate control configured to switch the output signal between the first voltage level and the second voltage level at a constant slew rate.

Abstract: A circuit for skew reduction, includes: first signal lines configured to transmit first signals delayed by first paths respectively; second signal lines configured to transmit second signals delayed by second paths respectively; and a first swap circuit, wherein the first swap circuit is configured to swap and connect the at least one of the first signal lines to the at least one of the second signal lines, when a mutual delay time difference of the second signals in a state where the at least one of the first signal lines is swapped and connected to the at least one of the second signal lines is smaller than a mutual delay time difference of the second signal lines in a state where the first signal lines is connected to the second signal lines without being swapped.

Abstract: An apparatus, comprising a load; an output FET having a drain coupled to the load; a first and second of a pair strong FETs, wherein: a) a source of the first of the pair of the strong FETs is coupled to the load; b) a drain of the first pair of the strong FETs is coupled to the source of the second of the of the pair of the strong FETs; the drain of the second pair of the strong FETs is coupled to a gate of the output FET; and a fixed current mirror is coupled to the gate of the first of the pair of the strong FETs.

Abstract: An exemplary differential output buffer includes a mixing stage and an output stage. The mixing stage includes a mixing circuit that mixes a differential data signal and an inverted delayed differential data signal to generate a mixed differential data signal. The output stage includes a first and a second output stage differential pair of transistors. Sources of the transistors in each of the output stage differential pairs are commonly coupled. Gates of the transistors in the first and second output stage differential pairs are supplied with the differential data signal and the mixed differential data signal, respectively. Drains of corresponding ones of the transistors in the first and second output stage differential pairs are commonly connected to form output nodes to output an emphasized differential data signal. The mixing stage includes a mixing ratio setting circuit that sets the mixing ratio to one of 1:0, 1:1, and 0:1.

Abstract: A circuit may include a detector, an approximator, a look-up table, a scaler, and an integrator. The detector may generate a first difference signal and a second different signal based on an input and an output. The approximator may generate, using a one's complement operation, an index based on approximated modulus values of the first difference signal and the second difference signal. The look-up table may select one of a plurality of scaling factors based upon the index. The scaler may adjust the first difference signal and the second difference signal based on the selected scaling factor. The integrator may generate the output based on the adjusted first difference signal and the adjusted second difference signal.

Abstract: An integrated circuit for switching a transistor is disclosed. In some embodiments, an operational amplifier is configured to drive a transistor, and slew rate control circuitry is configured to control the slew rate of the transistor source voltage during turn on. The transistor source voltage is employed as feedback to the operational amplifier to facilitate closed loop control of the transistor source voltage during switching of the transistor.

Abstract: The present invention pertains to a high speed duty cycle correction and double to single ended conversion circuit for PLL, comprising a reshaper stage, a single-edge detection circuit and a duty cycle restorer. The present invention introduces a way to convert double-ended output of PLL VCO into single-ended signal and adjust duty cycle of PLL VCO's output waveform by 50%, so that the circuit can output single ended clock signal with 50% duty cycle.

Abstract: A circuit includes a first power node at a first voltage level, a second power node at a second voltage level, a first voltage driver, a first current driver, and a control unit. The first voltage driver is configured to electrically couple a first output node to the first power node when a first input signal at the first input node is at a first logic state, and electrically couple a first output node to the second power node when the first input signal is at a second logic state. The first current driver is configured to inject or extract a first adjustment current into or out of a first output node. The control unit is configured to generate a measurement result of the first voltage level, and to set the first adjustment current according to the measurement result.

Abstract: To reduce power supply noises occurring in a control circuit unit for controlling an output buffer. A semiconductor device includes unit buffers for driving a data output terminal, impedance control circuits for controlling the unit buffers, and a control circuit unit for controlling the impedance control circuits. The impedance control circuits and the control circuit unit operate by mutually-different power supplies, the control circuit unit supplies pull-up data and pull-down data in mutually reverse phase to the impedance control circuits, and the impedance control circuits convert the pull-up data and the pull-down data from reverse phase to in-phase and supply the same to the unit buffers. Thereby, a noise is difficult to occur in a power supply VDD used for the control circuit unit.

Abstract: Apparatuses and methods are described that include a plurality of drivers corresponding to a single via. A number of drivers can be selected to operate individually or together to drive a signal through a single via. Additional apparatus and methods are described.

Abstract: Provided is a semiconductor apparatus which includes a plurality of output buffers configured to connect a plurality of power sources, and a data noise measuring unit configured to fix an output data of a selected output buffer among the plurality of output buffers to have a specific level, measure a noise of the output data using a capacitance and control a slew rate of the plurality of output buffers based on the noise.

Abstract: There is provided an apparatus for output buffering having a half-swing rail-to-rail structure. The apparatus provides output buffering by using a switch structure in order to attain a high slew rate and low power characteristics, thereby reducing current consumption. The provided apparatus for output buffering having a half-swing rail-to-rail structure includes a first output buffer, driven between a first voltage rail and a second voltage rail and outputting a first output signal in response to a first input signal and a second input signal, and a second output buffer, driven between the first and the second voltage rails and a third voltage rail and outputting a second output signal in response to a third input signal and a fourth input signal.

Abstract: A method for driving a controllable power semiconductor switch, having a first input terminal and first and second output terminals coupled to a voltage supply and a load, the first and second output terminals providing an output of the power semiconductor switch, includes adjusting a gradient of switch-off edges of an output current and an output voltage of the power semiconductor switch by a voltage source arrangement coupled to the input terminal. A gradient of switch-on edges of an output current and an output voltage is adjusted by a controllable current source arrangement that is coupled to the input terminal and generates a gate drive current. The profile of the gate drive current from one switching operation to a subsequent switching operation, beginning at a rise in the output current and ending at a decrease in the output voltage, is varied at most within a predefined tolerance band.

Abstract: A buffer circuit is provided. The buffer circuit includes an operational amplifier and a slew-rate compensating circuit. The operational amplifier amplifies an input voltage signal and generates an output voltage signal. The slew-rate compensating circuit generates a compensation current based on a voltage difference between the input voltage signal and the output voltage signal, and provides the compensation current to a load stage of the operational amplifier.

Abstract: Provided is a method for driving a semiconductor device, which allows a reduction in scale of a circuit, reduce the power consumption, and increase the speed of reading data. An H level (data “1”) potential or an L level (data “0”) potential is written to a node of a memory cell. Potentials of a source line and a bit line are set to the same potential at an M level (L level<M level<H level) so that the potential of the node is held. When the potential of the bit line is maintained at the M level, data “1” is read and when the potential of the bit line is reduced to an L level, data “0” is read.

Abstract: Disclosed is a high-swing voltage-mode transmitter or line driver. The transmitter can operate over a wide range of supply voltages. Increasing the available output swing merely involves increasing the supply voltage; the circuit adapts to maintain the desired output impedance. This allows for a tradeoff between output amplitude and power consumption. Another advantage of the proposed architecture is that it compensates for process, voltage, and temperature (PVT) and mismatch variations so as to keep rise and fall times matched. This feature reduces common-mode noise and hence EMI in systems in which the transmitter is used.

Abstract: A circuit configuration for the limiting of current intensity and/or the edge slope of electrical signals includes: a voltage source; a switching element connected to the voltage source and equipped for switching the voltage source; and a limiting unit functionally positioned between the switching element and the voltage source, the limiting unit being equipped to limit a current intensity and/or an edge slope of an electrical signal in response to a switching process of the voltage source while using the switching element.

Abstract: A semiconductor device driving unit to supply a drive signal to a gate of a semiconductor switching device, the semiconductor device driving unit comprising: a plurality of gate impedance circuits selectably connectable to the gate of the semiconductor switching device; and a selector to select one or more of the gate impedance circuits to connect to the semiconductor switching device. Also provided is a method of supplying a drive signal to a gate of a semiconductor switching device, the method comprising: selecting one or more of a plurality of gate impedance circuits to be connected to the gate of the semiconductor switching device based on one or more operating conditions and stored data relating to the one or more operating conditions; and connecting the selected one or more of the gate impedance circuits to the semiconductor switching device.

Abstract: An integrated circuit includes an output driver circuit having a plurality of output driver devices connected in a parallel arrangement and an output driver controller that is capable of individually controlling the conducting states of the output driver devices. In at least one embodiment, the controller is capable of achieving any of a plurality of different fall times (and/or rise times) in an output signal by appropriately controlling the conducting states of the output devices if a change in the state of the output signal is desired, in some implementations, the controller is capable of achieving different waveshapes during rising and/or failing edges of an output signal.

Abstract: Disclosed is a slew rate control device using a switching capacitor which includes a first capacitor that is connected to a target circuit operated in response to a clock signal, and controls a rising slope of a signal output from the target circuit when the clock signal is in a high state; a switch that is connected to the first capacitor in parallel, receives a reverse signal of the clock signal, as a control signal, and is turned on when the clock signal is in a low state; and a second capacitor that is connected to the switch in series, and controls a falling slope of the signal output from the target circuit when the clock signal is in the low state.