Abstract: A reference output device includes a low side selector configured to select a first voltage level as an output signal. The output signal is a reference voltage. The reference output device also includes a high side selector configured to select a second voltage level as the output signal. The reference output device also includes a slew rate control configured to switch the output signal between the first voltage level and the second voltage level at a constant slew rate.

Abstract: Data transmission circuits are provided. The data transmission circuit includes a control signal generator and an output driver. The control signal generator generates a pull-up control signal and a pull-down control signal by using a count signal that changes in response to a clock signal during a drive control period. The output driver receives an internal data signal and drives a transmission data signal in response to the pull-up control signal and the pull-down control signal.

Abstract: An apparatus, comprising: a NFET current mirror having a first NFET and a second NFET; a PFET gate-coupled to the drain of the second NFET, wherein the PFET has a larger gain than the second NFET; a driver NFET having a gate that is coupled to the drain the PFET; wherein the second NFET is coupled through its source to the drain of the driver NFET.

Abstract: The slew rate of a transistor is controlled. Upon a transition of a MOSFET control signal, an operating voltage of the MOSFET is measured and a determination of whether the voltage is between a predetermined set of values is made. Based upon the determination, a counter is incremented, and the count of the counter corresponding slew rate. The turn-on current of the MOSFET is controlled based upon the count.

Abstract: To provide reliable notification of a fault state when a power supply to a calculation processing portion is in the OFF state when a power supply to a communication processing portion is in the ON state. An isolating circuit, an inverting circuit inverting a signal branch-outputted through an output line of the isolating circuit, and a selecting circuit that uses the signal outputted from the output line of the isolating circuit as a first input and the inverted signal from the inverting circuit as a second input, to select either the first input or the second input, depending on a selection setting status thereof, to output the selected signal to the communication processing portion are provided. A +5 V voltage is applied through a resistor to the output line of the isolating circuit. This +5 V voltage is produced through the power supply supplied from the second double-wire transmission path.

Abstract: In accordance with these and other embodiments of the present disclosure, an apparatus and a method may include receiving a first input configured to indicate an output voltage of an output node of a switched output stage comprising a pull-down driver device coupled at its non-gate terminals between a ground voltage and the output node and a pull-up driver device coupled at its non-gate terminals between a supply voltage and the output node. The method may also include receiving a second input configured to indicate a gate voltage of a gate terminal of a first one of the pull-up driver device and the pull-down driver device. The method may further include detecting direction of an output current flowing into or out of the output node based on the first input and the second input.

Abstract: Disclosed herein is a device that includes: a first circuit configured to operate on a first power voltage to produce a first set of slew rate control signals; a second circuit configured to operate on a second power voltage to produce a second set of slew rate control signals in response to the first set of slew rate control signals; and a third circuit configured to operate on the second power voltage to produce a signal at a rate that is controllable in response to the second set of slew rate control signals.

Abstract: There is provided an apparatus for output buffering having a half-swing rail-to-rail structure. The apparatus provides output buffering by using a switch structure in order to attain a high slew rate and low power characteristics, thereby reducing current consumption. The provided apparatus for output buffering having a half-swing rail-to-rail structure includes a first output buffer, driven between a first voltage rail and a second voltage rail and outputting a first output signal in response to a first input signal and a second input signal, and a second output buffer, driven between the first and the second voltage rails and a third voltage rail and outputting a second output signal in response to a third input signal and a fourth input signal.

Abstract: A first transmitter transmits symbols. The leading edge of each symbol has the form Djexp{?jt}, where Dj is real, where ?j is selected from N possible values based on a current group of bits. The receiver has N filters whose transfer functions correspond respectively to the N possible values. The filter outputs are used to recover the group of bits. A second transmitter transmits an exponential symbol or a zero symbol depending on a current bit to be transmitted. The zero symbol has zero amplitude over the symbol period. The corresponding receiver applies threshold detection to estimate the transmitted bits. A third transmitter transmits a sequence of analog pulses with known interpulse time separation(s). The pulse sequence reflects from a moving object. A receiver captures the reflected pulse sequence. The interpulse separation(s) of the reflect pulse sequence is used to determine the radial velocity of the object.

Abstract: A semiconductor device includes a plurality of driving units configured to drive an output node based on an input signal and be on/off controlled based on driving force control codes, respectively, a slew rate control signal generation block configured to generate a slew rate control signal based on the driving force control codes, and a plurality of signal delay units configured to delay the input signal by respectively different delay amounts, transfer resultant signals to the plurality of driving units, and be respectively controlled in their delay amounts based on the slew rate control signal.

Abstract: An IC generally comprises enable pin, ground pin, input pin, output pin, load switch, control circuitry, and level shifter. Load switch is coupled between the input pin and output pin and receives a negative voltage through the input pin. The control circuitry is coupled to the enable pin, the ground pin, and the load switch and controls the load switch and uses ground pin as positive supply rail and input pin as an internal ground. Voltage applied to the input terminal is negative, enabling pulling of the gate of a transistor of a level shifter to ground turns transistor as “on,” enabling a negative output signal to be provided through output pin VOUT. Therefore, the output signal (at output pin VOUT) can be ground (applied to the ground pin GND) when the transistor is “off” and can be the negative voltage (applied to the input pin VIN) when transistor is “on.

Abstract: Provided is a semiconductor device with an output circuit in which a variation of a common voltage is suppressed in an idling mode and in a normal mode. The output circuit provided in the semiconductor device includes a first termination resistor and a second termination resistor and a drive circuit which flows current through the termination resistors. The output circuit is configured so as to be able to adjust the value of current which flows through the first termination resistor and the second termination resistor or the value of resistance of the first termination resistor and the second termination resistor.

Abstract: A method and circuit for implementing protection for complementary metal oxide semiconductor (CMOS) output drivers, and a design structure on which the subject circuit resides are provided. An output driver stage transistor stack includes a plurality of series connected PFETs series connected with a plurality of series connected NFETs connected between upper and lower voltage supply rails. A pair of offset DC voltage levels provides respective gate voltages of an intermediate PFET and an intermediate NFET in the output driver stage transistor stack. A pair of pre-driver circuits receiving voltage level translated logic signals drive respective gate inputs of the upper PFET and the lower NFET in the output driver stage transistor stack. A voltage feedback circuit provides respective gate voltages of the PFET and NFET connected together in the output driver stage transistor stack.

Abstract: An output signal adjustment system includes a signal adjustment unit, a reference slope generating unit, a slope detecting unit, a voltage-to-current conversion unit, and a control unit. The slope detecting unit compares the slope of the rising and falling edges of the output signal of the reference slope generating unit with that of the signal adjustment unit and outputs a voltage signal. The voltage-to-current conversion unit converts the voltage signal into a current signal. Based on the current signal, the control unit outputs a control signal for controlling the adjustment of the signal adjustment unit to the slope of the rising and falling edges of the output signal. The output signal adjustment system can automatically adjust the slope of the rising and falling edges of the output signal, so that the output signal is insensitive to the packaging, the printed circuit board, the transmission line and other sender loads.

Abstract: Apparatuses and methods are described that include a plurality of drivers corresponding to a single via. A number of drivers can be selected to operate individually or together to drive a signal through a single via. Additional apparatus and methods are described.

Abstract: An IC generally comprises enable pin, ground pin, input pin, output pin, load switch, control circuitry, and level shifter. Load switch is coupled between input pin and output pin and receives a negative voltage through the input pin. The control circuitry is coupled to the enable pin, the ground pin, and the load switch and controls the load switch and uses ground pin as positive supply rail and input pin as an internal ground. Voltage applied to the input terminal is negative, enabling pulling of the gate of a transistor of a level shifter to ground turns transistor as “on,” enabling a negative output signal to be provided through output pin VOUT. Therefore, the output signal (at output pin VOUT) can be ground (applied to the ground pin GND) when the transistor is “off” and can be the negative voltage (applied to the input pin VIN) when transistor is “on.

Abstract: A Local Interconnect Network (LIN) driver circuit employs a charging/discharging current applied to the gate of a driver transistor coupled to an LIN bus. The charging current includes a constant charging current and an additional soft charging current, whereas the discharging current includes a constant discharging current and an additional soft discharging current. As a result of the soft charge/discharge components, there is a significant reduction in electromagnetic emission on the LIN bus.

Abstract: A switching-element drive circuit that is configured to be applied to a power converter includes: a switching element; and a control unit that controls an operation of the switching element. The control unit includes a drive-voltage control unit that is configured to be capable of changing a switching speed of the switching element based on a power supply current.

Abstract: A switch controller is provided that uses one or more capacitors to generate a slow turn on/slow turn off switch control signals to suppress audible switching noise in an audio switch. In some embodiments, an analog inverter and a capacitor are used to generate the switch control signals, while in other embodiments two capacitors are used to generate the switch control signals. To conserve power between switching states, routing logic is provided that ties the switch control signals to respective voltage rails and disables selected portions of the switch controller.

Abstract: Embodiments are provided including one directed to an output driver system, having an adjustable pre-driver configured to maintain a generally constant slew rate of an output driver across a plurality of output driver impedances. Other embodiments provide a method of operating a memory device, including determining an output driver strength of an output driver and configuring the pre-driver based on the determined output driver strength.

Abstract: A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.

Abstract: A gate driver includes a control input receiving a control signal, an output to provide an amplified output signal to the gate, and controller. The controller produces an adaptive pulse train varying with the control signal. An adaptive incrementer produces a sequence of numbers that set a slew rate of the switch, and a look-up table is fed with the sequence of numbers, and associates the numbers produced by the adaptive incrementer with values representing the duty cycle of the output signal to control the slew rate of the switch. The switch can be driven at various intermediate levels, and allows gate drive conditions to adapted to abnormal system states by varying the control input signal. The adaptive response allows the slew rate to vary without replacing any gate driver circuit components. Because the gate current is provided adaptively, the delivery of gate current results in low power dissipation.

Abstract: This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are configured as a parallel array of complementary inverter pairs to provide a divided voltage to a calibrator. The calibrator is configured to respond to a differential voltage to adjust the divided voltage such that the differential voltage is forced to zero. The calibrator outputs a plurality of discrete signals from an up/down counter to toggle the individual transistors of the parallel array to increase and decrease a collective current. In some embodiments, transistor channel currents are modulated to step-adjust a voltage based on a ratio associated with a static resistance. In various embodiments, the divided voltage is an analog voltage based on a resistance associated with trim circuitry.

Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.

Abstract: An apparatus, comprising: a NFET current mirror having a first NFET and a second NFET; a PFET gate-coupled to the drain of the second NFET, wherein the PFET has a larger gain than the second NFET; a driver NFET having a gate that is coupled to the drain the PFET; wherein the second NFET is coupled through its source to the drain of the driver NFET.

Abstract: A gate line driver including an output buffer configured to receive a driving signal and output a driving voltage, and a slew rate controller including at least one capacitor and a switch connected in series to the at least one capacitor, the switch configured to selectively, electrically connect the at least one capacitor between an input terminal and an output terminal of the output buffer according to a slew rate control signal to control a slew rate of the output buffer.

Abstract: A switching circuit includes a first input stage having an input for receiving a first input signal, an output, and a power terminal for receiving an increasing analog current, a second input stage having an input for receiving a second input signal, an output, and a power terminal for receiving a decreasing analog current, and an output node coupled to the outputs of the first input stage and the second input stage for providing a switched output signal. An output stage is coupled between the first and second input stages and the output node. The first and second input stages are operational amplifiers.

Abstract: A switching device for driving a load is provided. The switching device comprises a control terminal and has a conduction threshold which, when crossed by a control signal coupled to the control terminal, causes the switching device to conduct. A control circuit for generating the control signal is also provided. The control circuit is configured to generate a control signal having a first slew rate prior to the control signal crossing the conduction threshold and a second slew rate after the control signal has crossed the conduction threshold. The first slew rate may be faster than the second slew rate.

Abstract: A method and apparatus to independently adjust the output rise and fall time of a transmitter for the purposes of improving high-speed signaling characteristics and reducing electromagnetic interference (EMI). Also described is an apparatus to provide a high-speed edge-rate control feature. The disclosed method and apparatus for rise and fall time equalization has a closed-loop calibration system that includes an actuation apparatus within the transmitter driver, a sensing means at the output of the transmitter to measure the degree of rise/fall time imbalance, and a calibration state machine operating on the sensor output to devise correction control inputs to the actuator in the transmitter driver to correct the rise/fall time imbalance. Also described is how the actuation apparatus within the transmitter driver can further be used to provide an open-loop edge-rate control feature for the transmitter.

Abstract: Disclosed is a wave shaping apparatus and a method for shaping an input pulse train signal alternating between a low level and a high level to provide a signal delaying a turn on of one output transistor with respect to a turn off of the other output transistor thus decreasing time, when both the transistors would be simultaneously conducting current.

Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.

Abstract: A power semiconductor device includes first and second power semiconductor elements connected in parallel to each other and a drive control unit. The drive control unit turns on or off each of the first and second power semiconductor elements in response to an ON instruction and an OFF instruction repeatedly received from outside. Specifically, the drive control unit can switch between a case where the first and second power semiconductor elements are simultaneously turned on and a case where one of the first and second power semiconductor elements is turned on first and thereafter the other thereof is turned on, in response to the ON instruction. The drive control unit turns off one of the first and second power semiconductor elements first and thereafter turns off the other thereof, in response to the OFF instruction.

Abstract: A source driver with an automatic de-skew capability is configured to receive a data signal and a clock signal from a timing controller, which are configured to drive a liquid crystal display panel. The source driver includes a signal delay unit, a setup time register, a hold time register, a first signal delay unit, a second delay unit and a logic circuit. In one embodiment of the present disclosure, the first data delay signal is configured to sample the second clock delay signal and the second data delay signal is configured to sample the first clock delay signal.

Abstract: A switching circuit device has a first transistor which has a drain coupled to a high-potential terminal, a source coupled to a low-potential power supply, and, a driving circuit, which outputs, to a gate of the first transistor in response to an input control signal, a pulse having a potential higher than a threshold voltage of the first transistor and a potential of the low-potential power supply, wherein the driving circuit has a first inverter including a second transistor provided between the gate and the source of the first transistor, wherein when the first transistor changes from on to off due to the pulse, the second transistor conducts and short-circuits the gate and the source of the first transistor.

Abstract: A switching device for driving a load is provided. The switching device comprises a control terminal and has a conduction threshold which, when crossed by a control signal coupled to the control terminal, causes the switching device to conduct. A control circuit for generating the control signal is also provided. The control circuit is configured to generate a control signal having a first slew rate prior to the control signal crossing the conduction threshold and a second slew rate after the control signal has crossed the conduction threshold. The first slew rate may be faster than the second slew rate.

Abstract: A semiconductor device according to the present invention includes an input circuit that is connected between an input node and an output node and that changes a level of the output node corresponding to a signal supplied to the input node, wherein when a control signal represents a first mode, a speed at which input circuit changes the level of the output node from a first level to a second level is greater than the speed at which input circuit changes the level of the output node from the second level to the first level and when the control signal represents a second mode, the speed at which input circuit changes the level of the output node from the second level to the first level is greater than the speed at which the input circuit changes the level of the output node from the first level to the second level.

Abstract: The slew rate of a transistor is controlled. Upon a transition of a MOSFET control signal, an operating voltage of the MOSFET is measured and a determination of whether the voltage is between a predetermined set of values is made. Based upon the determination, a counter is incremented, and the count of the counter corresponding slew rate. The turn-on current of the MOSFET is controlled based upon the count.

Abstract: A slew rate regulation circuit varies a slew rate of a waveform of a voltage outputted to a DC motor through a N-channel MOSFET. The slew rate regulation circuit lowers a peak level by dispersing frequency components of switching noise, which develops in a frequency range higher than a frequency range determined by a carrier frequency.

Abstract: A slope compensation module provides slope compensation of a switched-mode power supply using current mode control. The slope control unit comprises a capacitor coupled between an input and an output of the slope control unit, a switch for discharging the capacitor and a constant current source for charging the capacitor. Slope compensation parameters may be changed during operation with a programmable constant current source. The slope compensation module may also function as an analog sawtooth waveform frequency generator, and as an analog pulse width modulation (PWM) generator. Charging the capacitor generates a linearly decreasing (negative slope) ramp voltage for modulating a feedback error voltage into a slope compensated feedback error voltage. Capacitor charging may be controlled from a pulse width modulation signal. Opening of the switch may be programmably delayed, and a minimum closed time thereof may also be programmed during operation of the slope compensation module.

Abstract: A complementary output generator (COG) module generates at least two complementary outputs determined by rising and falling event sources. In a simple configuration of the COG module, the rising and falling event sources are the same signal which is a signal having the desired period and duty cycle. The COG module converts this single signal input into dual complementary outputs. The frequency and duty cycle of the dual outputs substantially match those of the single input signal. Blanking and deadband times may be introduced between the complementary outputs, and the dual complementary outputs may also be phase delayed. In addition the COG module may provide up to four outputs for controlling half and full-wave bridge power applications.

Abstract: Interconnections between signal lines help to reduce signal skew between signals carried on the signal lines. The interconnections may be resistive interconnections, and the signal lines may be clock lines. In a memory controller, for example, resistive traces may connect adjacent clock lines. The resistive traces reduce the clock signal skew between the adjacent clock lines, and throughout the memory controller as a whole.

Abstract: One embodiment relates a method of correcting skew and/or duty cycle distortion in a differential signal using a transmitter buffer circuit. Skew and/or duty cycle distortion may be detected in the differential signal. Delay times for at least two variable-delay buffer circuits are adjusted. The variable-delay buffer circuits may have outputs coupled to control gates of pull-up and pull-down transistors coupled to one or more output nodes of the transmitter buffer circuit. Other embodiments, aspects, and features are also disclosed.

Abstract: An output driver that includes a pull-up network comprising a first plurality of resistive branches forming a first R-2R resistive ladder structure, wherein the resistive branches of the pull-up network are coupled to a high voltage supply through pull-up switching transistors. The output driver may further include a pull-down network comprising a second plurality of resistive branches forming a second R-2R resistive ladder structure, wherein the resistive branches of the pull-down network are coupled to a low voltage supply through pull-down switching transistors. The output driver includes a control circuit to selectively activate or deactivate each of the first plurality of resistive branches and to selectively activate or deactivate each of the second plurality of resistive branches.

Abstract: An apparatus, comprising: a PMOS current mirror have a first PFET and a second PFET coupled at their respective gates; a first current source coupled to drain of the first PFET; a second current source configured to have a current that is greater than the first current source, coupled to the drain of the second PFET; a capacitor coupled to the gates of the PFET current mirror; a third PFET gate-coupled to the current mirror; a driver NFET having a gate coupled to the drain of the third PFET, wherein a drain of the driver NFET is coupled to the capacitor.

Abstract: Disclosed is a wave shaping apparatus and a method for shaping an input pulse train signal alternating between a low level and a high level to provide a signal delaying a turn on of one output transistor with respect to a turn off of the other output transistor thus decreasing time, when both the transistors would be simultaneously conducting current.

Abstract: An apparatus, comprising: a PMOS current mirror have a first PFET and a second PFET coupled at their respective gates; a first current source coupled to drain of the first PFET; a second current source configured to have a current that is greater than the first current source, coupled to the drain of the second PFET; a capacitor coupled to the gates of the PFET current mirror; a third PFET gate-coupled to the current mirror; a driver NFET having a gate coupled to the drain of the third PFET, wherein a drain of the driver NFET is coupled to the capacitor.

Abstract: A transmission channel configured to transmit high-voltage pulses and to receive echos of the high-voltage pulses includes a high voltage buffer, a voltage clamp and a switch. The voltage clamp may include clamping transistors and switching off transistors coupled together in series with body diodes in anti-series. The transmission channel may include a reset circuit configured to bias the transmission channel between pulses. The switch may include a bootstrap circuit.

Abstract: A driver device drives a load circuit by a common output signal from a first driver transistor and a second driver transistor. The driver device includes a first pre-driver unit that outputs a first driver control signal to the first driver transistor in response to the input signal; and a second pre-driver unit that outputs a second driver control signal to the second driver transistor in response to the input signal. The first pre-driver unit controls the first driver control signal in such a manner that the first driver control signal is rounded in the vicinity of a threshold of the first driver transistor and is sharply changed in a region exceeding the threshold.

Abstract: A circuit can compensate for intra pair skew or mode conversion in a channel by applying a second or corrective mode conversion effect that counters the channel's mode conversion. The circuit can process the common mode signal with a frequency dependent filter prior to injection back into the differential mode. The circuit can implement the reverse mode conversion with passive circuits using integrated resistors and metal oxide semiconductor (MOS) switches. In certain embodiments, such actions can proceed effectively without necessarily consuming active power.

Abstract: The contribution of noise to digitally sampled signals is reduced using a statistical processor and a slope limiter. The statistical processor determines an average value (mean and/or standard deviation) of the filtered signal which is used to determine a slope limit corresponding to an expected maximum first derivative value of a target signal frequency. This slope limit is applied to constrain the output of an analog to digital converter, to prevent the output of the analog to digital converter from exceeding this maximum rate of rise or fall. By constraining the output of the analog to digital converter, it is possible to digitally sample analog signals without first utilizing an anti-aliasing filter, since the post processing of the digitally sampled signals limits the contribution of the higher frequency components of the signal to thereby enable a fully digital sampling and filtering circuit to be provided for receiving signals.