Abstract: This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are configured as a parallel array of complementary inverter pairs to provide a divided voltage to a calibrator. The calibrator is configured to respond to a differential voltage to adjust the divided voltage such that the differential voltage is forced to zero. The calibrator outputs a plurality of discrete signals from an up/down counter to toggle the individual transistors of the parallel array to increase and decrease a collective current. In some embodiments, transistor channel currents are modulated to step-adjust a voltage based on a ratio associated with a static resistance. In various embodiments, the divided voltage is an analog voltage based on a resistance associated with trim circuitry.

Abstract: Multi-protocol driver slew rate calibration systems for calibrating slew rate control signal values are provided. Embodiments include generating, by a first phase rotator, a first clock signal; generating, by the second phase rotator, a second clock signal; initially setting, by a calibration controller, phase selector amounts such that the first clock signal is delayed relative to the second clock signal; determining whether the first clock signal is delayed relative to the second clock signal; if the first clock signal is delayed, changing the second phase selector amount; and if the first clock signal is not delayed, using the first clock signal and the second clock signal to calibrate values of control signals provided to control a slew rate of a calibration clock delay line such that the slew rate of the calibration clock delay line substantially matches a target slew rate.

Abstract: An apparatus comprising a first line driver, a second line driver, a charge pump, and a control logic circuit coupled to the first line driver and the second line driver and configured to disable the charge pump when both a first control signal associated with the first line driver and a second control signal associated with the second line driver indicate a charge pump disable state. A network component comprising at least one processor configured to implement a method comprising receiving a first control signal and a second control signal, disabling a charge pump when both the first control signal and the second control signal indicate a charge pump disable state, and operating the charge pump to boost a voltage when the first control signal, the second control signal, or both indicate a charge pump active state.

Abstract: A driver circuit suitable for outputting a signal onto an output line affected by conducted EMI, has a slope control circuit and an output circuit, (op-amp, Mo, M13 to M21). It can be used for driving a LIN network. The slope control circuit outputs a slope controlled version of the input signal to the output circuit, which (M6,M7) is arranged to reduce an amount of conducted EMI induced DC shift in the output circuit. This can involve clipping a feedback signal, and regulating an output stage of the op-amp to prevent the DC shift. Having a separate output circuit can help shield the slope control circuit from the EMI on the output line.

Abstract: An LIN transmitter includes a current mirror coupled to a transmit output node and a control circuit coupled to a transmit input node for controlling the current mirror with various load current control signals.

Abstract: A margin circuit for controlling skew between first and second signals in order to determine margin, includes a variable delay circuit and a margin controller. Based on a current code value, the delay circuit applies a delay to the second signal to generate a delayed second signal. The margin controller generates the current code value for the variable delay circuit to be any one of a plurality of available code values. In one embodiment, the margin circuit is a write margin circuit that generates a first clock signal and a delayed second clock signal used to generate transmit (TX) clock and data signals having a non-zero phase offset between them. In another embodiment, the margin circuit is a read margin circuit that applies a phase offset between receive (RX) clock and data signals to enable the RX clock signal to be used to recover data from the RX data signal.

Abstract: A slew rate control circuit configured to control a slew rate of driver circuit comprises a clock delay module that receives a half-rate clock signal and that includes a plurality of delay cells configured to generate a plurality of respective delayed clock signals each having a different time delay from one another. A driver module includes a plurality of multiplexers in electrical communication with a respective data cell to receive a corresponding delayed clock signal. The multiplexers are configured to output a respective full-rate data stream in response to the delayed clock signal. The slew driver module further includes an output stage circuit in electrical communication with each multiplexer to combine each full-rate data stream and to generate a final step-wise driving signal that controls the slew rate.

Abstract: Apparatuses and methods are described that include a plurality of drivers corresponding to a single via. A number of drivers can be selected to operate individually or together to drive a signal through a single via. Additional apparatus and methods are described.

Abstract: Provided is a method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data. The method includes the steps of: driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; and measuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result.

Abstract: A current mode controlled power converter controllable in a digitally processing current mode even during an on time. In the power converter, each control period based on a reference signal includes a slope calculation period in which a slope compensation signal for the control period is calculated by a slope compensation unit. During each slope calculation period, the slope compensation unit negates the slope compensation signal calculated previous to the control period including the slope calculation period, and a reset signal generation unit compares a current detection signal detected by a current detection unit with a current instruction set to an error signal generated by an error signal generation unit to generate a reset signal.

Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.

Abstract: An output driver circuit including a pre-driver stage that receives a first data signal, the pre-driver stage including a plurality of first differential pairs that perform current subtraction to output a second data signal based on the first data signal, and an output driver stage electrically coupled to the pre-driver stage that receives the second data signal from the pre-driver stage, the output driver stage including a plurality of second differential pairs that transmit an output signal along transmission lines.

Abstract: A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.

Abstract: A gate driver includes a control input receiving a control signal, an output to provide an amplified output signal to the gate, and controller. The controller produces an adaptive pulse train varying with the control signal. An adaptive incrementer produces a sequence of numbers that set a slew rate of the switch, and a look-up table is fed with the sequence of numbers, and associates the numbers produced by the adaptive incrementer with values representing the duty cycle of the output signal to control the slew rate of the switch. The switch can be driven at various intermediate levels, and allows gate drive conditions to adapted to abnormal system states by varying the control input signal. The adaptive response allows the slew rate to vary without replacing any gate driver circuit components. Because the gate current is provided adaptively, the delivery of gate current results in low power dissipation.

Abstract: A slew rate boost circuit for an output buffer and an output buffer circuit for a source driver having the same are provided. In an output buffer including a pull-up unit providing a buffer output signal in a first level by receiving a buffer input signal and performing pull-up operation and a pull-down unit providing a buffer output signal in a second level having opposite phase from the first level by receiving the buffer input signal and performing pull-down operation, the slew rate boost circuit includes a first comparator generating a first boost signal to boost pull-up operation of the pull-up unit of the output buffer by inputting a first input signal and a second input signal and a second comparator generating a second boost signal to boost pull-down operation of the pull-down unit of the output buffer by inputting the first input signal and the second input signal.

Abstract: Electronic chips with slew-rate control at output signals are disclosed. A disclosed electronic chip includes a slew-rate control circuit and slew-rate control charging and discharging transistors wherein the transistors are coupled at an output pin of the electronic chip. According to an input signal for an output stage of the electronic chip and a signal at the output pin, the slew-rate control circuit generates the slew-rate control charging and discharging signals to separately control the slew-rate control charging and discharging transistors to charge/discharge a load capacitance at the output pin.

Abstract: Aspects of the invention provide for equalizing rise and fall slew rates at an output for a buffer. In one embodiment, a method includes: measuring, simultaneously, rise and fall slew rates at an input of the buffer and rise and fall slew rates at the output of the buffer; generating a slew reference based on at least one of the rise slew rate or the fall slew rate at the input of the buffer; comparing the rise slew rate and the fall slew rate at the output of the buffer to the slew reference; and generating at least one of a rise control signal or a fall control signal for adjusting at least one of the rise slew rate or the fall slew rate at the output of the buffer.

Abstract: Clock signal timing cells, clock signal timing circuits, clock circuits, memory devices, systems, and method for altering the timing of a clock signal are disclosed. An example method for altering the timing of an output signal provided responsive to an input clock signal includes adjusting a transition of an edge of the output signal from one voltage level to another based at least in part on a bias signal. An example clock signal timing cell includes an inverter and a bias controlled inverter coupled in parallel to the inverter. The bias controlled circuit is configured to provide an output signal wherein a transition of a clock edge of the output signal between first and second voltage levels is based at least in part on a bias signal.

Abstract: An output buffer includes a pullup driver, a pulldown driver, and an output stage. The pullup driver has a drive control input, and an output for providing a pullup drive signal in a push-pull mode in response to receiving a first drive control signal on the drive control input, and in a current limited mode in response to receiving a second drive control signal on said drive control input. The pulldown driver has a drive control input, and an output for providing a pulldown drive signal in the push-pull mode in response to receiving a third drive control signal on the drive control input, and in the current limited mode in response to receiving a fourth drive control signal on the drive control input. The output stage provides a voltage on an output terminal in response to the pullup and pulldown drive signals.

Abstract: A circuit can compensate for intra pair skew or mode conversion in a channel by applying a second or corrective mode conversion effect that counters the channel's mode conversion. The circuit can process the common mode signal with a frequency dependent filter prior to injection back into the differential mode. The circuit can implement the reverse mode conversion with passive circuits using integrated resistors and metal oxide semiconductor (MOS) switches. In certain embodiments, such actions can proceed effectively without necessarily consuming active power.

Abstract: Aspects of the invention provide for equalizing rise and fall slew rates at an output for a buffer. In one embodiment, a method includes: measuring, simultaneously, rise and fall slew rates at an input of the buffer and rise and fall slew rates at the output of the buffer; generating a slew reference based on at least one of the rise slew rate or the fall slew rate at the input of the buffer; comparing the rise slew rate and the fall slew rate at the output of the buffer to the slew reference; and generating at least one of a rise control signal or a fall control signal for adjusting at least one of the rise slew rate or the fall slew rate at the output of the buffer.

Abstract: In examples, apparatus and methods are provided that mitigate buffer slew rate variations due to variations in output capacitive loading, a fabrication process, a voltage, and/or a temperature (PVT). An exemplary embodiment includes an inverting buffer having an input and an output, as well as an active resistance series-coupled with a capacitor between the input and the output. The resistance of the active resistance varies based on a variation in a fabrication process, a voltage, and/or temperature. The active resistance can be a passgate. In another example, a CMOS inverter's output is coupled to the input of the inverting buffer, and two series-coupled inverting buffers are coupled between the input of the CMOS inverter and the output of the inverting buffer.

Abstract: This document discusses, among other things, a system and method for reducing electromagnetic interference of a switched signal. In an example, a switched input signal can be received at an input and a transition rate of an edge rate controlled, switched output signal can be controlled in response to the received switched input signal.

Abstract: A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V2 from a first voltage V1; and a control circuit that generates the current control signal OVDR, makes a current that is flowed by the current mirror increase by a first transition of the current control signal OVDR, and makes the current that is flowed by the current mirror decrease by a second transition of the current control signal OVDR. The control circuit includes a slew-rate processing unit that makes a second slew rate of the current control signal OVDR related to the second transition be smaller than a first slew rate of the current control signal OVDR related to the first transition.

Abstract: Output driver feedback circuitry is configured to sense an amount of output capacitance of an output pad and to adjust the strength of the output driver accordingly. The feedback circuitry adjusts the output driver within a single cycle. A chain of delay reference signals is generated by representative capacitive loads that replicate a range of actual output loads. Adjustments to the output driver are based on a comparison of the delay reference signals with output of the output driver.

Abstract: A semiconductor device including, a slope signal generator configured to generate a slope signal, an error signal generator configured to generate an error signal in response to an output voltage, a pulse width modulation (PWM) signal generator configured to generate a PWM signal using a difference between the slope signal and the error signal, and a slope signal controller configured to adjust the slope signal according to a difference between the output voltage and a reference voltage.

Abstract: Disclosed is a high-swing voltage-mode transmitter or line driver. The transmitter can operate over a wide range of supply voltages. Increasing the available output swing merely involves increasing the supply voltage; the circuit adapts to maintain the desired output impedance. This allows for a tradeoff between output amplitude and power consumption. Another advantage of the proposed architecture is that it compensates for process, voltage, and temperature (PVT) and mismatch variations so as to keep rise and fall times matched. This feature reduces common-mode noise and hence electromagnetic interference in systems in which the transmitter is used.

Abstract: Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a signal generation circuit. The signal generation circuit is configured to generate a first output signal and a second output signal in response to a reference signal. The first output signal and the second output signal are a pair of complementary signals. The first output signal has first transitions of a first polarity and second transitions of a second polarity. The second output signal has third transitions of the second polarity that are simultaneous to the first transitions in the first output signal and has fourth transitions of the first polarity non-simultaneously corresponding to the second transitions in the first output signal.

Abstract: A gate drive circuit includes a turn-on circuit having an upper limiter for receiving a gate drive signal. The upper limiter has an output terminal. The turn-on circuit also has a transistor having a base connected to the output terminal of the upper limiter. In addition, the terminal has a terminal connected to a gate of a power switching device. The upper limiter limits a voltage input to the base of the transistor to not exceed a first predetermined value.

Abstract: A drive circuit includes a first transistor coupled in series with a second transistor at a first intermediate node coupled to a load. An amplifier has an output driving a control terminal of the second transistor. The amplifier includes a first input coupled to a second intermediate node and a second input coupled to a reference voltage. A feedback circuit is coupled between the first intermediate node and the second intermediate node. A slope control circuit is coupled the second intermediate node. The slope control circuit injects a selected value of current into the second intermediate node, that current operating to control the output of the amplifier in setting a slope for change in voltage at the first intermediate node.

Abstract: A bridge output circuit includes an output terminal, a high side transistor, a low side transistor, a high side driver for controlling a gate voltage of the high side transistor, a low side driver for controlling a gate voltage of the low side transistor, and a controller for controlling the high side and low side drivers. The low side driver includes a first current source, a second current source, and a first assist circuit. The controller is configured to control the turning-on and turning-off states of the first current source, the second current source and the first assist circuit.

Abstract: The semiconductor device includes an output driver and a characteristic switching circuit that switches characteristics of the output driver. The characteristic switching circuit mutually matches a rising time and a falling time of an output signal output from the output driver, when a power voltage supplied to a power line is a first voltage, with a rising time and a falling time of the output signal output from the output driver, when the power voltage supplied to the power line is a second voltage. As a result, an increase in an influence of a harmonic component or a crosstalk when the power voltage is reduced does not occur. Moreover, because a receiving condition on a receiver side does not change even when the power voltage is reduced, signal transmission and reception can be performed correctly irrespective of the power voltage.

Abstract: A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.

Abstract: An integrated circuit for achieving power reduction in a transceiver may include a jammer detector that determines an interference level corresponding to a received signal, and a transmit power detector that determines a required transmit power level for a transmitted signal. The integrated circuit may also include at least one of the following: a process monitor that determines process corners of components within the receiver and/or the transmitter, and a temperature monitor that determines a temperature of the receiver and/or the transmitter. The integrated circuit may also include a state machine. The state machine may transition the receiver from a high linearity mode to a low linearity mode if a set of operating conditions is satisfied. Similarly, the state machine may transition the transmitter from a high power mode to a low power mode if a set of operating conditions is satisfied.

Abstract: A system includes control circuitry configured to provide one or more control pulses in response to a command signal, the one or more control pulses being communicated from the control circuitry to associated circuitry via a connection. A detector is configured to detect a disturbing signal that mitigates reception of the one or more control pulses via the connection. The command signal is controlled to cause the control circuitry to provide one or more additional control pulses when the disturbing signal is detected by the detector to improve a likelihood of the reception of the one or more control pulses via the connection.

Abstract: A system is provided for generating an output clock used for N.5 modulus division. An edge-slip circuit accepts a modulus count, a divisor select signal, and a clock signal having a frequency greater than a modulus count frequency. The edge-slip circuit also has an input to accept an output clock signal, and an output to supply a clock slip signal (NE). An exclusive-or (XOR) has an input to accept a buffered clock signal (NF) and the clock slip signal (NE). The XOR has an output to supply the output clock signal. The output clock signal has a frequency equal to a buffered clock signal frequency, with no skipped clock edges, when the clock slip signal does not change logic levels. Alternatively, the output clock signal frequency is equal to the buffered clock signal frequency, with a skipped clock edge, when the clock slip signal changes logic levels.

Abstract: A reference current generating circuit includes a generator that generates a reference voltage, a bias generator includes plural transistors of a different conductive types from each other and generates a first bias voltage and a second bias voltage, respectively, a first output transistor and a second output transistor of a different conductive type that outputs a current corresponds to a reference current when the first bias voltage or the second bias voltage is supplied thereto, an input-output unit that one terminal connected between the first output transistor and the second output terminal and the other terminal connected to a load, and supplies current from the first output transistor to the load or from the load to the second output transistor, and a switch that turns on/off the first and the second output transistors based on the output voltage of the input-output unit.

Abstract: Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.

Abstract: A pulse generation circuit and method includes using digital signals to trigger a first and second varying analog signals and detecting when they reach one or more reference levels. In response to the first and second varying analog signals reaching one or more reference levels, a first and a second digital control signals are produced and provided as input to a pulser producing a voltage excitation pulse having a width and timing defined by the first and second digital control signals.

Abstract: A semiconductor device according to the present invention includes an input circuit that is connected between an input node and an output node and that changes a level of the output node corresponding to a signal supplied to the input node, wherein when a control signal represents a first mode, a speed at which input circuit changes the level of the output node from a first level to a second level is greater than the speed at which input circuit changes the level of the output node from the second level to the first level and when the control signal represents a second mode, the speed at which input circuit changes the level of the output node from the second level to the first level is greater than the speed at which the input circuit changes the level of the output node from the first level to the second level.

Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.

Abstract: A boosting circuit is provided which performs an appropriate boosting operation in accordance with load capacitance. In the boosting circuit, a slope control circuit is provided between a limiter circuit, which limits a high voltage obtained by a charge pump circuit to a desired boosted voltage VPP, and a discharge circuit, which makes the boosted voltage VPP drop quickly to a power supply voltage VCC after the completion of writing, to enable a boosting operation in an appropriate boosted-voltage reach time, by increasing the time taken to reach the boosted voltage VPP in the case where the load capacitance is low, while keeping the time taken to reach the boosted voltage VPP unchanged, irrespective of the presence/absence of the slope control circuit, in the case where the load capacitance is high as in the case of selecting the memory cells collectively.

Abstract: A signal shaper generates an output signal representing a binary sequence, the output signal being the time-dependence of a signal value F. The signal shaper is input a first signal value F0 and a different second signal value F1, and receives a sequence of data bits. If the state of a first data bit and the state of a second data bit differ, the signal shaper controls the signal value F to change monotonically from the first signal value F0 or the second signal value F1 at a first point in time via one or more intermediate values at intermediate points in time to the second signal value F1 or the first signal value F0 at a later second point in time. On the time interval from the first point in time to the second point in time, the output signal may be a monotonic step function.

Abstract: A power control device can generate control signals to control operation of power sources. Additional control signals control operation of load switches that can be connected to the power sources to provide secondary sources of power. The load switches can be turned in a gradual manner at rates that depend on the power sources to which they are connected. The outputs of the load switches can be monitored for overvoltage and undervoltage conditions relative to the power sources to which they are connected.

Abstract: A slew rate control circuit generates a slew-rate controlled clock signal from an input clock signal based on a feedback control mechanism. The feedback control mechanism uses the input clock signal duty cycle characteristics as a reference for controlling and maintaining an optimum slew rate for the slew-rate controlled clock signal. By using the input clock signal as a reference, the slew-rate controlled clock signal is dynamically measured and periodically adjusted over each cycle of the input clock signal.

Abstract: A high voltage drive circuit includes an edge detector for generating an edge detection signal by detecting edges of a first high side input signal and a first low side input signal, the edge detector providing a high side delay signal and a low side delay signal by delaying the first high side input signal and the first low side input signal, a dead time generator for generating a dead time signal indicating a preset dead time in response to the edge detection signal, and a driver comprising a drive signal generator for providing a high side output signal and a low side output signal by inserting the preset dead time based on the dead time signal into the high side delay signal and the low side delay signal.

Abstract: An apparatus for outputting data of a semiconductor memory apparatus, which is capable of varying the slew rate and the data output timing, includes a bias generator that generates a bias having a level corresponding to a set value, a slew rate controller that controls a pull-up slew rate or a pull-down slew rate of input data on the basis of the bias generated by the bias generator, and a data outputting unit that outputs data on the basis of the slew rate controlled by the slew rate controller. Therefore, it is possible to satisfy various operational conditions without changing the structure of the circuit and to correspond rapidly and appropriately whit a change in the system, which enables the applied range of the products to be extended.

Abstract: A receiver circuit includes a buffering unit configured to buffer an input signal and generate a buffering signal; a variation detection unit configured to generate a control signal according to a level of a reference voltage; a driving unit configured to drive the buffering signal and generate an output signal; and a compensation unit configured to control a slew rate of the output signal in response to the control signal.

Abstract: Circuits and methods to limit an in-rush current of a load circuit such as a processor are disclosed. A charge pump is used as driver for switches with pulse modulation width (PWM) control on the duty cycle of a clock. A clock generator generates a ramp signal with variable slope and a reference voltage. The slope of the ramp signal is dependent on the in-rush current of the switch. No dedicated slew rate driver or an external capacitor is required. The main building blocks are: a charge pump used as driver connected to single supply domain, one external (or internal) switch device, a single capacitive feedback between the switch device and the PWM control, and a PWM control comprising a fix frequency voltage triangular pulse generator with variable slope proportional to the in-rush current measurement.

Abstract: A circuit configuration for the limiting of current intensity and/or the edge slope of electrical signals includes: a voltage source; a switching element connected to the voltage source and equipped for switching the voltage source; and a limiting unit functionally positioned between the switching element and the voltage source, the limiting unit being equipped to limit a current intensity and/or an edge slope of an electrical signal in response to a switching process of the voltage source while using the switching element.