Abstract: A power-on reset circuit includes a capacitor, an inverter, a resistor and first and second transistors which are connected in series between a power supply line and ground. The electric current flowing through the resistor flow through the first and second transistors with a certain time delay because of an electric charge stored in the capacitor. A rising of a power supply voltage is applied to the inverter with a certain time delay when the power supply voltage goes up. According to the power-on reset circuit, a reset pulse can be generated regardless a speed of rising of the power supply voltage.

Abstract: A sensor with a dynamic latch comprising having a sensor coupled to a gain amplifier, a delay circuit connected to the gain amplifier and a summing circuit coupled through first and second nodes to the gain amplifier. The sensor with a dynamic latch further comprises an output stage coupled to a comparator circuit and the summing circuit and to third and fourth nodes and first and second energy storing devices coupled to the comparator circuit.

Abstract: The present invention relates to a power on reset circuit capable of stabilizing an operation of a chip by generating a reset signal regardless of a ramp up time of a power supply voltage, and includes a first means for controlling a potential of a first node to a first potential according to a potential of a second node, a second means for supplying the power supply voltage to be ramped up to the second node according to the potential of the first node, a third means for determining a potential of a third node by inverting and delaying the potential of the second node, a fourth means for controlling a potential of a fourth node to a second potential according to the potential of the third node, a fifth means for inverting and delaying the potential of the fourth node, a sixth means for outputting the potential of the third node to an output terminal according to an output signal from said fifth means and its inverted signal, and a seventh means for controlling a signal of the output terminal according to the

Abstract: A power on reset cell is disclosed capable of accommodating faster power cycling rates and providing better trip point control. When the input supply voltage ramps up, the output of the power on reset cell transitions when the input is greater than a predetermined value. The power on reset cell includes a discharge circuit that is capable of discharging a subcircuit of the power on reset cell when the input supply voltage ramps down so that the output of the power on reset cell is prevented from prematurely transitioning during a subsequent ramping up of the input due to any latent charge accumulated in the prior ramping up cycle. The discharge circuit allows the power on reset cell to undergo faster power cycling without providing an invalid output. Furthermore, the discharge circuit provides better control of the output trip point.

Abstract: A semiconductor integrated circuit device has a data storage section for storing mode setting data corresponding to products of a plurality of types, redundancy data, and so on. The redundancy storage section is made up of a nonvolatile transistor for storing the mode setting data corresponding to the products, the redundancy data, etc., a latch circuit for latching data read out from the nonvolatile transistor and generating a mode signal, and a transmission gate for transmitting the data from read out from the nonvolatile transistor to the latch circuit. The semiconductor integrated circuit device also has an internal voltage generator for generating an internal voltage. This internal voltage is used as the power supply voltage of the data storage section.

Abstract: The monitoring of multiple supply voltages of an integrated circuit is done using a single external capacitor connected to a pin of the integrated circuit. Part of the multiple supply voltages are externally generated and part are internally generated. The internally generated supply voltages may include different voltages with different signs. A logic signal indicating that all the supply voltages have reached pre-established values before enabling functioning of the integrated circuit is generated after an initial soft start phase of the turn-on process.

Abstract: A power loss detector for generating a signal indicating the need to switch from a main power supply to an auxiliary power supply responsive to detecting that the main power supply has dropped below a predetermined threshold.

Abstract: The present invention provides a mode setting determination signal generation circuit for generating a mode setting determination signal based on a power-on signal applied during power-up, including signal generation means for generating an output signal fixed either to a high or low level, a first logic circuit section for outputting a signal based on a NOR or OR logic between the output signal from the signal generation means and the power-on signal, a second logic circuit section for outputting a signal based on a NAND or AND logic between a power-on signal having a polarity opposite to that of the power-on signal and the output signal from the signal generation means, a third logic circuit section for outputting a signal based on a NAND or AND logic between a signal at a mode setting determination signal output terminal thereof and the output signal from the second logic circuit section, a transfer gate circuit section for outputting either the output signal from the third logic circuit section or a mode

Abstract: An electronic system, precharge circuit, and method for precharging system net. The system includes a plurality of devices. Each of the devices includes at least one I/O pin driven by an driver circuit. The system further includes a system net connected to at least one of the I/O pins of each of the plurality of devices. A precharge circuit suitable for connecting to the system net is provided. The precharge circuit includes a sense stage and a charging stage. The sense stage is configured to receive the system net voltage as an input and adapted to sense a system net voltage transition. The charging stage is connected to the system net and configured to receive an output of the sense stage. The sense stage is configured to activate the charging stage in response to detecting a system net voltage transition. The charging stage, upon activation, is configured to provide a current path between a supply voltage and the system net for a specified duration.

Abstract: A power-up-reset circuit draws zero standby current. Rather than use a voltage divider that always draws current, a capacitive-pullup divider is used as the first stage. The capacitive-pullup divider has a capacitor to power (Vcc) and n-channel series transistors to ground. A sensing node between the capacitor and n-channel series transistors is initially pulled high to Vcc as Vcc is ramped up. The n-channel transistors remain off until Vcc reaches about 1.5 volts. Then the n-channel transistors pull the sensing node quickly to ground, ending the reset pulse. The second stage has a capacitor to ground that initially holds a threshold node low. A p-channel transistor has a gate connected to the sensing node and charges up the capacitor when the sensing node falls to ground. A third stage is triggered to change state as the capacitor is charged up by the p-channel transistor. Then a Schmidt trigger toggles, as do downstream inverter stages.

Abstract: A /POR circuit which can detect a power-on of a power supply voltage without fail even in a case where a potential of the power supply rises gently and which produces a /POR signal having a waveform sufficient for initializing internal circuits, as well as a semiconductor device having the /POR circuit. In a power-on reset circuit, a first line potential monitoring circuit and a second line potential monitoring circuit detect a line potential, and there is provided in a /POR signal waveform generation circuit a setting circuit which outputs a pulse signal in response to the results of such detection and operates in response to the pulse signal. Even when the potential of a power-on reset signal rises gently at power-on, the power-on reset signal can be brought to an activation potential without fail, thereby initializing internal circuits.

Abstract: The invention relates to a control circuit for a bias source including a stand-by device and a starting-aid device, with their respective outputs connected to a control input of the bias source, the starting-aid device including a switch to inhibit its operation, controlled by the bias source, said circuit including capacitive means for reactivating the starting-aid device when the “Stand-by” control signal changes state, indicating that the bias source should be reactivated.

Abstract: A digital power-up reset circuit is disclosed which provides a pulse of a predetermined width after a period of time after power-up. Because the power-up circuit is digital, it can be easily implemented in an integrated circuit. Moreover, it is relatively invariable to differences in manufacturing processes from device to device, in contrast to conventional analog (e.g., RC time constant based) power-up reset circuits, which have widely varied output pulses from device to device, and which are highly susceptible to variances in output pulse width due to changes in ambient temperature. The digital power-up reset circuit includes a first linear feedback shift register which starts up in an arbitrary state, and a second linear feedback shift register which defines a desired length of an activation of an output reset signal.

Abstract: According to the present invention, in an integrated circuit device for receiving an external clock signal and a clock enable signal and for supplying to an internal circuit an internal clock signal which has a predetermined phase relationship with the external clock signal, a DLL circuit for generating a delay clock signal, synchronized and in phase with the external clock signal, is operated continuously even in a low power consumption mode, and the provision of the delay clock signal to the internal circuit is halted. When the mode is switched from the low power consumption mode to the normal mode, the delay clock signal generated by the DLL circuit, which is operated continuously, is supplied as an internal clock signal to the internal circuit again.

Abstract: There is disclosed an electronic circuit comprising a clock driver for generating a clock signal, a clock line on which the clock signal generated by said clock driver is transmitted, a shield-cum-signal line extending along said clock line serving optionally for transmission of a predetermined signal and for shielding of a noise generated from said clock line in accordance with a mode, a transfer gate for transferring a transmitted signal to said shield-cum-signal line, said transfer gate turning on or off in accordance with a mode, and a transistor disposed between said shield-cum-signal line and a power source, said transistor turning on when said transfer gate turns off and turning off when said transfer gate turns on in accordance with a mode.

Abstract: A novel structure and method are taught for fully discharging a capacitor and thereby reducing the capacitance needed to achieve a desired RC time constant. The invention overcomes the previously encountered problem of using a large and area-inefficient capacitor. The invention allows for conservation of integrated circuit space and is cost effective.

Abstract: A regulated voltage supply contains a zener diode controlled by a constant current generator to maintain the zener voltage at a constant level regardless of the swings of the voltage input to the diode. A current amplifier responds to the constant current generator to maintain the output voltage of the regulated voltage supply at the value of the zener voltage regardless of the demands of the load. A low voltage inhibit circuit responds to the magnitude of the input voltage and the magnitude of the voltage on the zener diode to generate a binary voltage signal for inhibiting the operation of a load such as a microcomputer when the voltage regulator is below the zener voltage level and the input is below the desired voltage.

Abstract: A method and apparatus for a power-on reset system is provided. The power-on reset system comprises a voltage sense circuit for determining whether a voltage level is above a threshold and a write/rewrite verifier circuit for determining whether the voltage level is high enough to write to and rewrite a memory cell content. A power-on reset pulse emitted by the power-on reset system if the voltage level is above the threshold and high enough to write to and rewrite the memory cell. For one embodiment, this is system generates an initial POR pulse upon power-up but can thereafter be selectively disabled and consume zero power.

Abstract: A neutralization device is provided that is designed to block the operation of an electronic circuit when this device is insufficiently supplied. The device is designed especially for electronic circuits supplied with low supply voltages. The neutralization device comprises, upline with respect to an inhibiting means to block the operation of the electronic circuit, a control circuit reproducing the critical path or the potential critical paths of the functional electronic circuit in the form of elementary circuits. The deactivation of the inhibiting means is done only when the totality of the elementary circuits deliver same-state elementary signals indicating that the supply voltage is sufficient to ensure their efficient operation. The invention is useful in fields requiring low supply voltages such as mobile telephony or portable microcomputers.

Abstract: An LVDS interface for a programmable logic device uses phase-locked loop (“PLL”) circuits to provide data clocks for data input and output. The PLL clocks are highly accurate and each includes a multiply-by-W counter so that a multiplied and an unmultiplied clock are available. The multiplied clock is used to clock data into or out of a shift register chain serially. The unmultiplied clock is used to load or read the registers in the shift register chain in parallel. Providing both the multiplied and unmultiplied clocks from a single PLL assures that the clocks are in proper phase relationship so that the serial inputting or outputting, and the parallel loading or unloading, are properly synchronized.

Abstract: A power-on reset circuit employs all-CMOS circuitry to initiate a reset signal when the circuit's power supply voltage is low, and terminate the signal in response to the supply voltage exceeding a reference voltage by at least the greater of the threshold voltages of PFET and NFET transistors employed in the circuit. A diode-connected bipolar transistor is implemented with an FET-compatible circuit structure to establish the reference voltage, which compensates for the possibility of fabrication tolerances.

Abstract: A delay locked loop (DLL) is described comprising: a delay unit configured to delay an input clock signal by a specified amount to produce a delayed clock signal, said specified amount controlled by a control voltage applied to said delay unit; and a switch configured to clamp said control voltage to a predetermined value when said DLL is reset.

Abstract: A first latch circuit (15) and a control latch circuit (16) are used to control another circuit (18) in a self-timed circuit arrangement (10). The first latch circuit (15) produces a first latch circuit output signal (L1) responsive to a first clock signal (C1) in a multiple-clock system. The control latch circuit (16) responds to the second clock signal (C2) to latch the first latch output signal (L1) and produce a reset control signal which is used to produce both a reset signal (RE) and a control output signal (L2). The reset signal (RE) resets the first latch circuit (15), while the control output signal (L2) may be used to control the other circuit (18) even after the first latch circuit is reset.

Abstract: A power-on reset circuit reduces power consumption and layout area by utilizing a time delay to deactivate a reset circuit and clamp a reset signal a period of time after a power supply voltage has reached a predetermined level. The reset circuit includes a reset signal generator which maintains the reset signal in an active state until the power supply voltage has reached the predetermined level. The reset signal generator then deactivates the reset signal which causes a delay circuit to begin a time delay after which a delay signal is asserted. The delay signal deactivates a comparator in the reference voltage generator, a voltage detector, and a reset signal generator within the reset circuit, thereby reducing power consumption. The delay signal also activates a clamp circuit which clamps the reset signal to an inactive state.

Abstract: A shut-off circuit included in a dynamic flip-flop isolates output terminals of the dynamic flip-flop from circuitry within the flip-flop that could introduce noise on either output terminal during a portion of the evaluation phase. Since the output terminals are isolated from the input terminals during this portion of the evaluation phase, spurious input signals have no affect on the output signal levels. Similarly, charge within the dynamic flip-flop that is not completely dissipated in the transition from a precharge phase to the evaluation phase has no affect on the output signal levels during this portion of the evaluation phase.

Abstract: The present invention provides a voltage detecting circuit comprising: at least a low voltage detecting circuit for detecting that a power voltage is lower than at least a predetermined reference voltage; at least a high voltage detecting circuit for detecting that the power voltage is higher than the at least a predetermined reference voltage; and a controller being connected to the at least a low voltage detecting circuit and the at least a high voltage detecting circuit for detecting that the power voltage is higher than the at least a predetermined reference voltage; and a controller being connected to the at least a low voltage detecting circuit and the at least a high voltage detecting circuit so that the controller receives an output signal from the at least a high voltage detecting circuit in order to place the at least a low voltage detecting circuit into selected one of operable and inoperable states in accordance with the output signal from the at least a high voltage detecting circuit.

Abstract: An apparatus detects the loss of an asynchronous input signal and generates a reset signal that is synchronous to a system clock signal. The apparatus detects the loss of the input signal and generates a first output signal. The first output signal is delayed by a predetermined number of clock cycles, and a second output signal is generated to indicate a sustained loss of the input signal. A signal monitoring circuit is provided to confirm the loss of the input signal and generate a third output signal. The reset signal is generated only if the signal loss is both sustained and confirmed. Accordingly, the apparatus will not be unnecessarily reset as a result of noise that delays or accelerates the arrival of an edge of the asynchronous input signal.

Abstract: A power-on reset circuit for a dual-supply system. The reset circuit includes a voltage divider powered by the first power supply and a sub-circuit supplied by the second power supply. The output of the voltage divider is connected to a control node of the first reset sub-circuit that is otherwise powered by the second power supply. A second reset sub-circuit is strictly regulated and powered by the second power supply. The first reset sub-circuit provides for translation of a signal having a potential limited by the potential of the first supply into a signal having a potential associated with that of the second supply. Only when a control signal from the voltage divider reaches a certain potential, and the second power supply reaches a certain potential, is the first reset sub-circuit activated in a manner that results in a circuit output signaling both supplies are at a suitable potential. This is useful for hot insertion applications in dual-supply systems.

Abstract: A circuit for ensuring stabilized configuration information upon power-up is disclosed. In one embodiment, a semiconductor device includes a configuration information stored in a number of nonvolatile storage elements (fuse bits (16)). A configuration power-on reset circuit (10) generates a signal for latching the configuration data into volatile configuration registers (18) on power-up. The configuration data signals are generated in response to a power-on reset (POR) pulse, and not latched until a predetermined delay after the POR pulse is terminated. The predetermined delay allows time for the data signals from the fuse bits (16) to “settle.” Subsequent POR pulses will not result in another latching action.

Abstract: An apparatus for supervising input voltages of a multi-rail power supply includes a corresponding voltage detector unit electrically connected to each rail for ascertaining values of the input voltages of each rail. An output of each voltage detector unit is electrically connected at a wired-or node. A pull-up resistor is connected between the wired-or node and a power supply for pulling the voltage level of the wired-or node high. Circuitry generates a power-good signal responsive to the voltage of the wired-or node being greater than a predetermined threshold voltage.

Abstract: A power-up detection circuit to produce a power-up detection signal detects a reference voltage of a device. After a power-up detection has been produced, a DC current path to ground is established to conduct DC current to reset the power-up detection circuit to produce a subsequent power-up detection signal.

Abstract: An integrated circuit including a DC sensing power-up reset (PUR) circuit and method for generating a reset signal. The PUR circuit comprises a first terminal for receiving a supply voltage and a second terminal for receiving a reference voltage corresponding to a low logic state. A first transistor is coupled between the first terminal and a first node, wherein the first transistor switches on when the supply voltage is rising and exceeds a rising trip point voltage. A second transistor is coupled between the first terminal and the first node, and switches off when the supply voltage falls below a falling trip point voltage which is less than the rising trip point voltage. A first inverter is coupled at an input terminal to the first node and at an output terminal to a second node. A resistor is coupled between the first node and the second terminal.

Abstract: A power on reset includes a latch controller and a latch circuit. The latch controller sets the latch circuit to an initialization state when a power supply voltage is less than a first threshold voltage during power-up, so that a power on reset signal from the latch circuit has the power supply voltage, a logical high level (i.e., goes to a logically activated state). The latch controller resets the latch circuit when the power supply voltage becomes higher than a second threshold voltage which is higher than the first threshold voltage, so that the power on reset signal goes to the ground voltage Vss, a logical low level (i.e., goes to a logically inactivated state). According to such a circuit configuration, even though the power supply voltage oscillates around a voltage at a point in time when the power on reset signal transitions from the power supply voltage to the ground voltage, the power on reset signal continues to be maintained at a previous set state.

Abstract: The invention provides a power-on circuit which assures a high impedance state of a terminal of an IC until the IC starts its operation after a point of time immediately after a power supply voltage is made available to the IC. The power-on circuit is built in a synchronous IC memory and includes a ring counter, an output controlling circuit, and a pulse signal interruption circuit. The ring counter successively generates a pulse signal after a power supply voltage begins to be supplied to the synchronous IC memory. The output controlling circuit controls an output terminal of the synchronous IC memory to a high impedance state while the pulse signal generated by the ring counter is inputted to the output controlling circuit. The pulse signal interruption circuit interrupts the pulse signal from being inputted to the output controlling circuit after a clock signal is inputted to the pulse signal interruption circuit.

Abstract: An apparatus is used to control a reset function of an electronic device. The apparatus includes a circuit adapted to monitor a system voltage level and deliver a control signal in response to the system voltage level falling below a first preselected value. A duration controller receives the control signal and delivers a first reset signal for a preselected duration of time after receiving the control signal. A voltage level controller receives the first reset signal, and delivers a second reset signal that persists until the system voltage rises above a second preselected magnitude.

Abstract: A zero static power laser fuse circuit is formed from one laser fuse and three transistors, with the fuse connected in series to a reverse-biased diode and with the common node of the fuse and diode connected to the input of a driving circuit, such as a CMOS inverter. Blowing the fuse allows a small subthreshold conduction current to flow to the common node and pull the node to the opposite logic state. This fuse circuit, which allows the capacitance at the common node to be minimized for zero static power operation, requires less circuit area than previous zero static power fuse circuits.

Abstract: A method and apparatus for compensating for input threshold variations in input buffers is provided. The method and apparatus compensate for input threshold variations by applying a bias voltage on a known capacitance of an RC calibration circuit using, for example, a pulse width modulator. The bias voltage helps ensure that the time to charge the known capacitance from the bias voltage to the input threshold voltage of the input buffer is independent of the threshold voltage. The bias voltage is chosen using an iterative process in which the time to charge from the bias voltage to the threshold voltage is compared with a reference time. The bias voltage is adjusted based on the comparison.

Abstract: Power-on-reset logic is included within an integrated circuit. The power-on-reset logic includes a power-on-reset cell. The power-on-reset cell causes a reset signal to be issued upon a power signal being connected to the integrated circuit. The power-on-reset cell includes a power down input connected to a power-down line. When a power-down signal is placed on the power-down line, the power-on-reset cell is inactivated so that the power-on-reset cell does not cause the reset signal to be issued upon the power signal being connected to the integrated circuit. The power-on-reset logic also includes a logic block connected to the power-down line and to a system clock. The logic block issues a reset when the power-down signal is placed on the power-down line and the system clock is active. For example, the logic block is a delay (D) flip-flop having a D input connected to the power down line and a clock input connected to the system clock.

Abstract: An electronic system is described for a flip-flop circuit having a data input stage with a clock input and a data input, coupled to an output stage which generates at least one data output, a reset circuit coupled to said data output stage for resetting the logic state of the data outputs to a predetermined desired condition, and a shutoff circuit coupled to said data input stage blocking data input from being acted on by said data input stage. An alternate embodiment includes a data processing circuit with a feedback mechanism coupled with the reset circuit of the flip-flop which informs the flip-flop that data is no longer required.

Abstract: Integrated circuit devices having metastability protection circuits therein include a main active circuit and a metastability detection/prevention circuit. The main active circuit may comprise a comparator, a sense amplifier, a differential amplifier or a voltage generating circuit, for example. The metastability detection/prevention circuit performs the function of detecting whether an output of the main active circuit has been disposed in a metastable state for a duration in excess of a transition duration. The output of the main active circuit may be considered as being in a metastable state if a potential of the output signal equals VMS, where VMS is in a range between VIL, and VIH. If the output signal has been in a metastable state for a duration in excess of the transition duration, then the metastability detection/prevention circuit will generate a control signal at a designated logic level.

Abstract: When a voltage of a voltage source increases higher than a predetermined value, a reset signal generation circuit generates a power-on reset signal for a battery charger. In the reset signal generation circuit, power for an output circuit is supplied from a divided point between a voltage source and a ground, which power is stabilized by a voltage stabilizer circuit. Since the power for the output circuit is supplied from the divided point, a fluctuation of the voltage of the power for the output circuit is reduced compared to that of the voltage source. Moreover, the voltage stabilizer circuit prevents an erroneous reset signal for the battery charger from being generated due to the voltage fluctuation of the voltage source.

Abstract: A power-on reset circuit for resetting the register values contained on an integrated circuit upon power-up of the integrated circuit. The power-on reset circuit can be implemented either internal or external to the integrated circuit. The power-on reset circuit generates a reset signal as long as the supply voltage is not in the operational range and maintains the reset signal for a certain time after the supply voltage has returned to its nominal value. The power-on reset circuit also provides accurate detection of a serious supply voltage drop and has low power consumption. The power-on reset circuit comprises a battery, a voltage-referenced switching circuit, a current source, a capacitor and a voltage buffer.

Abstract: The circuit arrangement has two electrical quantities in the form of a first quadrature-axis current component (I.sub.1) and of a second quadrature-axis current component (I.sub.2) that are compared to one another. The circuit arrangement has a first inverter unit (n.sub.1, p.sub.1) and a second inverter unit (n.sub.2, p.sub.2). Respectively one output (50, 52) of the two inverter units ((n.sub.1, p.sub.1, (n.sub.2, p.sub.2)) are coupled to an input of the respectively other inverter unit (52, 53). A reset unit (5) that initiates the comparison of the currents when activated is located between the two outputs of the two inverter units (n.sub.1, p.sub.2). When the reset unit (5) is deactivated, the output datum obtained in the evaluation remains stable.

Abstract: OCD circuitry is provided for an integrated circuit having a split rail power supply providing a first and a second voltage. The OCD circuitry comprises a tristate logic circuit adapted to control the OCD and a detection circuit coupled to the tristate logic circuit and adapted to generate an inactivation signal that inactivates the OCD if the first voltage is low. The detection circuit preferably comprises a comparator that compares the first voltage to the second voltage, and that generates the inactivation signal if the first voltage is less than the second voltage. To prevent the inadvertent inactivation of the OCD circuitry, the detection circuit preferably is provided with a filter that sets a minimum time period that the first voltage must be low before the detection circuit generates the inactivation signal and thus inactivates the OCD circuitry.

Abstract: A fabrication- and temperature-independent power-on reset circuit for providing improved control over live insertion of integrated circuitry. The reset circuit includes a comparator having an output terminal and two input terminals, one positive and one negative. One of the two terminals is coupled to a first threshold turn-on branch and the other terminal is coupled to a second threshold turn-on branch. Both threshold branches are referenced to ground but they supply different initial potentials to the terminals of the comparator. As a result, one terminal acting as the reference terminal holds the circuit output of the present invention at a potential designed to halt circuit power-on regardless of independent enable control pin signals. The other of the two terminals does not trigger switching of the comparator output until after a common supply power rail reaches a desired potential at initial turn-on.

Abstract: An output logic setting circuit includes a fusible fuse element which is selectively rendered disconnected by external signal operation. The output logic setting circuit is designed to output, from an output terminal, a change in logic output state when the fuse element is rendered disconnected. The output logic setting circuit includes an inverter circuit which is arranged between the fuse element and the output terminal and which has a threshold set to ensure proper circuit operation even if the blown fuse element returns to an apparent connected state over time.

Abstract: To form a means preventing a logic circuit from outputting wrong data at uncontrolled, unstable state of power turn-on in a control circuit. The control circuit has two logic circuits therein and takes negative OR or negative AND of output thereof. A first input terminal is connected to an input of an inverter circuit and a second logic circuit; the output of the inverter circuit is connected to the input of the first logic circuit; a second input terminal is connected to the first logic circuit and the second logic circuit; outputs of the first logic circuit and the second logic circuit are connected to inputs of a gate circuit; the output of the gate circuit is connected to a output terminal; and the first logic circuit and the second logic circuit output the opposite level to each other, positive and negative.

Abstract: An internal voltage generator is disclosed.

Abstract: An isolation method and circuit for providing dc isolation between two circuits that may have different reference potentials. There is provided a control circuit having an output terminal for providing a reset signal of predetermined length on the output terminal. A circuit to be controlled having an input terminal is provided, the circuit to be controlled being reset when a signal on the input terminal is below a predetermined threshold. A capacitor is coupled between the output terminal and the input terminal, the plate of the capacitor directly coupled to the circuit to be controlled being normally at a relatively high voltage. A voltage source is coupled to the input terminal of the circuit to be controlled through the parallel combination of a resistor and circuitry for unidirectional transmission of current toward the voltage source, generally a diode.

Abstract: A power edge detector includes a voltage divider, a pull-up circuit, and a cut-in pull-down circuit. The voltage divider receives and divides an input power voltage so as to generate a divided voltage. The pull-up circuit receives the input power voltage and transmits the input power voltage to an output terminal when the input power voltage does not exceed a predetermined threshold. The cut-in pull-down circuit is connected to the voltage divider and the pull-up circuit for pulling down the voltage level of the output terminal in response to the divided voltage when the input power voltage exceeds the predetermined threshold.