Abstract: A power-on reset circuit and method for generating a reset signal according to the voltage of a power source. The circuit includes an oscillator for generating an oscillation signal. The frequency of the oscillation signal increases with the rising of the voltage of the power source. The circuit further includes a frequency detector for converting the oscillation frequency of the oscillation signal into a first output voltage, and includes a reset signal output circuit for outputting a reset signal according to the first output voltage. Therefore, the power-on reset circuit can be applied in low-voltage chips.

Abstract: A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.

Abstract: Systems and methods for creating a limited duration clock divider reset are disclosed. Aspects of the invention may include a method for resetting a chip or a circuit. The method may include buffering a main reset input signal, inverting the main reset input signal to create an active high reset signal, resetting a counter utilizing the active high reset signal, comparing a counter output value and a counter-associated value in a comparator to obtain a comparator output value, and applying an OR logical operation to the comparator output. A limited duration clock divider reset may be generated from the output of the OR logical operation. The OR logical operation may be applied to the buffered main reset input signal. The comparator output may be inverted.

Abstract: In a standard Flash EPROM, a plurality of flash memory cells are arranged in an array of rows and columns. In order to determine the programming state of each cell, the magnitude of the cell read current is measured using a reference current source set to approximately 25 uA. The memory cell being examined is connected with the drain wired to a positive voltage between about 1 to 2 volts. The source of the memory cell is connected to the current source. The control gate voltage is set to approximately 5V. An unprogrammed memory cell will have a drain current equal to that of the reference current source and the cell output will be slightly less than the drain voltage (logic 1). Under these conditions, a programmed memory cell, having a higher threshold voltage, will conduct only leakage currents. This results in the cell output being very close to ground potential (logic 0). Older technologies utilized fixed current sources for the reference current.

Abstract: An integrated circuit may be initialized by determining that the supply voltage is ramping up and resetting logic in the integrated circuit to a predetermined initial state using a reset signal. After the logic is determined to be in its initial state and the supply voltage is established, the reset signal may be latched off. A pulse generator includes circuits that prevent the pulse generator from being reactivated until after a power cycle.

Abstract: A low voltage pull-down circuit for maintaining a node at a logic LOW voltage is provided. When a logic LOW is desired, the circuit provides a low-impedance path from the node to ground. The node may be easily pulled-up to a logic HIGH voltage, for example, by simply removing the low-impedance path and allowing a voltage source to reach the node through a resistor or transistor.

Abstract: In a clock-synchronized serial communication device, a counter counts pulses in a communication clock signal. When the count reaches 8, the counter sets a start signal. With this start signal, a pulse generator outputs the first to fourth signals successively. Received data stored in a receiving shift register is transferred to a received-data processing circuit synchronously with the first signal. The received data is further transferred to a timer-setting value register as a timer-setting value synchronously with the second signal. A timer present value is output from a timer present value register synchronously with the third signal. The timer present value is further written into a transmitting shift register as transmission data synchronously with the fourth signal.

Abstract: Systems and methods are disclosed for a power-on reset used in low power supply voltage applications (i.e., having a full operating power supply voltage of less than about 2.0 volts). One embodiment of the reset circuit comprises a differential voltage generation circuit and an amplifier circuit. The differential voltage generation circuit is adapted to create two voltages changing at different rates. The amplifier circuit is adapted to amplify a difference between the two voltages.

Abstract: A supply noise compensation circuit. The supply noise compensation circuit senses the onset of dI/dt noise events on a supply line and selectively gates off/forces on a chip clock to chip circuits.

Abstract: Devices, circuits, and methods generate a substantially constant output voltage. A power storage element generates a DC output voltage from an input voltage. The output is sampled to generate a feedback signal. An error amplifier generates an error signal from the feedback signal and a reference voltage. A ramp generator generates a ramp signal from the error signal. A comparator generates a pulse signal by comparing the ramp signal to a threshold voltage. The pulse signal is used to control a power switch, which switches the power storage element on and off. The pulse signal is generated such that, if the input voltage changes within a certain range, a width of its pulses changes so as to maintain the output voltage substantially constant.

Abstract: A power-on reset (POR) circuit determines when integrated circuit voltages and/or currents have reached predetermined levels and provides trigger signals to control the POR transition of the integrated circuit.

Abstract: A circuit for use with a pulse width modulated integrated circuit having a soft-start reset function comprising a diode having a first terminal connected to a soft-start reset terminal of the integrated circuit, a voltage divider coupled between a voltage reference and a common terminal for the integrated circuit, the diode having a second terminal coupled to a tap of the voltage divider and a soft-start capacitor coupled between the second terminal of the diode and the common terminal whereby upon power startup of the integrated circuit, the soft-start capacitor is charged by the tap of the voltage divider and wherein in the event of a single event upset condition, when the soft-start reset terminal of the integrated circuit is reduced to a level at or near the level of the common terminal of the integrated circuit, the diode prevents the soft-start capacitor from discharging through the integrated circuit.

Abstract: A power-on reset circuit which outputs a power-on reset signal through an output node includes a first signal generator that generates a first signal voltage. The first signal voltage increases from a ground voltage when a power supply voltage reaches a first threshold voltage. A second signal generator generates a second signal voltage, and the second signal voltage decreases from the power supply voltage when the power supply voltage reaches a second threshold voltage. A comparator activates the power-on reset signal responsive to a comparison of the first and second signals.

Abstract: A start-up circuit includes a power supply node which receives a power supply voltage, a ground node which receives a ground voltage, a first node, a first capacitor which is coupled between the first node and the ground node, a supply circuit which is coupled between the power supply node and the first node, and which supplies an electrical charge from the power supply node to the first capacitor, a discharge circuit which is coupled between the first node and the ground node, and which discharges an electrical charge stored in the first capacitor to the ground node, and an output circuit which is connected to the first node, and which outputs a start-up signal when a voltage level of the first node becomes higher than a set voltage level.

Abstract: When a power supply is turned off its output voltages decrease over certain times. If the power supply is turned back on before the output voltages have had time to decrease to a level required by certain electronic circuits before power is reapplied, then these electronic circuits may malfunction or latch-up. A power supply shutdown control monitors voltage levels of the power supply. The power supply shutdown control prevents the power supply from being turned back on before the output voltages have reached a sufficiently low voltage level. A voltage reset monitor determines when a power supply voltage drops below a certain level, and then a memory device stores the instance of a power supply voltage drop and uses the stored instance to prevent the power supply from being turned on until the monitored voltage(s) have reached the sufficiently low voltage level. Then, the stored instance is reset and the power supply may be re-energized.

Abstract: A brown-out detector that continuously monitors power supply voltage and provides an output signal that transitions to a logic HIGH state when the monitored power supply voltage exceeds a predetermined threshold value. One embodiment of the present invention comprises a first voltage reference with respect to ground that varies in direct proportion to absolute temperature, a second voltage reference with respect to the supply voltage that varies inversely with absolute temperature, and a comparator having the first voltage reference coupled to one input, and the second voltage reference coupled to the other input, such that the comparator output changes state when the power supply voltage exceeds a predetermined threshold voltage that is relatively independent of absolute temperature. The circuit may also be configured such that the first voltage reference varies inversely with absolute temperature, while the second voltage reference varies in direct proportion to absolute temperature.

Abstract: An integrated circuit comprising a circuit block whose power supply is controlled by waiting operation, is supplied which is able to prevent the occurrence of penetrating electricity caused by unstable signals output from the circuit block whose power supply was broken. In the integrated circuit, a mask signal is set at “L” level before a power in the circuit block is broken, a latch circuit formed by a NAND and an inverter keeps a node in “L” state, then when the power supply is broken and drops into “L” level, the output signal of the NAND is fixed in “H” level. Thus, from the circuit block, even if a unstable mask signal is output, the node keeps in “L” level, so that gate circuits become off.

Abstract: A power-on detector includes a reference potential generation circuit which generates a reference potential, and a comparator which compares the first voltage generated on the basis of the reference potential output from the reference potential generation circuit and the potential of the first potential supply source, and the second voltage generated on the basis of the reference potential and the potential of the second potential supply source different from the potential of the first potential supply source. Power-on is detected when the potential difference between the potentials of the first and second potential supply sources upon power-on becomes larger than the sum of the first and second voltages.

Abstract: DC voltage VREF produced in an LSI and having a value between power supply voltage VDD and the ground potential is applied to the gate electrode of pMOS transistor QP1 which forms a function determination circuit. Since the gate voltage of a transistor QP1 is lower than that in a conventional function determination circuit, current through the transistor QP1 is reduced. Hence, the gate length of the transistor QP1 can be reduced. When a second pMOS transistor is connected in parallel to the transistor QP1 so that the transistor has a function for supplying charge to junction A when power is fed to the LSI, the area of the transistor QP1 can be further reduced. When a voltage produced for a purpose other than for the function determination circuit such as a step-down power supply of the LSI is used as DC voltage, the area of the transistor can be reduced.

Abstract: A voltage sensing circuit includes a bandgap generator that generates a bandgap voltage, and a monitoring unit that determines whether the bandgap generator is adequately powered. The bandgap voltage is used as a reference voltage for comparison with a voltage to be sensed; alternatively, a separate reference voltage is derived from the bandgap voltage. In the latter case, the circuit that derives the reference voltage amplifies the bandgap voltage, using a differential amplifier biased according to a bias voltage derived from the bandgap generator, and has a compensation circuit for compensating for amplifier offset due to variations in the bias voltage. In either case, if the monitoring unit decides that the bandgap generator is inadequately powered, it forces the sensing result signal to a fixed state, avoiding the output of erratic sensing results.

Abstract: The apparatus for generating a driving voltage for a sense amplifier has at least voltage output means, and first and second core voltage step-up means. The voltage output means outputs a voltage for driving the sense amplifier to a node. Each of the first and second core voltage step-up means are connected between a power supply and the node. The first and second core voltage step-up means are turned on in sequence to elevate the voltage level of the node connected with the sense amplifier up to the level of the power supply. This enhances the performance of the sense amplifier as well as the execute detection amplification in a short time period. The first and second core voltage step-up means are turned on in sequence to elevate the core voltage as the driving voltage, reducing the power noise. Each core voltage step-up driver may be installed in each bank to reduce power consumption.

Abstract: A power-up circuit comprises a first PMOS transistor connected between the power supply and a first node, wherein a gate terminal of the first PMOS transistor is connected to the ground, a first voltage divider for dividing the power upon a power up, a first NMOS transistor driven an output of the first voltage divider upon a power up and connected between the first node and the ground, an inverter having a plurality of PMOS transistors connected between the power supply and a second node, in which gate electrodes of the plurality of inverter are connected from each other and a second NMOS transistor connected between the second node and the ground and gate of the second NMOS transistor is connected to the plurality of the PMOS transistors, thereby inverting the potential of the first node, and a third NMOS transistor connected between the first node and the ground, wherein the third NMOS transistor is turned on by an output of the inverter, thereby preventing shifting faster than the potential of the first n

Abstract: A voltage level detection circuit (1) with a threshold level, which is dependent on the manufacturing process. The circuit comprises a first current generator (4), which generates a monitoring current (IM) derived from the voltage (VM) to be monitored. This monitoring current (IM) is compared with a reference current (Iref1). A switchable reference current (Iref2) provides for hysteresis. The first current generator (4) comprises an element, the resistance of which depends on the manufacturing process.

Abstract: In accordance with one embodiment of the present invention, a circuit provides power stability functions for a microcontroller, during startup and normal operations performing power on reset functions and an array of power stability functions. The power on reset functions hold the microcontroller in a safe reset condition, reinforce the POR hold, and force its switch mode pump to drive up voltage provided to its common supply source. The power stability functions constitute a power on reset function, a power supply health, e.g., power state condition monitoring function, a control function for dynamically controlling the common supply source, and auxiliary functions, which may be protective of a flash memory. The power on reset function operates at a fixed and/or programmably changeable voltage levels. In one embodiment, the POR circuit is interconnected with a processor through a bus, enabling programmatic processor control of microcontroller power through interaction with the POR circuitry.

Abstract: An apparatus comprising a first arbiter cell, a second arbiter cell and a selection device. The first arbiter cell may be configured to lock if one or more requests are not resolved within a first predetermined time period. The second arbiter cell may be configured to dominate if the first arbiter cell enters a metastable state. The selection device may be configured to provide arbitration between the first and second arbiter cells within a second predetermined time period.

Abstract: A method and system dynamically controlling microcontroller power. In one embodiment, the method and system configures a microcontroller power state, senses its condition, and determines its suitability status, communicates that status between a POR circuit and a processor, controls certain microcontroller functions accordingly, and dynamically programs power related functions. This is enabled, in one embodiment, by dynamic interaction between the POR circuit and the processor. Microcontroller power status is ascertained, and a corresponding optimal power state determined. Optimal values for programmable independent multiples of a supply voltage is programmatically calculated and set, dynamically adjusting microcontroller power states. In one embodiment, the optimal values are communicated to a scaler in the POR circuit by the processor, and registered within a multiplexer/register matrix within the scaler.

Abstract: A power monitor circuit for notifying processing circuits operating from a first power supply (VDD) that a second power supply (VDDIO) is powered up. VDDIO is greater than VDD. The power monitor circuit comprises: 1) a voltage divider circuit coupled between the second power supply and ground having an output node that goes high when the second power supply is powered up; and 2) an odd number of serially connected inverters operating from the first power supply. An input of a first serially connected inverter is connected to the voltage divider circuit output node. An output of the last serially connected inverter produces a status signal that is the inverse of the voltage divider circuit output node. The status signal is an input to the voltage divider circuit that minimizes the voltage divider circuit—s current consumption when the second power supply is ON, while maintaining the status signal value.

Abstract: A circuit for controlling an initializing circuit in a semiconductor device is described herein. The circuit comprises a first circuit configured to generate a NOP operation command signal, and a second circuit configured to maintain a power-up signal to a LOW state until the NOP operation starts and to shift the power-up signal to a HIGH state based on the NOP operation command signal.

Abstract: Methods and apparatus implementing techniques for prevention of metastability in a bistable circuit. The techniques include detecting a change in a data signal, sampling the detected change in reference to a sampling window of a clock signal input of a bistable circuit to determine if the detected change occurs within the sampling window, and selecting a stable data input to present to an input of the bistable circuit based on whether the detected change occurs within the sampling window. The sampling window represents a time period during which a change in the data signal can cause metastability in a bistable circuit.

Abstract: A power-on management system for an on-chip voltage down-converter, monitoring both external and internal voltage supplies to independently determine when both supplies have reached minimum levels for proper operation of on-chip circuitry. The power-on management system supplies output signals that: control the discharge of the internal supply nodes at the initiation of power-on; force the active mode of the voltage down-converter; and deactivate a fast local voltage reference on completion of power-on.

Abstract: An apparatus comprising a margin logic circuit, one or more discriminator circuits and a sense circuit. The margin logic circuit may be configured to receive a plurality of requests and present one or more control signals. The one or more discriminators may be configured to (i) present one or more leading access signals and (ii) receive the one or more control signals and the plurality of requests. The sense circuit may be configured to receive the one or more leading access signals and the plurality of requests and present grant access signal. The sense circuit may be configured to reduce the effects of metastable conditions.

Abstract: The semiconductor integrated circuit is provided with a plurality of sub reset signal generators and a main reset signal generator. The sub reset signal generators respectively generate sub power-on reset signals whose timings differ from each other. The main reset signal generator generates a main power-on reset signal according to at least one from any of the sub power-on reset signals. Therefore, even where the characteristics of elements constituting the semiconductors integrated circuit change due to changes in the manufacturing conditions of the semiconductor integrated circuit, one of the sub power-on reset signals is generated at a normal timing. As a result, the main reset signal generator is able to generate a main power-on reset signal by using a normal sub power-on reset signal. That is, it is possible to constitute a power-on resetting circuit having a wide operation margin, wherein the internal circuits can be initialized without fault.

Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

Abstract: A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.

Abstract: A circuit includes a second switching unit, a first switching unit that is connected to and selectively actuates the second switching unit, and a capacitive voltage divider including first, second and third capacitances connected in series. The first and second switching units are connected respectively to first and second junctions between the first and second and the second and third capacitances respectively. An associated method involves applying a supply voltage to the voltage divider so as to charge the first and second junctions, discharging the first junction through the first switching unit, which, dependent on the voltage of the first junction, selectively actuates the second switching unit to supply an additional charging current to the second junction. A time-limited signal such as a power-on reset signal is tapped from the first or second switching unit or from the second junction. Thereafter, the circuit draws no further current.

Abstract: As a power-supply voltage VCC is applied to a second terminal, a latch is reset by a reset signal POR from a power-on reset unit. Subsequently, as the voltage of a signal IN applied to a first terminal is increased to higher than the voltage VCC by a threshold voltage Vth of a PMOS 11, the PMOS 11 turns on, causing a node N1 to become “H.” Thus, a test mode is set in the latch. Subsequently, even if the signal IN is reduced to VCC or lower, the test mode is maintained. A high-voltage test can be conducted by increasing the power-supply voltage at the second terminal, thereby eliminating the need for applying the first terminal with a higher voltage than required to set the test mode. It is therefore possible to prevent a gate oxide film of a buffer from being destroyed.

Abstract: The semiconductor integrated circuit has a power-on resetting circuit for activating a reset signal which initializes an internal circuit, for a predetermined period after a power supply is switched on, and then inactivating the reset signal. The inactivation timing of the reset signal is changed by a timing changing circuit. Therefore, the inactivation timing which has deviated due to fluctuations in the manufacturing conditions of the semiconductor integrated circuit can be adjusted to a normal value. This consequently allows reliable initialization of the internal circuit. In general, a power-on resetting circuit utilizes the threshold voltage of transistors to generate the reset signal. Here, the inactivation timing depends on the threshold voltage of the transistors. Changing the inactivation timing corresponding to the threshold voltage of the transistors implemented makes it possible that the timing changing circuit optimally adjusts the inactivation timing of the reset signal.

Abstract: A POR circuit includes a signal generator which has a PMOS transistor and a first and second resistors connected in series. The PMOS transistor is controlled in accordance with a DPWD signal. A first signal obtained by dividing a voltage difference between the ground voltage and the supply voltage is output from a first node between the first and second resistors. The POR circuit also includes an edge generator which includes a third resistor and an NMOS transistor connected in series, and an inverter coupled to a second node between the third resistor and the NMOS transistor. The NMOS transistor is controlled in accordance with a voltage of the first signal output from the first node. When the NMOS transistor turns on, a second signal having an edge waveform is generated at the second node, the first inverter outputs a third signal which is a reversal of the second signal.

Abstract: A transient rejecting system for protecting the state of a memory is described. The transient rejecting system includes a signal transfer circuit and a charge storage circuit coupled to at least one pin of a circuit. The signal transfer circuit receives a supply signal and determines when a transient event occurs. When a transient event occurs, the charge storage circuit provides a signal to the pin of the circuit maintaining the state of the memory prior to the transient. During normal operation, the charge storage circuit is charged, and the supply signal is provided to the pin of the memory circuit. P-channel FETs are used in the signal transfer circuit and allow for low voltage operation of the transient rejecting system.

Abstract: A circuit and method for the input of a start signal, a controller being transferred from a first state into a second state as a function of the start signal, the energy consumption of the controller in the second state being greater than in the first state, the circuit having a clocked energy source which emits a timed energy signal, and the start signal is formed as a function of the energy signal.

Abstract: Circuits and methods for generating a reset signal are disclosed. A reset driver circuit receives a reset signal from a circuit, e.g., a reset generator and an input signal indicative of a required characteristic of a reset signal for a second circuit. The reset driver compares a characteristic of the reset signal with the input signal indicative of a required characteristic of a reset signal for a second circuit and generates an output signal that includes the required characteristics of the reset signal for a second circuit. A reset driver circuit may be placed in a communication path between a conventional reset generator and a second circuit that requires a reset signal.

Abstract: A circuit for use with a pulse width modulated integrated circuit having a soft-start reset function comprising a diode having a first terminal connected to a soft-start reset terminal of the integrated circuit, a voltage divider coupled between a voltage reference and a common terminal for the integrated circuit, the diode having a second terminal coupled to a tap of the voltage divider and a soft-start capacitor coupled between the second terminal of the diode and the common terminal whereby upon power startup of the integrated circuit, the soft-start capacitor is charged by the tap of the voltage divider and wherein in the event of a single event upset condition, when the soft-start reset terminal of the integrated circuit is reduced to a level at or near the level of the common terminal of the integrated circuit, the diode prevents the soft-start capacitor from discharging through the integrated circuit.

Abstract: A VDD power-up detection circuit is provided having a p-channel transistor having a source coupled to a VDD voltage supply terminal and a gate coupled to a ground supply terminal. A first resistor or a diode element is coupled between the drain of the p-channel transistor and the ground supply terminal. An n-channel transistor has a source coupled to the ground supply terminal and a gate coupled to the drain of the p-channel transistor. A second resistor is coupled between a drain of the n-channel transistor and the VDD voltage supply terminal. A trigger circuit is coupled to the drain of the n-channel transistor. As the VDD supply voltage increases during power-up, the p-channel and n-channel transistors are both turned on. At this time, the trigger circuit asserts a control signal that enables an associated circuit to operate in response to the VDD supply voltage.

Abstract: MOS transistors A and B form a transistor circuit (an inverter in this case). A MOS transistor D is one for interrupting leakage current that has a channel length longer than those of the MOS transistors A and B. Under the action of an enable terminal (Enable), the MOS transistor D conducts only while the circuit is operated, and does not conduct and thereby interrupts leakage current while the circuit is in a standby state. A MOS transistor C does not produce effect while the circuit is operated, and makes the potential of an output terminal (Output) a high potential or a low potential (not intermediate potential) only while the circuit is in the standby state. Therefore, the circuit controls unnecessary through-transistor current of a standby type circuit in a succeeding stage, which current is conventionally caused at an intermediate potential during standby.

Abstract: An integrated circuit comprising a circuit block whose power supply is controlled by waiting operation, is supplied which is able to prevent the occurrence of penetrating electricity caused by unstable signals output from the circuit block whose power supply was broken. In the integrated circuit, a mask signal is set at “L” level before a power in the circuit block is broken, a latch circuit formed by a NAND and an inverter keeps a node in “L” state, then when the power supply is broken and drops into “L” level, the output signal of the NAND is fixed in “H” level. Thus, from the circuit block, even if a unstable mask signal is output, the node keeps in “L” level, so that gate circuits become off.

Abstract: When a driving unit (100) charges gate input capacitance (6) of an IGBT (7), the gate input capacitance (6) accumulates electric charges which are accumulated therein when the driving unit (100) discharges the gate input capacitance (6). Therefore, it is possible to reduce the amount of electric charges to be supplied to the gate input capacitance (6) by the driving unit (100) until the charge of the gate input capacitance (6) is completed. As a result, it is possible to reduce the required power capacity of a control power supply (15a). Further, since the electric charges accumulated in the gate input capacitance (6) are effectively used, it is possible to ensure power savings of a semiconductor device.

Abstract: A synchronous circuit comprising a first flip-flop which has a first clock input terminal inputting an input signal, a first output terminal outputting a first output signal based on the input signal, a second output terminal outputting a second output signal based on the input signal and a first data input terminal inputting the second output signal; a second flip-flop which has a second clock input terminal inputting a clock signal, a reset terminal inputting a reset signal, a third output terminal outputting a third output signal based on the clock signal and the reset signal, a fourth output terminal outputting a fourth output signal based on the clock signal and the reset signal and a second data input terminal inputting the fourth output signal; a third flip-flop which has a third clock input terminal inputting the third output signal of which voltage level is reversed, a fifth output terminal outputting a fifth output signal based on the reversed third output signal, a sixth output terminal outputting

Abstract: A wake-up circuit for a ECU on a ECN utilizes two complementary switching transistors which will turn ON when there is a differential voltage between CANH and CANL which will turn ON the transistors to pass a current which will be mirrored over to create a voltage which will switch a comparator or a Schmitt trigger. The two signals are then ORed together to generate a digital wake-up signal that can be utilized by other on-chip circuitry.

Abstract: A data-sampling strobe signal generator and an input buffer using the same. The data-sampling strobe signal includes a intermediate signal generator, a comparison circuit and a logic circuit. The intermediate signal generator compares non-inverting/inverting strobe signals and generates an intermediate signal based on the comparison result. The comparison circuit compares a reference voltage with the non-inverting strobe signal and the inverting strobe signal, respectively, and outputs a control signal. The control signal is enabled when one of the non-inverted/inverting strobe signals is higher than the reference voltage and the other is lower than the reference voltage, and disabled when the non-inverting/inverting strobe signals are the same logical level. The logic circuit receives the intermediate signal and the control signal and generates the data-sampling strobe signal from the intermediate signal when the control signal is enabled.

Abstract: An integrated circuit includes a reset connection to reset the device in response to an externally provided signal. The reset connection is used during test operations to receive elevated supply voltages. The reset connection is coupled to a bias circuit to maintain an inactive state such that the integrated circuit is not reset during the test operation when the reset connection is not actively driven by the external supply.