Abstract: A circuit arrangement (1) has a first circuit block (2) operating at a first supply voltage and a second circuit block (3) operating at a second supply voltage. The first circuit block (2) is coupled to the second circuit block (3) by a voltage level shifting unit (4) in order to transmit a first activation or deactivation signal to the second circuit block (3). It likewise has a voltage level detector (5) which operates at the second supply voltage and is coupled to the voltage level shifting unit (4) and which can be supplied with the first supply voltage, and which is set up such that it outputs a first control signal if the voltage level of the first supply voltage is below a threshold value. The voltage level shifting unit (4) transmits the first deactivation signal to the second circuit block (3) when the voltage level detector (5) outputs the first control signal.

Abstract: A data storage system includes power circuitry configured to provide power signals, storage processing circuitry configured to perform data storage operations, and a packaged microcontroller coupled to the power circuitry and the storage processing circuitry. The packaged microcontroller has input lines, output lines, and control circuitry coupled to the input lines and the output lines. The control circuitry is configured to (i) receive, on the input lines, first power signals (e.g., voltage signals for I/O circuitry) which is provided by the power circuitry to the storage processing circuitry, (ii) wait a predetermined time period in response to receipt of the first power signals on the input lines, and (iii) output, through the output lines, enable signals to the power circuitry after waiting the predetermined time period. The enable signals directs the power circuitry to provide second power signals to the storage processing circuitry (e.g., voltage signals for core circuitry).

Abstract: A reset circuit includes a power supply supplying a power supply voltage, and a band-gap reference that generates a voltage reference signal. A resistor start-up circuit is responsive to the voltage reference signal, and further responsive to an increase in the power supply voltage. The resistor start-up circuit generates a first current when the power supply voltage increases to a first predetermined voltage, and further generates a second current when the power supply voltage increases to a second predetermined voltage. When the second current generated by the resistor start-up circuit is supplied to a resistor divider, the resistor diver delivers an output voltage that is a predetermined portion of the power supply voltage. A comparator compares the voltage reference signal with the resistor divider output voltage, and generates a reset signal when the resistor divider output voltage equals the voltage reference signal.

Abstract: There is provided a power up circuit capable of outputting a power up signal delayed by a predetermined time. The power up circuit includes a voltage divider for dividing an external voltage, a delay controller for generating a control signal to control an output voltage of the voltage divider for a predetermined time by using the external voltage, and a signal generator for generating a power up signal delayed by a predetermined time by using the control signal.

Abstract: A power-on reset circuit is provided. The power-on reset circuit includes an adjusting circuit, a charging/discharging unit and an output circuit. The adjusting circuit receives and adjusts a clock signal so as to output a control signal, wherein a minimum level of the control signal is clamped to be higher than a pre-defined level. The charging/discharging unit having a capacitor apparatus receives the control signal, determines whether to charge/discharge the capacitor apparatus based on the control signal, and outputs a storage voltage of the capacitor apparatus. The output circuit receives the storage voltage and outputs the reset signal. Wherein, the adjusting circuit determines the charging/discharging duty cycle of the charging/discharging unit by adjusting the waveform and the minimum level of the control signal. The output circuit enables/disables the reset signal according to whether the storage voltage reaches the threshold voltage of the output circuit.

Abstract: Provided are a method and system for providing a power-on reset pulse. The system includes a level detector configured to receive an input signal and produce, at least indirectly, a reset signal when the input signal reaches a predetermined level. The system also includes a counter having counting characteristics and configured to receive the reset signal and a clock signal. The counter produces a delayed signal in accordance with the counting characteristics, the clock signal, and the received reset signal.

Abstract: In one embodiment, an integrated circuit device includes a power on reset (POR) circuit and a stochastic reset circuit configured to control enabling and disabling of the POR circuit. The stochastic reset circuit may have a value from among many possible values. The POR circuit may be enabled during a power up sequence of the device when the value of the stochastic reset during the power up is not a value designated to allow disabling of the POR circuit. The stochastic reset circuit may be configured such that the probability of the POR circuit being disabled during the power up is extremely low. After the power up sequence, the stochastic reset circuit may be controlled to allow disabling of the POR circuit to conserve power.

Abstract: An internal reset signal generator that generates an internal reset disable signal after an internal high voltage device has been completely reset. This can substantially reduce errors in operation of semiconductor memory devices. A first circuit generates a first control signal until the power source voltage reaches a stabilized state and a second control signal thereafter. A delay circuit responds to the first and second control signals and a reset complete signal from a reset circuit, and generates an internal reset disable signal only when the second control signal and the reset completion signal are inputted simultaneously, and in other cases, generates an internal reset signal. A reset circuit is connected in a feedback circuit with the delay circuit. It resets a high-voltage device in response to the internal reset signal, and generates a reset completion signal when the high voltage device is reset.

Abstract: A starter circuit includes a start detection circuit for detecting a change of an input signal and outputting a start digital signal, a digital OR circuit for outputting a determination digital signal based on the start digital signal, a power supply circuit being activated based on the determination digital signal, and a digital control circuit being operated based on a power from the power supply circuit. The digital control circuit inputs a retention signal to the digital OR circuit for maintaining an operation of the power supply circuit and a reset signal to the start detection circuit for resetting the start detection circuit.

Abstract: There is provided a reset circuit in which the necessity for adjusting the constant of the pull-up resistor of the reset trigger signal is eliminated to assure a reliable reset operation. The reset circuit has another function to cancel the reset, even when clocks are stopped on power up. During the normal operation, a clock stop detection signal CALMB takes on the level ‘H’ so that a reset trigger signal CPURSTB is masked by an OR gate circuit 8. If the clocks are stopped during the normal operation, and the clock stop detection signal CALMB is ‘L’, the reset trigger signal CPURSTB is passed through OR gate circuits 6, 8 and AND gate circuit 10, and output as a reset output signal RSTB.

Abstract: A device and a method for setting an initial value of a control chip. The device includes a setting unit, which is disposed outside the control chip and provides a setting signal, and a decoder, which is disposed inside the control chip, receives the setting signal, and generates a selecting signal according to the setting signal. The control chip obtains the initial value according to the selecting signal.

Abstract: A low pass filter de-glitch circuit is disclosed herein, it includes a first short pulse resetting circuit, a second short pulse resetting circuit having MOS transistors and a low pass filtering circuit having a capacitor coupled with an inverter. Forgoing circuits are cascode together and then connected to a buffer. The buffer provides two complementary signals which are served as control signals feedbacked to the first short pulse resetting circuit and the second short pulse resetting circuit. Utilizing the driving large current capability the MOS transistors have, the low pass filter de-glitch circuit can reset the capacitor rapidly. Therefore the circuit can filter those glitch signals.

Abstract: A power supply voltage follower connected to a power supply is used for proportionally following an increase of a supply voltage to output a power up reset signal. A pulse generation control circuit coupled to the power supply voltage follower is used for discharging the power supply voltage follower when the supply voltage exceeds a predefined threshold voltage, thereby causing the power up reset signal to produce a reset pulse.

Abstract: In a power-up signal generating device, a power-up signal is activated at a certain level of the power supply voltage VDD by adjusting the turn-on resistance value of the MOS transistor so that the chip reliability can be improved. The power-up signal generating device comprises a reference voltage generating unit, a bias level adjusting unit, a bias signal generating unit and a signal outputting unit. The reference voltage generating unit generates a reference voltage. The bias level adjusting unit receives the reference voltage as an input for controlling a voltage level of a bias signal in a constant level. The bias signal generating unit generates the bias signal under control of the bias level adjusting unit. The signal outputting unit outputs a power-up signal depending on the voltage level of the bias signal.

Abstract: The present invention is to provide a power down circuit, which can configure a wide range of the voltage of the control signal regardless of the fluctuation of the power supply voltage. In the power down circuit 1, the drain of the first N channel MOS transistor M1, into which the control signal PD is input, is connected to the power supply VDD via the resistor R, and at the same time, connected to the gate of the second N channel MOS transistor M2, the source of the second N channel MOS transistor M2 being connected to the gate of the N channel MOS transistor M4, to which the bias voltage VB is supplied, the drain of the N channel MOS transistor M4 being connected to the power supply VDD via the drain of the P channel MOS transistor M3, when the first N channel MOS transistor M1 is turned on/off by the control signal PD, the second N channel MOS transistor M2 is turned off/on, and the bias circuit 2 is operated under a normal condition when it is off, and comes into a power down state when it is on.

Abstract: A power supply switching circuit includes an input terminal (2) for receiving a signal from a motherboard, an output terminal (4) to output a control signal, a first Bipolar Junction Transistor (BJT) (5), and a second BJT (7). A base of the first BJT is connected to the input terminal via a base bleeder circuit. A collector of the first BJT is connected to a stand-by power supply terminal (10) via a collector resistor. A base of the second BJT is connected to the collector of the first BJT. A collector of the second BJT is connected to a system power supply terminal (12) via a collector resistor. The collector of the second BJT is connected to the output terminal. Emitters of the first and second BJTs are grounded.

Abstract: A power-on reset circuit and method for the same may provide reset signals during power-up and/or power-down cycles, to reduce the chances of error. An error may occur, for example, due to voltage fluctuations and/or the ambient temperature of circuit components. Reducing the chances of error during a power-up cycle may include setting an output node of a circuit to a reset state when a power supply voltage reaches a first voltage level and outputting a power-on reset signal to the output node when the power supply voltage equals a second voltage level higher than the first. Reducing the chances of error during a power-down cycle may include setting the output node to a reset state when the output node reaches a third voltage level between the first and second voltage levels.

Abstract: A PUR circuit for generating a reset signal includes a first node for receiving a reference voltage and a second node for receiving a supply voltage that is referenced with respect to the reference voltage. The circuit further includes a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node. The voltage level detector includes a first transistor having a first threshold voltage associated therewith. A resistance element is coupled between the second node and the third node, the resistance element having a first resistance value associated therewith. The circuit also includes an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal. The inverter includes a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage.

Abstract: A method and system for reducing glitch effects in combinational logic is presented. If combinational logic incurs a particle-induced single event transient (SET) signal, a glitch reducing circuit, which is connected in a signal path between the combinational logic and downstream logic, will prevent the SET from propagating to the downstream logic. The glitch reducing circuit functions as a signal filter that provides a SET-filtered drive signal to downstream logic. The glitch reducing circuit receives both the input to the combinational logic and the output from the combinational logic. The input acts to enable or disable the glitch reducing circuit, so that for certain input values, the glitch reducing circuit passes the logic output signal to downstream logic, and for other input values, the glitch reducing circuit blocks the output signal from passing to downstream logic.

Abstract: A reset generator circuit has an oscillator circuit and a delay circuit having a clock signal input, which is connected to an output of the oscillator circuit. The delay circuit can be activated by a control signal at a control input and is designed for outputting a first signal after a first time period and for outputting a second signal after a time period after the outputting of the first signal. The reset generator circuit comprises a generator circuit designed for outputting a reset signal in the event of detection of the first signal up to the detection of the second signal. Furthermore, the reset generator circuit contains a comparison device designed for a comparison of a supply potential with a potential threshold value and for outputting the control signal in the event of the potential threshold value being exceeded. The delay circuit and the generator circuit can be controlled by the comparison device.

Abstract: Optical transmission equipment with more than one power supply which can, when turning on the power supplies, set predetermined function of a signal processing circuit after a predetermined time period after the last turn-on of the power supply and can enable the operation of a drive circuit of the light emitting device after an additional predetermined time period.

Abstract: A semiconductor device includes both a logic circuit and a macro circuit. The macro circuit includes a circuit that consumes direct current (DC). In order to conserve power and allow for testing, the consumption of DC by the current consumption circuit can be stopped with a stop signal, which stops the operation of the macro circuit. The macro circuit can be restarted or returned to normal operation mode without risk of error caused by the stopping of the macro circuit.

Abstract: A power-low reset circuit is provided. The power-low reset circuit receives a reset signal outputted from a power on reset circuit and a stored voltage of a capacitive device in the power-on reset circuit provides an electrical path when a power voltage drops under a predetermined voltage level. The power-on reset circuit is used for generating the reset signal at an initial moment of turning on a power source. The capacitive device can be discharged or charged through the electrical path to restore to its initial status.

Abstract: A power-on reset circuit for generating a reset signal for an associated IC device includes a pull-up resistor connected between a supply voltage and a tracking node, a pull-down transistor connected between the tracking node and ground potential, and a voltage divider circuit connected between the supply voltage and ground potential. The voltage divider circuit has a first ratioed voltage node coupled to the gate of the pull-down transistor. For some embodiments, the voltage divider circuit includes a first resistor connected between the voltage supply and the first ratioed voltage node, a second resistor connected between the first ratioed voltage node and a second ratioed voltage node, a third resistor connected between the second ratioed voltage node and ground potential, and a shunt transistor connected between the second ratioed voltage node and ground potential has a gate responsive to the reset signal.

Abstract: In some embodiments, a circuit includes a reference current source to provide a substantially noise free current signal, and a detector coupled to one or two power supplies. In some embodiments, a method includes receiving a substantially noise free current signal, receiving one or two power supply signals, processing the substantially noise free current signal and the one or two power supply signals to detect a noise signal in the one or two power supply signals, and generating a noise detection signal in response to detection of the noise signal.

Abstract: A startup circuit provides a single connection to a node of a reference or other circuit to be started. The startup circuit injects high current into devices to start a reference circuit. The startup circuit provides strong current invention during startup, and low power consumption during operation.

Abstract: A clock stop detector for a memory comprises a first switch that closes in response to a first logic level of a clock signal to charge a capacitor, a second switch that closes in response to a second logic level of the clock signal to discharge the capacitor, and a logic circuit that outputs a control signal based on an inverted clock signal and a charge on the capacitor.

Abstract: A power on reset circuit includes a pulse generation circuit that is connected to receive a supply voltage and respond to an initial ramp-up of that supply voltage to generate an output pulse that transitions from a low to a relatively high state tracking the supply voltage ramp-up. The pulse generation circuit further sets a feedback node in an enable state. Responsive to a flip signal received at an input node, the pulse generation circuit then transitions the output pulse from the relatively high state to the low state and sets the feedback node in a disable state. A static current control transistor switch includes a source-drain circuit coupled to the supply voltage and further includes a gate. The gate is connected to the feedback node such that the transistor switch is actuated in response to the feedback node enable state and unactuated in response to the feedback node disable state.

Abstract: A power-on reset circuit includes a Schmitt trigger circuit, a voltage divider, and a compensate circuit. The Schmitt trigger circuit includes a plurality of MOS devices of a uniform threshold voltage (Vt) for determining a power reset trigger level. The voltage divider is coupled to an input of the Schmitt trigger circuit for tracking the supply signal. The compensate circuit is operative to generate a small reset pulse to compensate for temperature and the supply signal variation effect.

Abstract: The four types of the zero idle time Z-state circuits are presented with an improvement in productivity, cost, chip area, power consumption, and design time. The zero idle time Z-state circuits basically include a sensing gate, two stacked PMOS transistors, and a feedback line. The sensing gate senses a voltage at its input assuming no feedback is applied. Again, the corresponding output of two stacked PMOS transistors is assumed to be connected to the sensing input. Two stacked PMOS transistors generate a high impedance Z-state at its output according to the corresponding output of the sensing gate. Therefore, the feedback line keeps sampling the output and feeding back the output voltage to the sensing input. Consequently, the feedback configuration provides the initial output voltage, which is the midpoint voltage decided by the device aspect ratios of the sensing gate before normal operation starts in all three systems such as all kinds of phase-locked loops, delay-locked loops, and switching regulators.

Abstract: An integrated circuit preferably to be connected to a motor vehicle battery is selectively switchable between sleep and normal operating modes. The IC may include a useful control logic circuit, a wake-up circuit evaluating an input signal and responsively outputting a wake-up signal dependent on the input signal, and an input control and supply circuit connected between the wake-up circuit and the control logic circuit. The wake-up circuit includes at least one recognition circuit having an amplifier arrangement to selectively amplify the input signal, and an evaluation circuit having a switch arrangement controlled by the amplified signal and an amplifier producing the output signal. The wake-up circuit has a very low current consumption while monitoring the input signal, and produces the wake-up signal only if the input signal suitably exceeds or falls below a specified voltage threshold. The wake-up signal may activate the control circuit, which may activate the logic circuit.

Abstract: An apparatus for generating a power-up signal in a semiconductor memory device includes a signal generator for generating the power-up signal from a supply voltage in response to a first control signal, a temperature sensing block for sensing a circumference temperature and enabling one of a plurality of second control signals in response to the circumference temperature, and a selection block for receiving the plurality of divided voltages and outputting one of the plurality of divided voltages to the signal generator as the first control signal in response to a corresponding second control signal, wherein the divided voltages are generated by dividing a supply voltage.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, a voting structure with inputs from the second settable memory element, the third settable memory element and control to the settable memory elements determine the logical value held on the first settable memory element. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

Abstract: A semiconductor integrated circuit may include an internal circuit, and a power-on reset circuit for generating a power-on reset signal to initialize the internal circuit at a power-on. At the power-on, the power-on reset circuit delays a transition of the power-on reset signal from a first level to a second level until a given time duration after the power supply voltage reaches a detection voltage.

Abstract: Reset circuitry for an integrated circuit is presented. An internal oscillator produces an oscillating signal upon power-up of the integrated circuit. The internal oscillator is not dependent on signals generated outside the integrated circuit. An electro-static discharge blocker circuit receives an external reset signal generated outside the integrated circuit. The electrostatic discharge blocker circuit utilizes the oscillating signal to perform electro-static discharge blocking for the external reset signal to produce an internal reset signal.

Abstract: The present invention discloses a reset signal generating circuit including a power sensing stabilizing unit, a pull-up driving unit, a voltage adjusting unit, a feedback control unit, a pull-up control unit, a self pull-up bias unit and a self bias unit. The reset signal generating circuit generates a reset signal only when a power voltage reaches a predetermined level, regardless of a power-up slope. In addition, the reset signal generating circuit includes a temperature compensating circuit to compensate for variations of operation properties of the voltage adjusting unit due to variations of a temperature, thereby minimizing instability of generation of the reset signal due to variations of the temperature.

Abstract: In one embodiment, a power on reset circuit includes a process dependent element. The process dependent element may be designed to compensate for process and temperature effects that may vary a trip point of the power on reset circuit. The process dependent element may be configured to lower or raise the trip point. The process dependent element may be a diode connected transistor, for example.

Abstract: A semiconductor device includes both a logic circuit and a macro circuit. The macro circuit includes a circuit that consumes direct current (DC). In order to conserve power and allow for testing, the consumption of DC by the current consumption circuit can be stopped with a stop signal, which stops the operation of the macro circuit. The macro circuit can be restarted or returned to normal operation mode without risk of error caused by the stopping of the macro circuit.

Abstract: A bus hold circuit that satisfies both the over-voltage tolerance and maximum leakage current ‘Ioff’ specification without incorporating a diode in pull-up path of a bus-hold circuit is disclosed herein. Specifically, the bus-hold circuit includes a first subcircuit portion operable to provide the bus-hold feature of the circuit connected to a second subcircuit portion. The second sub-circuit portion provides the over-voltage tolerance feature and minimizes the leakage current in the bus-hold circuit. The bus-hold circuit in accordance with the present invention is enhances the performance of the bus-hold current by eliminating the voltage drop across the diodes customarily included within known bus-hold circuit designs. Thereby, this implementation eliminates the negative diode effect on the minimum high sustaining bus-hold current (IBHH) at low supply voltages due to the voltage drop across the diode.

Abstract: A power on reset (POR) circuit for providing a reset pulse signal to a chip when power supply voltage, VDD, ramps up so that the chip always starts in a known state. The POR circuit generates the reset pulse as soon as VDD exceeds an assertion voltage. The assertion voltage is independent of the ramp rate of VDD. The POR circuit is shut off as soon as the reset signal is generated, thereby drawing zero steady state current from VDD. The re-arm time for the POR circuit is very small. The POR circuit does not reset the chip when there is a dynamic change in VDD.

Abstract: A circuit for automatically resetting a central processing unit (CPU) is provided. The circuit includes a detector and a reset signal generator. The detector is electrically connected to the CPU for receiving a specified signal from the CPU, and the detector sends out a triggering signal when the specified signal is not received for a predetermined period of time. The reset signal generator is electrically connected to the detector for generating a reset signal in response to the triggering signal. A chipset with a reset completion indication function is also provided. The chipset includes a plurality of functional circuits and a calculating and recording device.

Abstract: A data strobe circuit is configured to generate an internal strobe signal for latching data in response to a clock signal. The data strobe circuit using a clock signal comprises an external input processing unit, a clock signal processing unit and a strobe signal output unit. The external input processing unit performs a logic operation on an externally applied data strobe signal and a reference voltage, and outputs the result of the logic operation in response to a clock enable signal and an internal control signal. The clock signal processing unit selectively outputs an external clock signal in response to the clock enable signal. The strobe signal output unit performs a logic operation on output signals from the external input processing unit and the clock signal processing unit, and selectively outputs one of the output signals from the external input processing unit and the clock signal processing unit as an internal data strobe signal.

Abstract: A power up signal generator includes a signal converter for converting an applied external source voltage to a voltage applied at a trigger node when the external source voltage rises to a first threshold, and a current source for flowing a reference current from the trigger node. A first inverter connected to the trigger node outputs a low level signal when the trigger node voltage reaches a second threshold. A second inverter outputs a power up signal after receiving the low level signal from the first inverter. The signal converter may include a PMOS transistor configuration, such that the trip voltage of the power up signal generator is dependent only on a single MOSFET transistor threshold voltage.

Abstract: An integrated circuit includes a reset connection to reset the device in response to an externally provided signal. The reset connection is used during test operations to receive elevated supply voltages. The reset connection is coupled to a bias circuit to maintain an inactive state such that the integrated circuit is not reset during the test operation when the reset connection is not actively driven by the external supply.

Abstract: A voltage detection circuit for detecting the voltage level of a first power source. A first transistor includes a first gate, a first source, and a first drain coupled to the first gate. A second transistor includes a second gate, a second source, and a second drain coupled to the second gate. A comparator includes a first input terminal, a second input terminal coupled to the second drain, and an output terminal. A first resistor is coupled between the first input terminal and the first drain. A second resistor is coupled to the first power source. A third resistor is coupled between the second resistor and the first input terminal. A fourth resistor is coupled between the second resistor and input terminal. A fifth resistor is coupled between the first source, and a second power source. A resistive device is coupled between the first source, and the first power source.

Abstract: A startup circuit for a power converter including an amplifier circuit, a comparator, and startup logic. The power converter includes an error amplifier that compares an output sense signal with a startup reference signal and that provides a compensation signal. The amplifier circuit charges the startup reference signal to a predetermined reference level based on a second reference signal in response to a start signal. The comparator determines when the compensation signal reaches a predetermined ramp level and asserts a startup complete signal indicative thereof. The startup logic provides the start signal and provides an output enable signal in response to the startup complete signal. The output enable signal enables output switching to initiate normal regulation operation of the output voltage. In one embodiment, the predetermined ramp level is approximately the center voltage of a sawtooth regulation waveform used for PWM modulation.

Abstract: An integrated circuit has circuitry and pins coupled to the circuitry. One of the pins is a non-dedicated reset pin having a pin signal that is set at a level outside of a normal range for the pin signal so that the integrated circuit is indicated to reset.

Abstract: A voltage detector circuit such as a power up and/or brownout detector circuit (100) includes a comparator (102) having at least one of its inputs (104) coupled to a diode-connected transistor (108). The other input can include another diode-connected transistor (110) or a resistor divider (302). Optional compensation capacitors (118 and 120) can be added to the comparator output (116) to provide glitch compensation. Since comparator (102) only needs to output a high or low voltage level, the components that are used to build circuit (100) do not have to have very tight tolerances. Circuit (100) also can operate at very low voltages and consume low amounts of power.

Abstract: There is provided a power-on reset circuit for generating a power-on reset signal regardless of a power-up slope using not an RC delay method but a current detection method. The power-on reset circuit includes: a power supply voltage sensing node; a power supply voltage detecting unit connected to the power supply voltage sensing node, for detecting a power supply voltage level caused by a difference between a pull-up current and a pull-down current, wherein the power supply voltage detecting unit pulls down the power supply voltage sensing node if the power supply voltage reaches a threshold voltage; and a driving unit connected to the power supply voltage sensing node, for pulling up the sensing node if the power supply voltage is lower than the threshold voltage and buffering a signal of the power supply voltage sensing node to output a power-on reset signal.

Abstract: An auto-grounding circuit responsive to a reset signal discharges an input terminal of an integrated circuit and its associated input line to ground, using a pull-down transistor coupled to the input line, with a gate of the pull-down transistor coupled to receive the reset signal. An exemplary circuit also includes a NAND gate and a second pull-down transistor to maintain an established voltage level of the input line after the reset signal is no longer asserted until the input terminal is driven by an applied input signal. The voltage maintaining circuitry is weaker than the main pull-down transistor to avoid interfering with normal operation of the input terminal.