Abstract: The invention aims at securely generating an internal supply voltage when turning on the power supply of internal circuits in a semiconductor integrated circuit where the operation voltage is low, and securely resetting the internal circuits. The voltage generator generates an internal supply voltage supplied to the internal circuits based on the reference voltage by using the external supply voltage supplied from the exterior. That is, the voltage generator forcibly supplies the external supply voltage as internal supply voltage when the power-on reset signal is activated. Therefore, when the external supply voltage is low at the time of turning-on of the power, and the voltage generator does not operate normally, the internal supply voltage can be securely generated following the external supply voltage so as to be supplied to the internal circuits.

Abstract: A monitor circuit for supplying a detection voltage reflecting a supply voltage, a reference voltage generation circuit for generating a high-precision reference voltage not depending upon the supply voltage, and a comparator for comparing the detection voltage with the reference voltage and outputting the result of the comparison are provided and, in addition, a controller is provided which is made up of an auxiliary reference voltage generation circuit for generating a low-precision auxiliary reference voltage with less power dissipation and an auxiliary comparator for comparing the detection voltage with the auxiliary reference voltage. The auxiliary reference voltage is set higher than the reference voltage, and when the detection voltage becomes higher than the auxiliary reference voltage to cause the comparison output of the auxiliary comparator to become active, the reference voltage generation circuit is placed in a power-down state, thereby achieving a reduction in current dissipation.

Abstract: The present invention relates to a semiconductor device; and, more particularly, to a power-on reset circuit to produce a stable reset signal irrespective of driving speed of a power-on signal which is applied thereto at the time of its initial chip operation. The power-on reset circuit according to the present invention comprises an input unit receiving the power-on signal from an external circuit; a schmitt trigger inverter including an output node, wherein a voltage level at the output node is toggled from a high voltage level signal to a low voltage level signal before an output signal from the input unit increases up to a desired voltage level; and an output unit coupled to the output node for generating the power-on reset signal in response to the voltage level at the output node.

Abstract: A self-power down circuit for a controller coupled to a battery to obtain power from the battery. The controller has a port, the state of which changes during powering up of the controller. The circuit includes a first switching device including a main current conducting path and a control terminal. The control terminal of the first switching device is coupled to the port for monitoring the state of the port. The circuit further includes a second switching device including a main current conducting path and a control terminal, and a switch. The port is coupled to the battery through the main current conducting path of the second switching device. The control terminal of the second switching device is coupled to the switch for actuation by actuation of the switch. The control terminal of the second switching device is also coupled to the main current conducting paths of the first and second switching devices through first and second voltage dropping elements, respectively.

Abstract: A self-power down circuit for a controller coupled to a battery to obtain power from the battery. The controller has a port, the state of which changes during powering up of the controller. The circuit includes a first switching device including a main current conducting path and a control terminal. The control terminal of the first switching device is coupled to the port for monitoring the state of the port. The circuit further includes a second switching device including a main current conducting path and a control terminal, and a switch. The port is coupled to the battery through the main current conducting path of the second switching device. The control terminal of the second switching device is coupled to the switch for actuation by actuation of the switch. The control terminal of the second switching device is also coupled to the main current conducting paths of the first and second switching devices through first and second voltage dropping elements, respectively.

Abstract: A computer system employs a sense amplifier having set and reset functions incorporated therein. Those functions can be performed by the sense amplifier rather than by circuits connected to the sense amplifier. The set and reset functionality is added to the sense amplifier in a manner that minimally impacts the sense amplifier's performance. Accordingly, the sense amplifier includes a number of discharge paths for discharging charges that develop on its output terminals. The set and reset circuit includes a number of high conductance paths that are turned-on in response to an assertion of a set control signal or a reset control signal. When either of those control signals is asserted, the corresponding output terminal is discharged. Accordingly, the output terminals can be either set or reset, responsive to which of the control signals is asserted. When the control signals are de-asserted, the sense amplifier performs in a normal sense amplifier manner.

Abstract: The object of the invention is to provide a power-off detection circuit with low power consumption and little dependence on power supply voltage. Detecting capacitor 11 is charged by the power supply voltage Vcc. When the power supply voltage Vcc drops at the time of power off, the drop is detected by starting transistor 14. Said detecting transistor 11 is discharged, and the discharge current is supplied to gate voltage generating circuit 21. Gate voltage generating circuit 21 generates a gate voltage depending on the discharge current. As a result, output transistor 17 is turned on, and the signal at control terminal 35 is inverted. Another circuit can detect the power-off state depending on the signal at control terminal 35.

Abstract: Method and circuitry for automatic resetting of an integrated circuit upon power up handles multiple clock sources and minimizes power dissipation. A robust voltage sensing circuit detects power up and triggers resetting of most of the circuit with the exception of the initialization circuit that includes an internal oscillator. After the circuit determines that the internal oscillator signal has settled, contents of non-volatile register are read to select the clock source for the circuit. Upon successful selection and clean up of system clock, the reset is removed.

Abstract: A circuit for power supply detection and power on reset. The circuit comprises two separate component groups for producing separate currents which vary in response to the level of a voltage source. For example, each may have a non-linear DC relationship between the power supply and a current of the respective component groups. Furthermore, the DC voltage to current relationship of two groups is different. The circuit has an output with two modes. The two component groups are operable to force the output into one mode when the voltage source is above a threshold and a second mode when the voltage source is below the threshold. Therefore, the circuit is operable to detect when the supply voltage has dropped below a threshold and to also serve as a power on reset. However, the circuit does not rely on the threshold voltage of a transistor to trigger the output.

Abstract: A starting circuit for an integrated circuit (IC) device insures that the IC device is properly initialized before an initialization signal is dropped. The starting circuit, which receives power from high and low potential power supplies, includes a first transistor having a threshold voltage within a known range. The first transistor receives a control voltage generated from the high and low potential power supplies and produces a start (initialization) signal, from the time that the high potential power supply voltage begins to rise to when the control voltage rises to the first transistor threshold voltage. A correction circuit connected to the first transistor adjusts the control voltage in accordance with the threshold voltage of the first transistor.

Abstract: A method is provided for controlling a capacitive charge pump. The charge pump is regulated by a regulating voltage when the supply voltage is greater than the regulating voltage. When the supply voltage is less than a triggering voltage, which is less than or equal to the regulating voltage, the charge pump is automatically supplied between the supply voltage and ground. In one preferred method, the charge pump has a first supply terminal connected to the supply voltage and a second supply terminal that is automatically grounded when the supply voltage is less than the triggering voltage. Also provided is a capacitive charge pump device that includes a charge pump having first and second supply terminals, a voltage regulator delivering a regulating voltage, a switch connected between the second supply terminal and ground, and switch control circuitry for automatically controlling the switch.

Abstract: A system and method is described for providing a single pin reset for a mixed signal integrated circuit. The system and method provides for a single reset signal/pin of the integrated circuit to be utilized to generate all internal resets for the analog and digital circuitry/sections of the mixed signal integrated circuit. In one form, a state machine generates a reset signal for a phase locked loop synthesizer that is utilized to generate internal system clocks for the analog and digital circuitry, as well as a digital reset signal that provides reset signals to the various digital sections circuitry of the integrated circuit. Preferably, the chip reset signal is provided for a longer period of time than the PLL reset signal in order to assure that the PLL is running and generating clocking signals before the digital logic is clocked.

Abstract: The present invention includes a circuit to maintain a constant voltage on a storage element such as a capacitor at the output of a regulator during an emergency power condition. It includes a detector to detect the emergency condition and to generate a fault signal in response to the emergency condition, a one-shot time delay circuit to delay the enabling of a regulator in response to the fault signal, and a second delay unit to delay the enabling of the load of a regulator to accommodate the non-zero recovery time of a regulator. These two time delay units are able to bypass the noisy switching on the fault signal so that the maintained voltage on the storage capacitor will not droop and can be reliably used for such purposes as head retract and spindle brake under a noisy power emergency situation.

Abstract: A low voltage reset circuit device without being influenced by temperature and manufacturing process is formed by a first low voltage reset circuit using an energy gap circuit to generate a reference voltage, and a second low voltage reset circuit using a threshold voltage of a MOS transistor as a reference voltage. The first low voltage reset circuit is used to provide an accurate low voltage reset property,. while the circuit only works as VDD>1.2V. When VDD<1.2V, the second low voltage reset circuit still works normally for providing the desired reset signal thereby covering the low VDD voltage range.

Abstract: A method and apparatus for glitch protection for differential strobe input buffers in a source-synchronous environment. The present invention provides a solution to the problem of noise sensitivity of differential strobe input buffers in a source-synchronous environment, which may cause functional problems. The present invention enables the use of fully differential strobe signals to improve electrical performance of the source synchronous data transfers while removing the noise sensitivity problem associated with these signals. This is accomplished by providing a glitch protection circuit that provides protection against input glitches for a first predetermined period of time after each strobe transition. The present invention also provides a detection circuit that detects when both differential strobe signals are in the same logic state, which corresponds to a transition between bus masters (a dead cycle).

Abstract: A resetting circuit includes first and second transistors that respectively receive first and second voltages through gates. The ratio W/L of the second transistor is larger than that of the first transistor. The first and second voltages rise in accordance with the rise of a supply voltage. The second voltage is lower than the first voltage. Since an increase in the current IDS of the first transistor is greater than an increase in the current IDS of the second transistor, an inversion occurs between the current IDSs of the first and second transistors by applying a predetermined supply voltage. Since a reset signal is generated when the values of the currents IDS of the first and second transistors cross, the reset signal can always be generated by the predetermined supply voltage, independent from the threshold voltage of the transistor.

Abstract: A bias block switching unit is responsive to a power down control signal for switching between first and second states thereof, being operatively coupled to a reference voltage and coupled to a first supply voltage. A first switch is responsive to the power down control signal for switching between first and second states thereof. The first switch provides an output signal. A first switched constant current unit is coupled to the first switch and a first supply voltage. A first switched constant current unit has a first state for providing a constant current output and a second state for providing substantially no current. The first switched constant current unit is responsive to a bias signal for switching between first and second states thereof. The bias signal is outputted from the bias block switching unit. A first voltage follower receives an input signal, is operatively coupled to a second voltage supply and operatively coupled to the first switch.

Abstract: A sensor with a dynamic latch comprising having a sensor coupled to a gain amplifier, a delay circuit connected to the gain amplifier and a summing circuit coupled through first and second nodes to the gain amplifier. The sensor with a dynamic latch further comprises an output stage coupled to a comparator circuit and the summing circuit and to third and fourth nodes and first and second energy storing devices coupled to the comparator circuit.

Abstract: The present invention relates to a bonding option circuit and a multi-level buffer that generates a plurality of selection signals from a single selective condition applied to a bonding pad to reduce the number of required bonding pads and buffers for a semiconductor device. A multi-level buffer according to the present invention can include a variable voltage divider, a comparator circuit and a logic signal generator. The variable voltage divider produces a first voltage, a second voltage, and a third voltage having voltage levels that are changed in accordance with conditions applied to a pad preferably when the variable voltage divider is activated by a power-up signal. The comparator circuit preferably generates a first comparison result and a second comparison result by being activated by the power-up signal and comparing the first to third voltages. The logic signal generator produces a first buffer output signal and a second buffer output signal.

Abstract: A power-off protection circuit for an LVDS line-driver eliminates initialization problems in a local LVDS driver circuit that are caused by a remote LVDS river when the local LVDS driver is disabled. The remote LVDS driver may introduce a signal into the substrate of the local LVDS driver when the local LVDS driver is in a power-off mode. A current source in the local LVDS driver couples power from a local power supply node to the local LVDS driver when power is active. A method and protection circuit connects the substrate of the current source to the local power supply when power is active, and decouples the substrate from the local power supply when power is deactivated. The remote LVDS driver cannot cause a false power supply signal in the local LVDS driver since the conduction path is disconnected. A first switching element couples a floating substrate node in the current source to the local power supply when the power is active.

Abstract: A power-off protection circuit for an LVDS line-driver eliminates initialization problems in a local LVDS driver circuit that are caused by a remote LVDS driver when the local LVDS driver is disabled. The remote LVDS driver may introduce a signal into the substrate of the local LVDS driver when the local LVDS driver is in a power-off mode. A current source in the local LVDS driver couples power from a local power supply node to the local LVDS driver when power is active. A method and protection circuit connects the substrate of the current source to the local power supply when power is active, and decouples the substrate from the local power supply when power is deactivated. The remote LVDS driver cannot cause a false power supply signal in the local LVDS driver since the conduction path is disconnected. A first switching element couples a floating substrate node in the current source to the local power supply when the power is active.

Abstract: A reset circuit outputting a reset signal /RESET when detecting an abnormal state in a ring counter is provided. The reset circuit divides the outputs of flip-flops constituting the ring counter into two groups, and check if either of the groups has “H” data. When “H” data exists in both of the two groups or when “H” data does not exist in either of the two groups, the reset circuit activates the reset signal /RESET to L level. Therefore, a semiconductor device can detect an erroneous state and recover to a normal state quickly.

Abstract: A protection device for preventing power-on sequence induced latch-up, which device is used in a power supply system having a first power supply and a second power supply wherein the voltage of the first power supply is higher than that of the second power supply.

Abstract: A startup control voltage preset method and apparatus to reduce phase locked loop lock acquisition time at startup. In one embodiment, the disclosed apparatus includes a phase locked loop circuit including a startup circuit that is activated at startup. The startup circuit is coupled to force a control input of a voltage control oscillator of the phase lock loop circuit across a loop filter to a voltage at or near a target nominal operating voltage. In one embodiment, the target nominal operating voltage corresponds to a target operating frequency of the phase locked loop circuit. In one embodiment, the startup circuit is coupled to be activated for a predetermined time at startup. In one embodiment, the startup circuit is coupled to be activated at startup until the control input voltage of the voltage controlled oscillator is at or near a reference voltage.

Abstract: A reset pulse signal generating circuit includes an output node with an output circuit connected thereto that outputs the reset pulse signal, and a first MOS transistor having a first conductivity type connected between a first power supply and the output node. The first MOS transistor is turned on responsive to a write signal. The circuit further includes a second MOS transistor having a second conductivity type connected between the output node and a second power supply, and a power supply transition detector connected to the first and second power supplies and the second MOS transistor. The power supply transition detector outputs a transfer signal having a level determined by a level of the power supplies when the write signal is in an inactive state. The power supply transition detector outputs the transfer signal having a predetermined level when the write signal is in the active state.

Abstract: A start-up circuit for a bias generator circuit includes an oscillator, a power monitoring circuit and a controllable current source. As the power supplies begin to ramp up to their final voltage, the power monitoring circuit monitors power consumed by the oscillator. As the oscillator begins to ring, the power monitoring circuit couples a control signal to the controllable current source, which generates a current used to start-up the bias generator circuit. Once the bias generator circuit has achieved an active operating condition, the start-up circuit is disengaged from the bias circuit by disabling the oscillator. The start-up circuit does not consume any standby current when disabled, and does not effect the operation of the bias generator circuit.

Abstract: Set and reset functions are corporated in a sense amplifier such that those functions can be performed by the sense amplifier rather than by circuits connected to the sense amplifier. The set and reset functionality is added to the sense amplifier in a manner that minimally impacts the sense amplifier's performance. Accordingly, the sense amplifier includes a number of discharge paths for discharging charges that develop on its output terminals. The set and reset circuit includes a number of high conductance paths that are turned-on in response to an assertion of a set control signal or a reset control signal. When either of those control signals is asserted, the corresponding output terminal is discharged. Accordingly, the output terminals can be either set or reset, responsive to which of the control signals is asserted. When the control signals are de-asserted, the sense amplifier performs in a normal sense amplifier manner.

Abstract: A system includes a detector, a first and second processor, and a reset circuit. The detector delivers a first signal in response to detecting a preselected condition, such as low battery voltage. The first processor receives the first signal and delivers an acknowledge signal indicating that the first processor will enter a reset mode of operation in response to receiving a reset signal. The second processor enters the reset mode of operation in response to receiving the first signal. The reset circuit delivers a reset signal to the first processor in response to receiving the first signal and the acknowledge signal so that the first processor is reset when it has acknowledged that it is ready to do so.

Abstract: A semiconductor integrated circuit has a reset signal generation circuit (10) that generates a reset signal (12) having a reset period based on a power-on reset signal (11), and a latch circuit (20) having an initialization circuit (23) that initializes a latch output (21) based on the reset signal (12). The reset signal generation circuit (10) has a delay circuit (14) that can variably set a pulse width corresponding to the reset period of the reset signal (12). An output line of the delay circuit (14) is connected to a first pad terminal (32). An output line of the initialization circuit (23) is connected to a second pad terminal (34). When the semiconductor integrated circuit is verified, the first and second pad terminals (32, 34) are brought in contact with a probe (40).

Abstract: Disclosed is a semiconductor integrated circuit capable of performing a normal operation from immediately after turn-on of power without deteriorating degree of integration. The collector of an NPN bipolar transistor Q1 is connected to a terminal P1 and the emitter of the same is connected to a positive electrode of a reference voltage source 32. The emitter of an NPN bipolar transistor Q2 is connected to the terminal P1 and the collector of the same is connected to the positive pole of the reference voltage source 32. The reference voltage source 32 generates a reference voltage VREF2 from its positive electrode and the negative electrode is connected to the ground.

Abstract: An IIL reset circuit includes an IIL inverter having input and output terminals, and a capacitor connected to the IIL inverter through the input terminal. When the IIL inverter is supplied with a constant current, it charges the capacitor through the input terminal, and outputs a reset pulse through the output terminal. The reset pulse has a pulse width that is determined based on both a current supplied to the capacitor, and on a capacitance of the capacitor.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first signal comprising a series of one or more pulses. The second circuit may be configured to generate a second signal in response to the first signal. The second signal may be configured to control the reset of an external device. In one example, the present invention may be implemented as a power on reset circuit.

Abstract: A circuit for protecting a microprocessor in a controller for controlling a coin validator from noise includes a noise detector and the circuit is configured to temporarily halt the microprocessor when noise is detected.

Abstract: A select signal generating circuit for preventing a malfunction and an increase in the circuit area is provided. The select signal generating circuit includes a select signal generator for generating a plurality of select output signals in accordance with a clock signal in response to a reset signal provided after a predetermined time passes since power on. A power-ON detection circuit detects the power-on, generates a power-ON detection signal, and maintains the power-ON detection signal until the reset signal is provided. The select signal generator includes a clamp circuit connected to the power-ON detection circuit for clamping the plurality of select output signals to predetermined levels in response to the power-ON detection signal.

Abstract: Integrated circuit devices having metastability protection circuits therein include a main active circuit and a metastability detection/prevention circuit. The main active circuit may comprise a comparator, a sense amplifier, a differential amplifier or a voltage generating circuit, for example. The metastability detection/prevention circuit performs the function of detecting whether an output of the main active circuit has been disposed in a metastable state for a duration in excess of a transition duration. The output of the main active circuit may be considered as being in a metastable state if a potential of the output signal equals VMS, where VMS is in a range between VIL and VIH. If the output signal has been in a metastable state for a duration in excess of the transition duration, then the metastability detection/prevention circuit will generate a control signal at a designated logic level.

Abstract: A semiconductor integrated device has a detection cell arranged in a power-supply line in the semiconductor integrated device and detecting a power-supply voltage. Further, a detection circuit detects a voltage drop of the power-supply voltage detected by the detection cell. Connection wiring connects the detection cell and the detection circuit and outputs the power-supply voltage detected by the detection cell to the detection circuit.

Abstract: An LVDS interface for a programmable logic device uses phase-locked loop (“PLL”) circuits to provide data clocks for data input and output. The PLL clocks are highly accurate and each includes a multiply-by-W counter so that a multiplied and an unmultiplied clock are available. The multiplied clock is used to clock data into or out of a shift register chain serially. The unmultiplied clock is used to load or read the registers in the shift register chain in parallel. Providing both the multiplied and unmultiplied clocks from a single PLL assures that the clocks are in proper phase relationship so that the serial inputting or outputting, and the parallel loading or unloading, are properly synchronized.

Abstract: An initializer that responds to change in a power supply potential level, for generating an initialize signal to initialize a circuit to a select state, the initializer includes a power-on reset circuit that switches between an active and a powered-down state, and is for generating the initialize signal. The initializer also includes a wake-up circuit that monitors the power supply potential level and switches the power-on reset circuit from the powered-down state to the active state when selected change in the power supply potential level occurs.

Abstract: A power-on reset (POR) circuit that delays de-assertion a POR control signal in an IC device such that, when unstable power levels are detected, the POR control signal is maintained in an asserted condition until the IC device is fully reset. During a start-up phase of the IC device operation, the POR control circuit maintains the POR control signal in the asserted condition for a delay period whose length is determined, in part, by the amount of noise in the applied power. After the internal voltage of the IC device achieves a steady state for a suitable period of time, the POR control circuit de-asserts the POR control signal, thereby initiating configuration of the IC device. Subsequently, if a low power condition is detected, the POR control circuit asserts the POR control signal, and maintains the POR control signal in the asserted condition for a pre-defined delay period after the low-power event is detected, thereby allowing the IC device to fully reset.

Abstract: A circuit for enabling a servo to perform an automatic system recovery and a method therefor, involves the provision of a timer and associated circuit in the servo˜such that the servo system can transmit a system normal signal to the timer at predetermined intervals. Once the servo system is abnormally terminated, resulting in an interruption of the transmission of the normal signal, the timer is triggered to generate a reset signal for restarting the servo so as to complete the reset process of the system.

Abstract: An output buffer includes a reference capacitor; a constant current source connected in series with the reference capacitor, for generating a reference voltage with a constant gradient by charging the reference capacitor; a first transistor having its source connected to a capacitive load, and its gate connected to the connecting point of the reference capacitor and the first constant current source to be supplied with the reference voltage; a second transistor connected between the drain of the first transistor and a voltage source; a third transistor connected between the capacitive load and the voltage source; and a fourth transistor connected to the control terminal of the second transistor and to the control terminal of the third transistor, for switching the second and third transistors from an OFF state to an ON state when the first transistor is turned on.

Abstract: A reset circuit includes an invertor having one control input terminal to which a positive supply voltage and a potential lower than GND are supplied, and an n-channel transistor having a gate terminal connected to an output terminal of the invertor, a source terminal connected to a potential lower than the GND and a drain terminal connected to the GND.

Abstract: A gated clock type logic circuit is provided in which timing designing for a supply of a clock can be made easy and a period of time required for designing can be shortened. The gated clock type logic circuit has a gate circuit designed to allow a clock signal inputted in accordance with a level of a clock enabling signal to be passed or to be masked. An output of the gate circuit to control a latching timing of a latch circuit for receiving data is fed to a clock input terminal of the latch circuit. The gated clock type logic circuit is provided with a selector which receives an input data and an output data from the latch circuit and selects either of the input data or the output data by using a data enabling signal as a selecting signal and outputs it. An output from the selector is fed to a data input terminal of the latch circuit.

Abstract: A power on reset (POR) circuit in a semiconductor device which is process independent and resistant to noise present in a power supply voltage when the power supply voltage has not yet obtained a predetermined operational voltage level. The POR circuit includes a differential amplifier, a non-inverting input control circuit and an inverting input control circuit. The differential amplifier senses and amplifies a difference in voltage between the non-inverting input terminal and the inverting input terminal. The non-inverting input control circuit controls a voltage of the non-inverting input terminal of the differential amplifier. The inverting input control circuit controls a voltage of the inverting input terminal of the differential amplifier.

Abstract: In an integrated circuit (IC) for providing an enabling signal (EN) to a converter, the integrated circuit (IC) comprising:

Abstract: An integrated circuit for particular use in a disc drive has a core logic module connected to a core voltage, an input/output buffer module connected to an input/output voltage and having input/output buffer control lines connected to the core logic module, and a mode switch input on the I/O buffer module that is operable to prevent output operation of the I/O buffer module whenever core voltage is below a safe operating level. One embodiment has the core logic module determining when the safe operating level is met and providing an appropriate signal to the I/O buffer. Another embodiment has a separate level detect module operably connected to the core voltage and the input/output voltage determining when the safe operating level is met, and having an output connected to the mode switch input on the I/O buffer module.

Abstract: A flip-flop control circuit for reducing low-frequency power supply noise, a processor incorporating the flip-flop control circuit, and a method for operating the processor are disclosed.

Abstract: A power-up detector for detecting power-up and power supply voltage bump conditions comprising a current mirror connected to a power supply, a pair of series connected resistors connected between the current mirror and ground, and providing a bias point at a junction of the series connected resistors, and a field effect transistor having a source-drain circuit connected between the current mirror and ground for providing an output signal, the transistor being controlled by the bias point.

Abstract: The present invention provides a reset circuit of a semiconductor circuit, which can reliably reset plural reset target circuits in the semiconductor circuit, even in a case where a surge noise signal having a short pulse length or the like is input to the reset circuit. A reset signal control circuit 120 for controlling a timing of deactivating a reset instruction signal which resets plural reset target circuits 141 to 143 in the semiconductor circuit is included. When the respective reset target circuits have been reset, the respective reset target circuits output reset completion signals S141 to S143 to the reset signal control circuit 120. Then, when all of the reset completion signals S141 to S143 have been activated, the reset signal control circuit 120 deactivates the reset instruction signal.

Abstract: When a semiconductor integrated circuit device is reset, an input and output node is to be pulled down or up for stability of the integrated circuit, wherein a series combination of a pull-down resistor/pull-up resistor and a switching transistor is integrated on the semiconductor chip in such a manner as to permit the switching transistor to flow electric current through the pull-down/pull-up resistor only when the semiconductor integrated circuit device is reset, thereby enhancing the stability without sacrifice of the power consumption.