Master-slave Bistable Latch Patents (Class 327/202)
-
Patent number: 9424921Abstract: An object is to provide a signal processing circuit which can be manufactured without a complex manufacturing process and suppress power consumption. A storage element includes two logic elements (referred to as a first phase-inversion element and a second phase-inversion element) which invert a phase of an input signal and output the signal, a first selection transistor, and a second selection transistor. In the storage element, two pairs each having a transistor in which a channel is formed in an oxide semiconductor layer and a capacitor (a pair of a first transistor and a first capacitor, and a pair of a second transistor and a second capacitor) are provided. The storage element is used in a storage device such as a register or a cache memory included in a signal processing circuit.Type: GrantFiled: July 16, 2014Date of Patent: August 23, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama
-
Patent number: 9425775Abstract: A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage.Type: GrantFiled: September 9, 2014Date of Patent: August 23, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Anis M. Jarrar, John M. Dalbey, Alexander B. Hoefler, Colin MacDonald
-
Patent number: 9425771Abstract: A flip-flop is disclosed that utilizes low area. The flip-flop includes a tri-state inverter that receive a flip-flop input, a clock input and an inverted clock input. A master latch receives an output of the tri-state inverter. The master latch includes a common inverter. A slave latch is coupled to the master latch. The common inverter is shared between the master latch and the slave latch. An output inverter is coupled to the common inverter and generates a flip-flop output.Type: GrantFiled: September 26, 2014Date of Patent: August 23, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Suvam Nandi, Badarish Mohan Subbannavar
-
Patent number: 9397641Abstract: Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.Type: GrantFiled: May 13, 2015Date of Patent: July 19, 2016Assignee: Intel CorporationInventors: Steven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy
-
Patent number: 9377957Abstract: Aspects of the disclosure provide an integrated circuit that includes a plurality of input/output (IO) circuits, an instruction receiving circuit and control circuits. The IO circuits are configured to receive a plurality of bit streams corresponding to an instruction to the integrated circuit. The instruction receiving circuit is configured to form the instruction from the plurality of bit streams. The control circuits are configured to operate according to the instruction.Type: GrantFiled: February 6, 2014Date of Patent: June 28, 2016Assignee: Marvell World Trade Ltd.Inventors: Shawn Chen, Wei Jiang, Lin Chen
-
Patent number: 9350334Abstract: To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided.Type: GrantFiled: October 9, 2014Date of Patent: May 24, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kiyoshi Kato, Jun Koyama
-
Patent number: 9350325Abstract: A CMOS D-type flip flop (D-FF) exhibits reduced power consumption by selectively disabling certain charging/discharging operations at specific circuit elements to minimize the capacitance of the circuit's internal nodes using a partial signaling technique. A clock inverter module may be used to provide a partial inverse clock signal that is the complement of a clock signal when a non-clock dependent input to the clock inverter module has a first value and to provide a fixed signal when the non-clock dependent signal has a second value. One or more MOSFETs controlled by the partial inverse clock signal do not charge or discharge when the non-clock dependent signal has the second value.Type: GrantFiled: May 30, 2012Date of Patent: May 24, 2016Assignee: Qualcomm, IncorporatedInventors: Yanfei Cai, Shuangqu Huang, Qiang Dai
-
Patent number: 9343183Abstract: A controller for a memory device has a power control section to control power to a memory element in an operation mode and in a retention mode. A monitoring section receives and monitors error information and a storage section stores a retention parameter. In the operation mode, the power control section causes an operation voltage to be applied to the memory element, and in the retention mode, the power control section causes a time-varying voltage to be applied to the memory. The power control section also causes the voltage across the memory element to change in the retention mode between a first retention voltage and a second retention voltage based on the retention parameter.Type: GrantFiled: August 20, 2014Date of Patent: May 17, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Ziyu Guo, Xiangming Kong, Shayan Zhang
-
Patent number: 9316692Abstract: The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.Type: GrantFiled: March 3, 2015Date of Patent: April 19, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Lee D. Whetsel
-
Patent number: 9306545Abstract: A master-slave flip-flop circuit with a master latch and slave latch has clock generating circuitry which generates a gated clock signal based on the clock signal and a gating control signal. When the gating control signal has a first value, then the gated clock signal has a value dependent on the clock signal, while when the gating control signal has a second value then the gated clock signal has a fixed value independent of the clock signal. At least one component of the master-slave flip-flop circuit is controlled by the gated clock signal so that dynamic switching power can be reduced. The gating control signal is dependent on the input signal or a signal within the master latch and is independent of a slave signal in the slave latch and the output signal of the flip-flop.Type: GrantFiled: January 14, 2014Date of Patent: April 5, 2016Assignee: ARM LimitedInventor: Anil Kumar Baratam
-
Patent number: 9287858Abstract: Multi-threshold CMOS (MTCMOS) sequential circuits are presented with a first latch circuit formed of transistors with threshold voltages in a first range, along with a second latch circuit with inverters and a transfer gate formed of higher threshold voltage transistors for low-power retention of data from the first latch with power switching circuitry to selectively decouple inverters of the second latch circuit from a voltage supply during low-power retention mode operation of the sequential circuit.Type: GrantFiled: October 23, 2014Date of Patent: March 15, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Vipul Kumar Singhal
-
Master-slave flip-flops and methods of implementing master-slave flip-flops in an integrated circuit
Patent number: 9281807Abstract: A master-slave flip-flop implemented in an integrated circuit comprises a master latch coupled to receive data at an input; and a slave latch coupled to an output of the master latch, wherein the slave latch comprises an SEU-enhanced latch, and the master latch is not enhanced for SEU protection. A method of implementing a master-slave flip-flop in an integrated circuit is also described.Type: GrantFiled: June 9, 2014Date of Patent: March 8, 2016Assignee: XILINX, INC.Inventors: Pierre Maillard, Praful Jain, Michael J. Hart, Sundeep Ram Gopal Agarwal, Austin H. Lesea, Jun Liu -
Patent number: 9276616Abstract: An integrated circuit chip including a first inductor; a second inductor having n1 turns and located a distance r1 from the first inductor; and a third inductor having n2 turns and located a distance r2 from the first inductor; wherein the second and third inductors are coupled so as to cause current to circulate around the second inductor in a first rotational direction and around the third inductor in a second rotational direction opposite to the first rotational direction; and wherein n1, n2, r1 and r2 are such that current induced in the first inductor due to magnetic coupling from the second inductor is negated by current induced in the first inductor due to magnetic coupling from the third inductor.Type: GrantFiled: January 10, 2014Date of Patent: March 1, 2016Assignee: Qualcomm Technologies International, Ltd.Inventor: Michael John Story
-
Patent number: 9276566Abstract: A dual edge triggered retention flip-flop reduces clock tree power dissipation in an active mode and leakage power in a low-power (e.g., standby) mode. For example, a first latch can be used to latch a first state of an input to a flip-flop in response to a first (e.g., positive-going) edge of a clock signal and a second latch can be used to latch a second state of the input to the flip-flop in response to a second (e.g., negative-going) edge of a clock signal. A retention latch can be used to latch and retain the state of the flip-flop when the first and second latches are disabled to save power in the low-power mode. The retention latch can also be used to initialize at least one of the first and second flip-flops when exiting the low-power mode.Type: GrantFiled: August 26, 2014Date of Patent: March 1, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Vipul Kumar Singhal
-
Patent number: 9264023Abstract: In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element and at least two legs, including a data leg and at least one scan leg. The first node of the storage element may be driven by the data leg. The opposite node of the storage element may be driven by at least one of the scan legs. The slave latch may be coupled to the master latch.Type: GrantFiled: March 7, 2014Date of Patent: February 16, 2016Assignee: Cavium, Inc.Inventor: Suresh Balasubramanian
-
Patent number: 9257972Abstract: A flip-flop circuit is disclosed. The flip-flop circuit includes pull-up and pull-down circuits each coupled to a data input and configured to be activated responsive to a clock signal transition from a first phase to a second phase, depending on the input data. A write circuit is configured to write data into a latch of the flip-flop responsive to activation of one of the pull-up and pull-down circuits. An output driver circuit includes a dynamic portion and a static portion, with the dynamic portion being activated responsive to activation of one of the pull-up and pull-down circuits. Activation of the dynamic portion may occur concurrently with writing of the data into the latch. The output driver circuit also includes a static portion. After the clock transitions back to the first phase, the static portion may drive and hold the output while the dynamic portion is deactivated.Type: GrantFiled: September 29, 2014Date of Patent: February 9, 2016Assignee: Oracle International CorporationInventors: Ha Pham, Jin-Uk Shin, Hiep Ngo
-
Patent number: 9197245Abstract: A digital serial-to-parallel converter capable of minimizing a malfunction of a circuit by more stably performing an operation of a D flip flop in implementing a GaAs MMIC digital serial-to-parallel converter and a GaAs MMIC using the same are disclosed. The digital serial-to-parallel converter includes: a converter configured to convert a received clock signal, serial data, and load signal of TTL into a DCFL signal; a plurality of D flip flops configured to transmit the serial data received through the converter to a D flip flop of a next stage by the clock signal received through the converter and output the serial data of the D flip flop of the next stage by the load signal received through the converter; and a plurality of buffers configured to receive the serial data from the plurality of D flip flops to generate and output complementary signals.Type: GrantFiled: October 15, 2014Date of Patent: November 24, 2015Assignee: Electronics and Telecommunications Reearch InstituteInventors: Jin-Cheol Jeong, Dong-Hwan Shin, In-Kwon Ju, In-Bok Yom
-
Patent number: 9160314Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.Type: GrantFiled: August 12, 2014Date of Patent: October 13, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Bartling, Sudhanshu Khanna
-
Patent number: 9160318Abstract: A data processing circuit that holds a state of a clock signal of each phase of an input multi-phase clock at a timing of an input latch clock, the multi-phase clock including clock signals of a plurality of phases sequentially shifted at certain intervals determined in advance, and generates a digital signal obtained by digitizing the states of the phases of the multi-phase clock at a timing at which the latch clock is input, the data processing circuit including: a latch portion including n latch unit groups (n is an integer of a power of 2) including the same number and a plurality of latch units, each latch unit holding the state of the clock signal of the corresponding phase of the multi-phase clock and outputting an output signal indicating the held state of the clock signal.Type: GrantFiled: September 18, 2013Date of Patent: October 13, 2015Assignee: OLYMPUS CORPORATIONInventor: Yosuke Kusano
-
Patent number: 9136013Abstract: The present invention relates to a display device field, and provides a shift register, a gate driver, and a display device. The shift register comprises an input programming unit, a latch unit, an output programming unit and an inverting output unit; the input programming unit is connected to the input end of the latch unit to program the input end of the latch unit; the latch unit is used for latching the output signal, and a non-inverting output end and an inverting output end of the latch unit are connected through the output programming unit; the output programming unit is connected to the output end of the latch unit to program the output end of the latch unit; the inverting output unit is connected to the inverting output end of the latch unit and is used for generating a inverting output signal of the shift register.Type: GrantFiled: September 13, 2012Date of Patent: September 15, 2015Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Haigang Qing, Xiaojing Qi
-
Patent number: 9130550Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.Type: GrantFiled: June 4, 2014Date of Patent: September 8, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chung-Hee Kim, Min-Su Kim, Ji-Kyum Kim, Emil Kagramanyan, Dae-Seong Lee, Gun-Ok Jung, Uk-Rae Cho
-
Patent number: 9124262Abstract: A device (300, 1000) provides a dual-edge triggered flip-flop (DETFF) that is reconfigurable to a master-slave flip-flop (MSFF). The device includes a reconfigurable MUX-D flip-flop including two distinct circuit configurations. In a first configuration, two latches or storage elements (340, 360, 1040, 1060) are operating in series to provide a MUX-D flip-flop. In a second configuration, the storage elements (340, 360, 1040, 1060) are operating in parallel to provide a dual-edge triggered flip-flop (DETFF).Type: GrantFiled: June 26, 2013Date of Patent: September 1, 2015Assignee: Freescale Semiconductor, Inc.Inventor: Ravindraraj Ramaraju
-
Patent number: 9116701Abstract: A memory unit comprises at least two volatile memory elements, analyzing circuitry and power gate. The memory elements may for example be latches, flip-flops, or registers. Each of the memory elements has at least two different states including a predefined reset state. The analyzing circuitry generates a power-down enable signal in response to each of the memory elements being in its reset state. The power gate powers down the memory elements in response to the power-down enable signal. The memory elements may be arranged to assume their reset states upon powering up the memory unit.Type: GrantFiled: June 11, 2010Date of Patent: August 25, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Michael Priel, Joseph Rabinowicz, Anton Rozen
-
Patent number: 9083328Abstract: In an embodiment of the invention, a flip-flop circuit contains a first inverter, a pass gate, master latch, a transfer gate and a slave latch. The clock signals and retention control signals determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals, the retain control signals, the slave control signals. The clock signals, the retain control signals, and the slave control signals determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. The retain control signals determine when data is stored in the slave latch during retention mode.Type: GrantFiled: August 12, 2014Date of Patent: July 14, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Bartling, Sudhanshu Khanna
-
Patent number: 9059694Abstract: An object is to provide a low-power semiconductor device which does not require a latch circuit to hold data at the output of inverter circuits. In the semiconductor device, an input of a first inverter circuit is connected to an input terminal through a source and a drain of a first transistor. An input of a second inverter circuit is connected to an output of the first inverter circuit through a source and a drain of a second transistor. An output of the second inverter is connected to an output terminal. An inverted clock signal and a clock signal are input to gates of the first transistor and the second transistor, respectively. The first and the second transistor have extremely low off-current, which allows the output potential of the device to remain unchanged even when the input varies.Type: GrantFiled: December 9, 2013Date of Patent: June 16, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Masato Ishii
-
Patent number: 9059693Abstract: Provided is a semiconductor circuit. The semiconductor circuit includes a pulse generator which is enabled by a rising edge of a clock signal and generates a read pulse which varies depending on a voltage of a feedback node; and a sense amplifier which generates a voltage of a dynamic node and the voltage of the feedback node in accordance with a data value of an input signal using the read pulse.Type: GrantFiled: March 15, 2013Date of Patent: June 16, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Rahul Singh, Min-Su Kim
-
Patent number: 9054679Abstract: A flip-flop circuit consuming lower power than a conventional flip-flop circuit is provided. Further, a flip-flop circuit having a smaller number of transistors than a conventional flip-flop circuit to have a reduced footprint is provided. An n-channel transistor is used as a transistor which is to be turned on at a high level potential and a p-channel transistor is used as a transistor which is to be turned on at a low level potential, whereby the flip-flop circuit can operate only with a clock signal and without an inverted signal of the clock signal, and the number of transistors that operate only with a clock signal in the flip-flop circuit can be reduced.Type: GrantFiled: September 10, 2013Date of Patent: June 9, 2015Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Masashi Fujita
-
Patent number: 9041429Abstract: The disclosure relates generally to sequential state elements (SSEs), triple-mode redundant state machines (TMRSMs), and methods and systems for testing triple-mode redundant pipeline stages (TMRPSs) within the TMRSMs using triple-mode redundant SSEs (TMRSSEs). The SSEs, TMRSMs, TMRPSs, and TMRSSEs may be formed as integrated circuits on a semiconductor substrate. Of particular focus in this disclosure are SSEs used to sample and hold bit states. Embodiments of the SSEs have a self-correcting mechanism to protect against radiation-induced soft errors. The SSE may be provided in a pipeline circuit of a TMRSM to receive and store a bit state of a bit signal generated by combinational circuits within the pipeline circuit. More specifically, the SSEs may be provided in a TMRSSE configured to perform self-correction. Also disclosed are methods for using the TMRSSE to test redundant pipeline stages of the TMRSM.Type: GrantFiled: October 24, 2013Date of Patent: May 26, 2015Assignee: Arizona Board of Regents, a body corporate of the State of Arizona, acting for and on behalf of Arizona State UniversityInventor: Lawrence T. Clark
-
Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related methods
Patent number: 9041448Abstract: Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch.Type: GrantFiled: March 5, 2013Date of Patent: May 26, 2015Assignee: QUALCOMM IncorporatedInventors: Yang Du, Jing Xie, Kambiz Samadi -
Publication number: 20150116019Abstract: Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.Type: ApplicationFiled: October 31, 2013Publication date: April 30, 2015Inventors: Steven K. HSU, Amit AGARWAL, Ram K. KRISHNAMURTHY
-
Patent number: 9013218Abstract: In an embodiment of the invention, a dual-port negative level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes low, CLKZ goes high, reset control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signal RET, the reset control signal REN and the control signals SS and SSN. The signals CKT, CLKZ, RET, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.Type: GrantFiled: June 23, 2014Date of Patent: April 21, 2015Assignee: Texas Instruments IncorporatedInventors: Steven Craig Bartling, Sudhanshu Khanna
-
Patent number: 9013219Abstract: A flip flop circuit has a first stage and a second stage. The first stage and the second stage each have interleaved filters.Type: GrantFiled: September 11, 2013Date of Patent: April 21, 2015Assignee: The Boeing CompanyInventors: Manuel F. Cabanas-Holmen, Ethan Cannon, Salim A. Rabaa
-
Patent number: 9007110Abstract: A register circuit adapted to store data is described. The register circuit comprises a master-slave flip flop coupled to receive the data to be stored by the master-slave flip flop at an input; and a delay element coupled to the master-slave flip flop, the delay element receiving a reference clock signal and generating a slave clock signal the slave clock signal which is delayed relative to a master clock signal. A method of storing data in a register circuit is also described.Type: GrantFiled: July 8, 2013Date of Patent: April 14, 2015Assignee: Xilinx, Inc.Inventor: Brian C. Gaide
-
Patent number: 9007111Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLKN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SS, RE and REN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.Type: GrantFiled: January 14, 2014Date of Patent: April 14, 2015Assignee: Texas Instruments IncorporatedInventors: Steven Bartling, Sudhanshu Khanna
-
Patent number: 9007112Abstract: A low power State Retention Power Gating (SRPG) cell has a retention component and a non-retention component, and is operable in a run state, a first retention state, and a second retention state. In the run state, the retention and non-retention components are powered with a supply voltage. In the first retention state, the retention component is powered at the same supply voltage as in the run state, and the non-retention component is powered down. In the second retention state, the retention component is powered at a lower supply voltage than in the run state, and the non-retention component is powered down.Type: GrantFiled: February 26, 2014Date of Patent: April 14, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Baiquan Shen, Xiaoxiang Geng, Shayan Zhang
-
Patent number: 8988124Abstract: An input buffer chooses, in accordance with first control clocks, to output an input data signal or output a high-impedance signal. A master flip-flop chooses, in accordance with second control clocks, to output a data signal received from the input buffer or retain a currently output data signal. A master-slave switch chooses, in accordance with the second control clocks, to output a high-impedance signal or output a data signal received from the master flip-flop. A slave flip-flop chooses, in accordance with the second control clocks, to retain a currently output data signal or output a data signal received from the master-slave switch. A clock buffer inputs the second control clocks, and generates and outputs the first control clocks.Type: GrantFiled: November 9, 2011Date of Patent: March 24, 2015Assignee: Renesas Electronics CorporationInventors: Masanao Yokoyama, Noboru Okuzono
-
Patent number: 8988123Abstract: Small area low power data retention flop. In accordance with a first embodiment of the present invention, a circuit includes a master latch coupled to a data retention latch. The data retention latch is configured to operate as a slave latch to the master latch to implement a master-slave flip flop during normal operation. The data retention latch is configured to retain an output value of the master-slave flip flop during a low power data retention mode when the master latch is powered down. A single control input is configured to select between the normal operation and the low power data retention mode. The circuit may be independent of a third latch.Type: GrantFiled: December 14, 2012Date of Patent: March 24, 2015Assignee: NVIDIA CorporationInventors: Ge Yang, Hwong-Kwo Lin, Xi Zhang, Jiani Yu
-
Publication number: 20150061741Abstract: In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element, a first data leg, and a second data leg. The first and second data legs may be coupled to the storage element. Clock selection logic may be coupled to the first and second data legs. The clock selection logic may have a select input for selecting between the first and second data legs. The slave latch may be coupled to the master latch.Type: ApplicationFiled: March 18, 2014Publication date: March 5, 2015Applicant: CAVIUM, INC.Inventors: Suresh Balasubramanian, Nitin Mohan, Manan Salvi
-
Publication number: 20150061740Abstract: In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element and at least two legs, including a data leg and at least one scan leg. The first node of the storage element may be driven by the data leg. The opposite node of the storage element may be driven by at least one of the scan legs. The slave latch may be coupled to the master latch.Type: ApplicationFiled: March 7, 2014Publication date: March 5, 2015Applicant: Cavium, Inc.Inventor: Suresh Balasubramanian
-
Patent number: 8957717Abstract: A scan flip-flop may include a selector outputting a data signal or a scan input signal in response to a scan enable signal, and a flip-flop that latches an output signal of the selector or the data signal, based on a clock signal and a low voltage signal.Type: GrantFiled: September 17, 2013Date of Patent: February 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventor: Min Su Kim
-
Patent number: 8957718Abstract: A flip-flop circuit has a master latch circuit and a slave latch circuit. In the flip-flop circuit, the master latch circuit and the slave latch circuit share at least a pair of transistors. In response to the clock signal, the signal held in the master latch circuit can be output at higher speed as the output signal via the intermediate node, the slave latch circuit and the output circuit. The flip-flop circuit can be reduced in cell size and improved in processing speed.Type: GrantFiled: July 29, 2013Date of Patent: February 17, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Muneaki Maeno
-
Patent number: 8957716Abstract: An integrated circuit cell includes a set of circuit elements associated with a logic function along a logical path between an input and an output of the integrated circuit cell. The set of circuit elements includes a first subset of circuit elements having a first width size and a first threshold voltage and configured to operate within a cycle of time. The set of circuit elements also includes a second subset of circuit elements having a second width size and a second threshold voltage and configured to operate within the cycle of time. The first subset and second subset of circuit elements are configured to toggle data between the input and the output. The second threshold voltage is less than the first threshold voltage when the second width size is less than the first width size.Type: GrantFiled: November 21, 2012Date of Patent: February 17, 2015Assignee: Broadcom CorporationInventor: Paul Penzes
-
Patent number: 8952739Abstract: A combination circuit generates first and second internal signals according to first and second input signals, respectively. A first master latch circuit selectively captures and holds a scan-in signal and the first internal signal, and generates a first output signal and a first intermediate signal based on the signals thus captured and held. A first slave latch circuit selectively captures and holds the first intermediate signal and the second internal signal, and generates a second output signal and a scan-out signal based on the signals thus captured and held. This arrangement reduces a circuit scale and power consumption of the input circuited provided in a semiconductor integrated circuit to which a scan path test method is applied.Type: GrantFiled: September 27, 2013Date of Patent: February 10, 2015Assignee: Panasonic CorporationInventors: Tsuyoshi Koike, Shigeo Houmura
-
Patent number: 8941427Abstract: A configurable flip-flop can be operated in a normal mode and a buffer mode. In the normal mode, the flip-flop latches data at the flip-flop input based on a clock signal. In the buffer mode, the flip-flop provides data at the flip-flop input to the flip-flop output, independent of the clock signal.Type: GrantFiled: December 15, 2011Date of Patent: January 27, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Shayan Zhang, Ravindraraj Ramaraju
-
Patent number: 8941428Abstract: A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop.Type: GrantFiled: April 9, 2014Date of Patent: January 27, 2015Assignee: ARM LimitedInventors: Virgile Javerliac, Yannick Marc Nevers, Laurent Christian Sibuet, Selma Laabidi
-
Patent number: 8941521Abstract: To decrease the burden of digital processing, provided is an AD conversion apparatus comprising a pattern generating section that, for each target bit specified one bit at a time moving downward in the output data, generates a pattern signal having a pulse width or number of pulses corresponding to a weighting of the target bit; an integrating section that integrates the pattern signals according to a judgment value for judging a value of the target bit each time a pattern signal is generated, and outputs a reference signal obtained by accumulating the integrated value of each pattern signal; a comparing section that, each time generation of a pattern signal is finished, compares the input signal to the reference signal; and an output section that outputs the output data to have values corresponding to the comparison results obtained after each generation of a pattern signal corresponding to a bit is finished.Type: GrantFiled: January 29, 2013Date of Patent: January 27, 2015Assignee: Advantest CorporationInventor: Yasuhide Kuramochi
-
Patent number: 8928378Abstract: In accordance with an embodiment, an integrated circuit comprises a master-slave flip-flop, a selection logic circuit, and a pass structure. The selection logic circuit is configured to selectively enable or disable one or more clock signals. The pass structure is configured to pass a data signal to the master-slave flip-flop in response to a selected clock signal being enabled.Type: GrantFiled: April 30, 2010Date of Patent: January 6, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Miaosong Wu
-
Patent number: 8928377Abstract: A scannable fast dynamic register including a data and scan enable circuit, a precharge circuit, a select circuit, a store circuit, and a scan input enable circuit. The data and scan enable circuit pulls a first precharge node to a discharge node in response to the clock upon evaluation in normal mode. The precharge circuit precharges first and second precharge nodes high, in which one of the precharged nodes discharges depending upon whether a data block evaluates. The store circuit and an output gate are responsive to the second precharge node to provide the output. The select circuit is interposed before the store circuit to allow injection of scan data in a scan mode. In scan mode, the scan input enable circuit provides scan data to the select and store circuits. The scan input enable circuit also includes a store circuit which operates with the first store circuit in a master-slave configuration.Type: GrantFiled: July 25, 2013Date of Patent: January 6, 2015Assignee: VIA Technologies, Inc.Inventor: Imran Qureshi
-
Publication number: 20140368246Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.Type: ApplicationFiled: June 4, 2014Publication date: December 18, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chung-Hee KIM, Min-Su KIM, Ji-Kyum KIM, Emil KAGRAMANYAN, Dae-Seong LEE, Gun-Ok JUNG, Uk-Rae CHO
-
Patent number: 8901979Abstract: In accordance with an embodiment, a description is given of a storage circuit including an input stage configured to provide a value to be stored, a storage stage configured to store the value to be stored, an output stage configured to output a value stored by the storage circuit, and a control circuit, wherein the control circuit is configured to receive a signal from the output stage, which signal indicates the charge state of the output stage, and, if the charge state of the output stage is equal to a predefined precharge state, to output an activation signal to the storage stage, and wherein the storage stage is configured to store the value to be stored, provided by the input stage, in reaction to the activation signal.Type: GrantFiled: November 26, 2013Date of Patent: December 2, 2014Assignee: Infineon Technologies AGInventor: Thomas Kuenemund