Abstract: An input/output circuit may include an input circuit, an amplifier circuit and a precharging circuit. The input circuit may load differential input data to setup nodes based on a data strobe clock. The amplifier circuit may compare and amplify the data that is loaded to the setup nodes and configured to output the amplified data. The precharging circuit may precharge the setup nodes based on the data strobe clock and the differential input data.

Abstract: An embodiment of a novel memory circuit is described that improves post aging performance of a shared VCC node with a write pre-charge on the supply line. A write pre-charge PMOS device is added to the shared VCC node in some embodiments. The write pre-charge circuit helps insure that the shared VCC node has a healthy voltage value at the beginning of a write phase and also enables the memory circuit to recover the shared VCC value after the write phase (e.g., immediately following), enabling a read operation after a write operation for a same register file entry or adjacent entries (e.g., entries connected to the same shared VCC node). Other embodiments are disclosed and claimed.

Abstract: Methods, systems, and devices for a single plate configuration and memory array operation are described. A non-volatile memory array may utilize a single plate to cover a subset of the array. One or more memory cells of the subset may be selected by operating the plate and an access line of an unselected memory cell at a fixed voltage. A second voltage may be applied to an access line of the selected cell, and subsequently reduced to perform an access operation. Removing the applied voltage may allow for the memory cell to undergo a recovery period prior to a subsequent access operation.

Abstract: The present disclosure provides a shift register, a gate line driving circuit, an array substrate and a display apparatus. The shift register comprises: an inputting circuit for controlling a potential of a pulling up node (PU); a pulling down driving circuit for controlling the potentials of the PU and a pulling down node to be different; a resetting circuit for pulling down the PU and a signal outputting terminal (Output); a first outputting circuit for pulling down the Output; a second outputting terminal for outputting a signal from a clock signal terminal via the Output; a controlling circuit for connecting the second outputting circuit with the PU when the PU is at a high level and pulling the first terminal of the second outputting circuit down to a potential as twice as the potential of the low level signal terminal when the PU is at a low level.

Abstract: A circuit includes a plurality of first circuits, a selection circuit, and a second circuit. The selection circuit is configured to selectively couple a first circuit of the plurality of first circuits with the second circuit. The first circuit includes a first data line and a second data line; and a pair of cross-coupled transistors of a first type coupled with the first data line and the second data line. The second circuit includes a first switching circuit and a second switching circuit; and a pair of cross coupled transistors of a second type different from the first type. The pair of cross-coupled transistors of the first circuit and the pair of cross-coupled transistors of the second circuit are configured as part of a sense amplifier when the first switching circuit and the second switching circuit are turned on.

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

Abstract: The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.

Abstract: Clock alignment circuitry may include phase comparator circuitry with a first input terminal that receives as first clock signal from a first clock tree and a second input terminal that receives a second clock signal from a second clock tree. The phase comparator circuitry may compare the first and second clock signals and generate different control signals based on the first and second clock signals. The integrated circuit may further include phase interpolator circuitry that generates an output clock signal based on at least one of the control signals received from the phase comparator circuitry. Edges of the generated output clock signal may align with edges of either the first clock signal or the second clock signal.

Abstract: A slicer includes a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal. The first latch further includes a developing transistor configured to receive a second clock signal, wherein the first clock signal is different from the second clock signal. The first latch further includes a first input transistor configured to receive a first input. The first latch further includes a second input transistor configured to receive a second input, wherein the first and second input transistors are connected with the developing transistor. The first latch further includes at least one pre-charging transistor configured to receive a third clock signal, wherein the at least one pre-charging transistor is connected to a first output node and a second output node. The slicer further includes a second latch connected to the first and second output nodes and to a third output node.

Abstract: An inverter and an antenna circuit. The inverter that receives control signals including a first control signal, a second control signal, and a third control signal, inverts the first control signal, and outputs the inverted first control signal, includes: a first MOS transistor having a gate to which the first control signal is applied and a source that is grounded; a second MOS transistor having a gate to which the third control signal is applied and a source to which the second control signal is applied; and a third MOS transistor having a gate to which the second control signal is applied and a source to which the third control signal is applied, wherein drains of the first MOS transistor, the second MOS transistor, and the third MOS transistor are connected to an output terminal.

Abstract: This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal.

Abstract: Embodiments of a synchronization circuit are described. This synchronization circuit includes multiple selectively coupled synchronization stages which are configurable to synchronize data and control signals between a first time domain and a second time domain, where the synchronization can be performed based on asynchronous or synchronous events associated with either the first time domain or the second time domain. Additionally, the synchronization circuit includes control logic, coupled to the synchronization stages, which is configured to adapt a number of synchronization stages used to synchronize the data and the control signals based on an estimate of a probability of metastability persisting to an output of the synchronization circuit during the synchronization.

Abstract: A data holding circuit including a first input terminal through which data is inputted; at least one delay element for delaying the data inputted through the first input terminal; and a first element for holding data, wherein, when the data inputted through the first input terminal and the data delayed by the delay element are equal to each other, the first element holds data corresponding to the data inputted through the first input terminal and wherein, when the data inputted through the first input terminal and the data delayed by the delay element are different from each other, the first element continues to hold the data presently held by the first element.

Abstract: A latch circuit includes an input transistor, a retention capacitor connected between an electrode of the input transistor and a first latch control line, a first transistor having an electrode connected to the first latch control line and a gate connected to the electrode of the input transistor, a second transistor having a gate connected to another electrode of the first transistor and an electrode is connected to the second latch control line, a third transistor having a gate connected to the another electrode of the first transistor and an electrode connected to another electrode of the second transistor and another electrode connected to an output terminal.

Abstract: A method for determining flop circuit types includes performing a layout of an IC design including arranging master and slave latches of each of a plurality of flops to receive first and second clock signals, respectively. The initial IC design may then be implemented (e.g., on a silicon substrate). After implementation, the IC may be operated in first and second modes. In the first mode, the master latch of each flop is coupled to receive a first clock signal. In the second mode, the first clock signal is inhibited and the master latch is held transparent. The slave latch of each flop operates according to a second clock signal in both the first and second modes. The method further includes determining, for each flop, whether that flop is to operate as a master-slave flip-flop or as a pulse flop in a subsequent revision of the IC.

Abstract: A communication apparatus including a clock generation circuit outputting a plurality of clocks, each clock having a different phase from the other, a synchronization detection block receiving a sync word and a payload having a predetermined length after receiving the payload, sampling the sync word by using each of the plurality of clocks and to output a first signal indicating a clock or clocks capable of sampling the sync word successfully, the synchronization detection block being capable of sampling the payload by using a clock or clocks, a clock phase selection block coupled to the synchronization detection block to receive the first signal, and a clock gate unit to receive each of the plurality of clocks and the second signal to output the selected one of the plurality of clocks, and not to output a rest of the plurality of the clocks based on the second signal.

Abstract: A latch circuit has: a data input unit to which an input data is input; and a data retention unit including a node connected to the data input unit. The data input unit transmits a data depending on the input data to the node, when both of a first clock signal and a second clock signal that are driven independently from each other are at a first level. The data retention unit holds a data at the node, when at least one of the first clock signal and the second clock signal is at a second level that is an inverted level of the first level.

Abstract: A shift register is disclosed.

Abstract: An integrated circuit (400) includes at least one clocked latch circuit (410). The clocked latch circuit (400) includes a first stage (415) including a latch node (420) positioned between a first pull up device (416) and a first (417) and at least a second pull down device (418), wherein the first stage (415) is operative to receive inputs comprising a data signal (D), a clock signal (CLK) and a clocked complement of the data signal (CDXX). A second stage (441) includes a second pull up device (442) and a third pull down device (445) having the latch node (420) therebetween, wherein at least one gate of the first pull up device (416) and the first (417) and second pull down device(418) is directly coupled to a gate of the second pull up device (442) or the third pull down device (445). An output inverter is coupled to the latch node (420).

Abstract: A latch includes: an amplifying circuit, for receiving a first bias current in a first state for amplifying an input signal to generate an amplified signal; a latching unit, for latching the amplified signal and receiving a second bias current in a second state to output the amplified signal; and a biasing circuit, for providing a biasing current to the amplifying circuit, and providing the second biasing current to the latching unit. The biasing circuit includes: a first biasing module for providing a third biasing circuit to the amplifying circuit in the first state; and a second biasing module, for providing a fourth biasing current to the amplified circuit; wherein the first biasing circuit is equal to a sum of the third biasing current and the fourth biasing current.

Abstract: A level shifter is provided. The level shifter includes a first input transistor, a second input transistor, a first bias transistor, a second bias transistor, a first switch transistor and a second switch transistor. At the time of change of the signal status, by raising the potential of the body terminal of the first input transistor, the threshold voltage is reduced so that the current flowing through the second input transistor is increased to shorten the time of the change of the signal status.

Abstract: A clocked scan flip-flop 2 is provided in which a latch 14 within the diagnostic data path is reused to store an operational signal value during a sleep mode. The operational signal value is supplied to the latch 14 via a sleep mode path 20 through a transmission gate 22 (or other tristate driver) controlled by a sleep mode control signal SLP. The diagnostic clock signal SCLK, the operational clock signal CLK and the sleep mode control signal SLP together provide the control operations for controlling the various elements within the clocked-scan flip-flop 2 to move into and out of sleep mode.

Abstract: A latch circuit to perform high-speed input and output operations by reducing a load of an input circuit or an output circuit of the latch circuit. The latch circuit includes four or more inverters connected in a loop to hold a signal, a plurality of input terminals respectively connected to different nodes, and a plurality of output terminals respectively connected to different nodes. At least one input terminal of the latch circuit is used for normal operation of the latch circuit, and at least one input terminal is used for a test operation of the latch circuit. Further, at least one output terminal of the latch circuit is used for normal operation of the latch circuit, and at least one output terminal is used for a test operation of the latch circuit. The latch circuit reduces the number of circuit elements at a connecting point of an input terminal of the latch circuit or at a connecting point of an output terminal of the latch circuit.

Abstract: A testable, pulse-triggered static flip-flop. A pulse generator produces a data enable trigger pulse only when a test enable input is low, and a scan test enable trigger pulse only when a test enable input is high. The data enable trigger pulse controls the data input to the flip-flop, while the scan test enable trigger pulse controls the scan test input to the flip-flop. The flip-flop consists of a selection circuit comprised of two latches, each including an inverter and a transmission gate. One latch receives the data input and the other latch receives the scan test input. The data enable trigger pulse controls the transmission gate receiving the data input, and the scan test trigger pulse controls the transmission gate receiving the scan test input. The flip-flop also includes a keeper circuit consisting of a feedback inverter and a static latch.

Abstract: An exemplary skew-tolerant true-single-phase-clocking (TSPC) flip-flop is disclosed that reduces current spikes by allowing willful introduction of skew in the clock tree of a single-phase circuit design. More precisely, a split-clock TSPC flip-flop, which allows the flip-flop hold times to be met in the face of skewed clocks, which, in turn, reduces the maximum value of current spikes, can be substituted for a traditional TSPC flip-flop in a sequential logic circuit. The input of the split-clock TSPC flip-flop is latched according to a first clock signal, which was used in a preceding stage, while the output of the split-clock TSPC flip-flop is driven according to a second clock signal. The first and second clock signals can be skewed in time, but have the same frequency and substantially the same phase. Metal Oxide Semiconductor (MOS) device can also be included within the split-clock TSPC flip-flop to reduce power dissipation in cases of large clock skew.

Abstract: A label printer-cutter includes a frame and a print head assembly connected to the frame. The print head assembly includes a print head for printing to a label media. The label printer-cutter includes a cutting assembly connected to the frame, and the cutting assembly is for catting the label media. The printer-cutter also includes a controller in operative association with the print head assembly and cutting assembly. The controller can be programmed to control the print head assembly and the cutting assembly such that printing to and cutting of the label media does not occur simultaneously in the label printer-cutter. Printing by the print head is controlled to correspond to cutting assembly rollers being positioned in a non-cutting position. Advantageously, printing to and cutting of a label media in a single label printer-cutter unit is accomplished in an efficient and cost-effective manner.

Abstract: An apparatus comprising a first one or more threshold devices, a second one or more threshold devices and a logic device. The first one or more threshold devices may be configured to control an output. The second one or more threshold devices may be configured to receive the output. The logic device may be (i) coupled to the second one or more threshold devices and (ii) configured to provide a feedback to the first one or more threshold devices. The feedback may be configured to force a reset condition if a metastable event occurs.

Abstract: A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention includes an antenna for receiving transmitting RF signals, a PLL for generating multi-phase clock signals having a frequency different from a carrier frequency in response to the multi-phase clock signals and a reference signal having the carrier frequency, a demodulation-mixing unit for mixing the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output the RF signals having a frequency reduced by the carrier frequency and an A/D converting unit for converting the RF signals from the mixing unit into digital signals.

Abstract: A latch control circuit for overcoming phase uncertainty between crossing clock domains, which includes an interface and control circuit for controlling and communicating data between the clock domains and, which also includes either static or dynamic initialization circuitry.

Abstract: A low hold time flip-flop that has a dynamic input stage and a static output stage is provided. The flip-flop uses a feedback stage to maintain a value on a dynamic node during an evaluation phase of the flip-flop so that an input to the flip-flop only has to be held for a relatively short period of time after the start of the evaluation phase.

Abstract: A new D-type latch structure is disclosed which has an input data sampling circuit and a symmetrical cross coupled latching circuit. The clock is delayed a predetermined time through an inverter circuit. The clock and the delayed inverted clock are used to generate a clock window time during which time the data input state and the inverted data input state are asserted on the latch output and complementary. The latch outputs are cross-coupled to pull-up and pull-down circuitry in each output circuit stage. A common pull-down transistor may be used to further reduce devices and to improve path delays from clocks to the latch outputs. The clock window assertion of states of the data inputs to the changing latch output is enhanced by the cross-coupled feedback of the latch outputs to improve the differential transition timings of the latch outputs. The D-type latch has fewer transistors and better delay, and more precise transition skew over prior art designs.

Abstract: A controllable latch/register circuit for an integrated circuit comprises an input latch (30) coupled in series with an output latch (32). The latches are operated under control of a control circuit (34) having mode inputs. In one mode, the latches are operated as a non-transparent register; the output latch (32) holds the output stable while new data is inputted to the input latch (30); the output latch (32) is only opened once the input latch has been latched closed. In one or more other modes, the latches are operated as a single controllable transparent latch; for example, one or the latches (30) can be held permanently open such that operation of the circuit depends entirely on the state of the other latch (32).

Abstract: A dynamic latch receiver device comprises a sequence of data latch devices arranged in parallel for enabling sequential latching of data signals communicated serially on a single data line. The device includes a first pointer signal generator for generating a sequence of one or more first pointer signals, each generated first pointer signal of a sequence corresponding to a specific latch device and overlapping in time with a prior generated first pointer signal of the sequence; and, a pulse converter device associated with a latch device for receiving a corresponding first pointer signal and generating a respective second pointer signal for input to a respective latch device, each second pointer signal generated in a non-overlapping sequence for triggering a respective latching of each data signal in synchronism with serially communicated data signals.

Abstract: A semiconductor integrated circuit includes a first shift register composed of a plurality of first flipflops each including a first selector for selecting a first or second clock, a second selector for selecting an inverted signal of the first clock or a third clock, a third selector for selecting a first data signal or a first scanning signal, a first latch circuit for latching an output of the third selector, and a second latch circuit for latching an output of the first latch circuit. The semiconductor integrated circuit further includes a second shift register composed of a plurality of second flipflops each including a fourth selector for selecting a second data signal or a second scanning signal, a third latch circuit for latching an output of the fourth selector, and a fourth latch circuit for latching an output signal of the third latch circuit.

Abstract: In transmitting a first pair of differential clock signals UCLK, UXCLK having an extremely small amplitude voltage based on a power-source potential and a second pair of differential clock signals LCLK, LXCLK having an extremely small amplitude voltage based on the power-source potential, an inverting circuit as a signal receiving circuit is composed of a CMOS inverting circuit. A PMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the first pair of differential clock signals. An NMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the second pair of differential clock signals. When the potentials of the differential clock signals change, potentials at the respective gate and source electrodes of the two transistors shift in opposite directions, which surely cuts off the transistors.

Abstract: There is disclosed a multi-power supply integrated circuit including a first pMOS transistor which is formed in a first n-well and operated at a first supply voltage and a second pMOS transistor which is formed in a second n-well and operated at a second supply voltage being lower than the first supply voltage, wherein the first n-well and the second n-well are placed adjacently to put a boundary line therebetween and also the first supply voltage is supplied to both the first and second n-wells. Because a space between the first and second n-wells is made small, a gate array LSI with a reduced chip area is provided. A common n-well may be formed in place of the first and second n-wells.

Abstract: A multi-clock pulse synchronizer circuit with and IN-section receiving and storing prescribed in-pulses and input clock signals and responsively outputting intermediate pulses; and an OUT-section for receiving and storing the intermediate pulses, synchronous with certain output clock signals and processing them to generate certain output-signals, for better avoiding metastability.

Abstract: A flip-flop cell having a main data input, a main scan data input, a main data output and a main clock input. The flip-flop cell includes a multiplexer having first and second inputs and an output. The first input is coupled to the main data input of the flip-flop cell and the second input is coupled to the main scan data input of the flip-flop cell. A first latch has a data input, a data output and an inverting clock input. The data input of the first latch is coupled to the output of the multiplexer. A second latch has a data input, a data output and a non-inverting clock input. The data input of the second latch is coupled to the data output of the first latch. A third latch has a data input, a data output and an inverting clock input. The data input of the third latch is coupled to the data output of the second latch, and the data output of the third latch is coupled to the main data output of the flip-flop cell.

Abstract: A metastableproof flip-flop receives an input value on a flip-flop input. The flip-flop holds an output value on a flip-flop output. In response to a transition of a clock signal, a transition in the output value occurs. The new output value is the input value formerly received by the flip-flop. In order to make the flip-flop metastableproof, the transition in the output value is delayed when the input value is in a metastable state. When the input value is no longer in the metastable state, then the transition in the output value is allowed to complete.

Abstract: A method of identifying potential clock qualifiers in netlist description of an integrated circuit, the netlist comprising logic elements. The method comprises the steps of initializing every net of the netlist to a speed of zero, identifying all potential clock nets so that all signals with a path to a clock source has a speed of one, computing the maximum speed of each output net of each of the logic elements in the netlist, and marking as a potential clock qualifier any net of the netlist that is input to the logic elements in the netlist that is slower than the maximum speed of any net that is input to the logic elements.

Abstract: The present invention ensures that the entire data path of the synchronous integrated circuit device composed of master and slave latches is initialized upon power-up in a test mode, thereby overcoming a prior art problem of non-initialization of the device data path. In the test mode, the master clock signal is initialized internally to the synchronous integrated circuit device to allow the master latch to conduct. A clock signal which is a derivative of a master clock signal is controlled to be equal to a first logic state in order to control a slave latch element of the synchronous integrated circuit device to conduct, regardless of the state of the master clock signal. Controlling the clock signal to be equal to the first logic state allows the clock signal to be able to control the slave latch element so that entire data path of the integrated circuit device is initialized upon power-up of the device in the test mode.

Abstract: Described are techniques to stabilize storage devices receiving signals from plural asynchronous docks, especially to avoid "metastability", in particular, a multi-dock pulse synchronizer circuit with an IN-section for receiving and storing prescribed impulses and input cock signals, and for responsively outputting intermediate signals: and an OUT-section for receiving and storing the intermediate pulses, synchronous with certain output clock signals and processing them to generate certain output-signals which avoid metastability.

Abstract: A latch, connected between an input self-reset dynamic MOS logic circuit and an output self-reset dynamic MOS logic circuit, is provided with clocked interface circuitry to assure proper latching of the state of the input logic in the latch and provides a pulsed output to the output logic circuit. Circuitry is provided to control the self-reset operation of the input logic circuit such that the reset does not occur until a predetermined period of time after the leading edge of the clock pulse latching the state of the input self-reset circuit in the latch. The output of the latch is gated from the latch to the output self-reset circuit under the control of a chopper circuit. The chopper circuit provides a control pulse to gate the state of the latch to the output self-reset circuit a predetermined period of time after the data has been latched. The control pulse has a duration sufficient to assure that the state of the latch is registered in the output self-reset logic.

Abstract: A toggle flip-flop circuit is described incorporating eight bi-directional switches which may be dual rail wherein each bi-directional switch for each rail includes an n and p channel transistor coupled in parallel. Clock input signals may have rise and fall times longer than the RC time constant of a bi-directional switch and node capacitance being charged which dissipates, very low power across the switch. The invention provides a practical toggle flip-flop circuit using adiabatic switching for very low power dissipation.