With Clock Input Patents (Class 327/212)
  • Patent number: 10505767
    Abstract: Disclosed herein are related to a system and a method for high speed communication. In one aspect, the system includes a set of slicers configured to generate a slicer output signal digitally indicating a level of an input signal received by the set of slicers. The system includes a speculative tap coupled to the set of slicers, where the speculative tap is configured to select bits of the slicer output signal based on selected bits of a prior slicer output signal. The system includes a decoder coupled to the speculative tap, where the decoder is configured to decode the selected bits of the slicer output signal in a first digital representation into a second digital representation. The system includes a feedback generator coupled to the decoder, where the feedback generator is configured to generate a feedback signal according to the decoded bits of the slicer output signal.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: December 10, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Heng Zhang, Jaehun Jeong, Bo Zhang, Arvindh Iyer, Kumar Thasari, Ullas Singh, Namik Kocaman
  • Patent number: 10497335
    Abstract: A display device comprises: a pixel array including pixels connected to gate lines; a gate driver that sequentially supplies scan signals to the gate lines by using a plurality of stages connected in cascade; and a driving voltage generator that supplies first and second driving voltages to the gate driver and inverts the first and second driving voltages of opposite phases at given intervals, wherein an nth stage (n is a natural number), among the stages of the gate driver, comprises: a start controller that charges a Q1 node in a period when an (n?1)th scan signal and a first clock signal are synchronized, and charges a Q1B node in a period when an (n?1)th carry signal, opposite in phase to the (n?1)th scan signal, and the first clock signal are synchronized; a first node controller that charges a Q2 node or a Q2B node in response to a voltage at the Q1 node; a first output control transistor that outputs an nth scan signal through a Q node in response to a voltage at the Q2 node; and a second output contro
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: December 3, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Seok Noh, Injune Kim, Kimin Son
  • Patent number: 10338820
    Abstract: A system architecture conserves memory bandwidth by including compression utility to process data transfers from the cache into external memory. The cache decompresses transfers from external memory and transfers full format data to naive clients that lack decompression capability and directly transfers compressed data to savvy clients that include decompression capability. An improved compression algorithm includes software that computes the difference between the current data word and each of a number of prior data words. Software selects the prior data word with the smallest difference as the nearest match and encodes the bit width of the difference to this data word. Software then encodes the difference between the current stride and the closest previous stride. Software combines the stride, bit width, and difference to yield final encoded data word. Software may encode the stride of one data word as a value relative to the stride of a previous data word.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: July 2, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Rouslan Dimitrov, Jeff Pool, Praveen Krishnamurthy, Chris Amsinck, Karan Mehra, Scott Cutler
  • Patent number: 10019958
    Abstract: A display panel includes a substrate, a plurality of pixels, a plurality of scan lines, a pull-down control circuit, and a gate driving circuit. The pixels are disposed on a display area of the substrate. The scan lines are disposed on the substrate and respectively coupled to the corresponding pixels. The pull-down control circuit is disposed on a peripheral area of the substrate, receives a plurality of clock signals, and has a plurality of pull-down units to provide a plurality of pull-down signals. The gate driving circuit is disposed on the peripheral area and has a plurality of shift registers. The shift registers are coupled to the scan lines to provide a plurality of gate driving signals and pull down the gate driving signals in sequence according to the pull-down signals. The pull-down control circuit and the gate driving circuit are arranged along a side of the display area.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: July 10, 2018
    Assignee: Chunghwa Picture Tubes, LTD.
    Inventors: Wei-Lung Li, Chih-Wen Lai
  • Patent number: 9893721
    Abstract: An edge detector includes a differential signal generator, a sense amplifier and a latch. The differential signal generator delays an input signal to generate a first differential signal and inverts the input signal to generate a second differential signal. The sense amplifier amplifies a difference between the first differential signal and the second differential signal to generate a first amplification signal and a second amplification signal at a first edge of a test clock signal and resets the first amplification signal and the second amplification signal at a second edge of the test clock signal. The latch generates an edge signal corresponding to edge information of the input signal in response to the first amplification signal and the second amplification signal.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: February 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Seok Lee, Woo-Seok Kim, Jae-Jin Park, Dong-Hyuk Lim, Dae-Young Chung
  • Patent number: 9837036
    Abstract: A gate driving circuit including: a plurality of stages outputting signals to gate lines, the stages includes a first transistor of which one end and a control terminal are connected, one end and the control terminal are connected with a first input terminal, and the other end is connected to a second node, a second transistor including a control terminal connected to a first node, connected with a clock input terminal, and the other end connected to a first output terminal, a first capacitor of which one end is connected to the first node, the other end is connected to the other end of the second transistor and the first output terminal, and a third transistor of which one end is connected to the other end of the first transistor, the other end is connected with the first node, and a control terminal is connected to a third node.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: December 5, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tadashi Amino, Jong Hee Kim, Masataka Kano, Jun Hyun Park
  • Patent number: 9530371
    Abstract: The present invention relates to a GOA circuit for tablet display and a display device. The GOA circuit comprises cascaded plurality of GOA units, the GOA unit comprises a pull-up control part 400 and a transfer part 500; the transfer part 500 comprises a first thin film transistor T22, the gate thereof is connected with the gate signal point Q(n), the drain and the source are respectively input the clock signal CK(n) and output the turn-on signal ST(n); the pull-up control part comprises: a second thin film transistor T11, the gate thereof is input the turn-on signal ST(n?2), the drain and the source are respectively connected with the horizontal scan line G(n?2) and the gate signal point Q(n); a third tin film transistor T12, the gate thereof is connected with the horizontal scan line G(n?1), the drain and the source are respectively connected with the horizontal scan line G(n?1) and the gate signal point Q(n). The present invention also provides a related display device.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: December 27, 2016
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Xiaojiang Yu, Wenying Li, Changyeh Lee, Tzuchieh Lai
  • Patent number: 9424894
    Abstract: A signal transfer circuit includes a signal input unit suitable for generating an input signal corresponding to a first voltage level and a second voltage level, a transfer control unit suitable for controlling a driving path of a transfer node in response to a control signal and selectively driving the transfer node to the second voltage level or a third voltage level, which is higher than the first voltage level, based on the driving path in response to the input signal, and an output control unit suitable for outputting an output signal by driving an output node based on a voltage level of the transfer node or maintaining a previous voltage level of the output node in response to the control signal.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: August 23, 2016
    Assignee: SK Hynix Inc.
    Inventors: Youk-Hee Kim, Yong-Ju Kim
  • Patent number: 9324715
    Abstract: A semiconductor device includes a substrate including PMOSFET and NMOSFET regions. First and second gate electrodes are provided on the PMOSFET region, and third and fourth gate electrodes are provided on the NMOSFET region. A connection contact is provided to connect the second gate electrode with the third gate electrode, and a connection line is provided on the connection contact to cross the connection contact and connect the first gate electrode to the fourth gate electrode.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: April 26, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Raheel Azmat, Rwik Sengupta, Chulhong Park, Kwanyoung Chun
  • Patent number: 9324288
    Abstract: The present invention provides a self-compensating gate driving circuit which comprises a plurality of GOA units which are cascade-connected, and a Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area. The Nth GOA unit comprises a pull-up controlling part, a pull-up part, a transmission part, a first pull-down part, a bootstrap capacitor part and a pull-down holding part. The pull-up part, the first pull-down part, the bootstrap capacitor part and the pull-down holding part are respectively coupled to a Nth gate signal point Q(N) and the Nth horizontal scanning line G(n), and the pull-up controlling part and the transmission part are respectively coupled to the Nth gate signal point Q(N), and the pull-down holding part is inputted with a DC low voltage VSS.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: April 26, 2016
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Chao Dai
  • Patent number: 9300506
    Abstract: A clock synchronization circuit is configured to capture an input data bit according to an input clock signal, and to synchronize and output the input data bit. The clock synchronization circuit includes a clock buffer for generating an internal clock signal according to the input clock signal and transmitting the internal clock signal to a clock line. The clock synchronization circuit further includes a D flip-flop for capturing and outputting the input data bit at an edge timing of the internal clock signal. The clock buffer includes an inverter core portion and an electric current suppressing portion. The inverter core portion is configured to generate the internal clock signal through alternately supplying an electric current to the clock line and drawing the electric current from the clock line according to the input clock signal. The electric current suppressing portion is configured to suppress an amount of the electric current.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: March 29, 2016
    Assignee: LAPIS SEMICONDUCTOR CO., LTD
    Inventor: Kenji Arai
  • Patent number: 9130555
    Abstract: A circuit including: an input stage that includes a first input unit into which input data is input and a pair of first output units and is driven by a first power-supply voltage; a pair of first gate elements that includes first transistors, and is driven by a clock that includes a second power-supply voltage that is lower than the first power-supply voltage; a first latch circuit that includes a pair of second input units, and is driven by the first power-supply voltage; a pair of second gate elements that includes second transistors, and is driven by an inverted clock of the clock; and a second latch circuit that includes a pair of third input units, and a third output unit that outputs one of a pair of pieces of data, and is driven by the first power-supply voltage.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: September 8, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Satoshi Tanabe, Kenichi Kawasaki
  • Publication number: 20150130524
    Abstract: A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention register and reducing power to a volatile stage of the retention register. The non-volatile stage may be powered by an external voltage source. The volatile stage may be powered by an internal voltage source.
    Type: Application
    Filed: January 26, 2015
    Publication date: May 14, 2015
    Inventors: Ramaprasath Vilangudipitchai, Prayag Bhanubhai Patel
  • Patent number: 9018976
    Abstract: In an embodiment of the invention, a dual-port positive level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: April 28, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Steven C. Bartling, Sudhanshu Khanna
  • Publication number: 20150102847
    Abstract: An example embodiment discloses a flip-flop including a first inverter configured to invert first data, first and second transistors connected to each other in series and configured to receive the inverted first data and a first clock, respectively, a third transistor and a first gate configured to perform a logic operation on the first data and the first clock, the third transistor configured to receive an output of the logic operation. The second transistor and the third transistor are connected to a first node.
    Type: Application
    Filed: July 24, 2014
    Publication date: April 16, 2015
    Inventors: Rahul SINGH, Min-Su KIM, Chung-Hee KIM
  • Patent number: 9007113
    Abstract: According to one aspect of the present disclosure, there is provided a flip flop circuit, comprising a first input circuit configured to receive a clock input signal and input data and comprising a first node. The flip-clop circuit further comprises a second input circuit configured to receive the input data and an inverse of the clock signal and comprising a second node. The first and second input circuits are configured such that the first node and the second node are pre-charged to respective complementary states when the clock signal is at a first level and, dependent on a value of the input data, one of said first and second nodes changes state to a state complementary to its pre-charged state when the clock signal transitions from the first level to a second level.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: April 14, 2015
    Assignee: NVIDIA Corporation
    Inventors: Stephen Felix, Stéphane Badel
  • Patent number: 9007091
    Abstract: In an embodiment of the invention, a dual-port positive level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: April 14, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Steven C. Bartling, Sudhanshu Khanna
  • Publication number: 20150077162
    Abstract: A transistor with excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) is provided. The transistor includes an oxide semiconductor layer including a channel formation region, a first gate electrode, a second gate electrode, a source electrode, and a drain electrode. The oxide semiconductor layer is between the first gate electrode and the second gate electrode. The oxide semiconductor layer has a pair of side surfaces in contact with the source electrode and the drain electrode and includes a region surrounded by the first gate electrode and the second gate electrode without the source electrode and the drain electrode interposed therebetween.
    Type: Application
    Filed: September 8, 2014
    Publication date: March 19, 2015
    Inventors: Shunpei Yamazaki, Masahiro Katayama, Kenichi Okazaki, Jun Koyama
  • Patent number: 8975934
    Abstract: A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention register and reducing power to a volatile stage of the retention register. The non-volatile stage may be powered by an external voltage source. The volatile stage may be powered by an internal voltage source.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: March 10, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Ramaprasath Vilangudipitchai, Prayag Bhanubhai Patel
  • Patent number: 8957717
    Abstract: A scan flip-flop may include a selector outputting a data signal or a scan input signal in response to a scan enable signal, and a flip-flop that latches an output signal of the selector or the data signal, based on a clock signal and a low voltage signal.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: February 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Min Su Kim
  • Patent number: 8957718
    Abstract: A flip-flop circuit has a master latch circuit and a slave latch circuit. In the flip-flop circuit, the master latch circuit and the slave latch circuit share at least a pair of transistors. In response to the clock signal, the signal held in the master latch circuit can be output at higher speed as the output signal via the intermediate node, the slave latch circuit and the output circuit. The flip-flop circuit can be reduced in cell size and improved in processing speed.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Muneaki Maeno
  • Patent number: 8952740
    Abstract: A pulsed latching apparatus and a method for generating a pulse signal are provided. The pulsed latching apparatus consists of a pulsed latch and a pulse signal generator. A data input terminal of the pulsed latch receives input data, the pulsed latch latches the input data according to a pulse signal, and transmits the latched input data through the data output terminal to serve as output data. The pulse signal generator duplicates a data transmission delay between the data input terminal and the data output terminal of the pulsed latch to obtain a duplicated delay. The pulse signal generator receives a clock signal, and processes the clock signal according to the duplicated delay to generate the pulse signal.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: February 10, 2015
    Assignee: Industrial Technology Research Institute
    Inventor: Shien-Chun Luo
  • Patent number: 8941428
    Abstract: A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: January 27, 2015
    Assignee: ARM Limited
    Inventors: Virgile Javerliac, Yannick Marc Nevers, Laurent Christian Sibuet, Selma Laabidi
  • Publication number: 20150003177
    Abstract: Disclosed herein is a device includes a command generation circuit that activates first and second command signals, an internal circuit that includes a plurality of transistors that are brought into a first operation state when at least one of the first and second command signals is activated, and an output gate circuit that receives a first signal output from the internal circuit, the output gate circuit being configured to pass the first signal when the second command signal is deactivated and to block the first signal when the second command signal is activated.
    Type: Application
    Filed: June 26, 2014
    Publication date: January 1, 2015
    Inventor: Keisuke Fujishiro
  • Patent number: 8917800
    Abstract: A mechanism is provided for dynamically adjusting DC offset at the time of deviation from DC balance ½ (DC level) in a data pattern including long-period consecutive bits generating DC offset in a section of data. A receiver circuit unit of an LSI having a serializer/deserializer arrangement for performing high-speed serial transmission includes an offset adjusting circuit. The offset adjusting circuit calculates DC balance in an arbitrary section of data by averaging received serial data. Based on comparison between a DC level and the DC balance obtained by averaging the received data, offset is shifted toward the H side when the DC balance exists on the H side from the DC level, and shifted toward the L side when the DC balance exists on the L side.
    Type: Grant
    Filed: August 10, 2013
    Date of Patent: December 23, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Akira Matsumoto, Naoki Mori, Takashi Yagi
  • Patent number: 8901973
    Abstract: A multi-band frequency multiplier configured to generate frequencies and multiplied frequencies in an integrated system. The multi-band frequency multiplier includes a multi-band multiplier core with a multiplier core differential amplifier configured to receive a multiplier input signal. A switchable load impedance connects to the multiplier core differential amplifier, and includes n multiplier sections. Each multiplier section includes a section impedance and a section switch. The multiplier core differential amplifier generates an output signal having a frequency substantially equal to k times the input frequency in a range of a selected one of n critical frequencies when a selected one of the section switches corresponding to the selected one of the n critical frequencies is triggered.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: December 2, 2014
    Assignee: Keysight Technologies, Inc.
    Inventors: Eric R. Ehlers, Bobby Yubo Wong
  • Patent number: 8878585
    Abstract: A slicer includes a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal. The first latch further includes a developing transistor configured to receive a second clock signal, wherein the first clock signal is different from the second clock signal. The first latch further includes a first input transistor configured to receive a first input. The first latch further includes a second input transistor configured to receive a second input, wherein the first and second input transistors are connected with the developing transistor. The first latch further includes at least one pre-charging transistor configured to receive a third clock signal, wherein the at least one pre-charging transistor is connected to a first output node and a second output node. The slicer further includes a second latch connected to the first and second output nodes and to a third output node.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: November 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tao Wen Chung, Chih-Chang Lin, Tsung-Ching Huang, Derek C. Tao
  • Publication number: 20140312950
    Abstract: A circuit including: an input stage that includes a first input unit into which input data is input and a pair of first output units and is driven by a first power-supply voltage; a pair of first gate elements that includes first transistors, and is driven by a clock that includes a second power-supply voltage that is lower than the first power-supply voltage; a first latch circuit that includes a pair of second input units, and is driven by the first power-supply voltage; a pair of second gate elements that includes second transistors, and is driven by an inverted clock of the clock; and a second latch circuit that includes a pair of third input units, and a third output unit that outputs one of a pair of pieces of data, and is driven by the first power-supply voltage.
    Type: Application
    Filed: March 6, 2014
    Publication date: October 23, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Satoshi TANABE, Kenichi KAWASAKI
  • Publication number: 20140306745
    Abstract: A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, an inversion is enabled from the second node to a third node. An inversion from the third node to the fourth node is provided. After the enabling the inversion from the second node to the third node, the first node is decoupled from the second node. After the enabling the inversion from the second node to the third node, the second node is coupled to the third node. An inversion from the fourth node to the third node is enabled and the second node is decoupled from the fourth node.
    Type: Application
    Filed: June 26, 2014
    Publication date: October 16, 2014
    Applicant: FREESCALE SEMICONDUCTOR INC.
    Inventors: RAVINDRARAJ RAMARAJU, Prashant U. Kenkare
  • Publication number: 20140306744
    Abstract: Signal value storage circuitry 2 is provided which includes a first transistor stack, a second transistor stack and a third transistor stack. The signal value storage circuitry is controlled by a single clock signal. Keeper transistors and isolation transistors serve to permit static operation of the signal value storage circuitry (i.e. the clock signal may be stopped without losing state) and to prevent contention within the circuitry.
    Type: Application
    Filed: April 11, 2013
    Publication date: October 16, 2014
    Inventor: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
  • Patent number: 8860484
    Abstract: Embodiments of a logic path are disclosed that may allow for a reduction in switching power. The logic path may include a storage circuit, a comparison circuit, and a clock gating circuit. The storage circuit may be configured to store received data responsive to a local clock signal. The comparison circuit may be operable to compare the received data to data previously stored in the storage circuit. The clock gating circuit may be configured to generate the local clock signal dependent on a global clock signal, and de-activate the local clock signal dependent upon the results of the comparison performed by the comparison circuit.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 14, 2014
    Assignee: Oracle International Corporation
    Inventors: Ha M Pham, Jin-uk Shin
  • Publication number: 20140253197
    Abstract: A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention register and reducing power to a volatile stage of the retention register. The non-volatile stage may be powered by an external voltage source. The volatile stage may be powered by an internal voltage source.
    Type: Application
    Filed: March 6, 2013
    Publication date: September 11, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Ramaprasath Vilangudipitchai, Prayag Bhanubhai Patel
  • Patent number: 8829965
    Abstract: A system and method to perform scan testing using a pulse latch with a blocking gate is disclosed. In a particular embodiment, a scan latch includes a pulse latch operable to receive data while a pulse clock signal has a first logical clock value and a blocking gate coupled to an output of the pulse latch. The blocking gate is operable to propagate the data from the output of the pulse latch while the pulse clock signal has a second logical clock value.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: September 9, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Venkatasubramanian Narayanan, Kashyap R. Bellur
  • Patent number: 8816741
    Abstract: A state retention power gated (SRPG) cell includes an input control circuit having an input coupled to an input signal and an output. The input control circuit includes has transistors configured as a first inverter transmission gate. The transistors also connect in series at least one transistor controlled by a power gating signal. A first latch has an input coupled to the output of the input control circuit and an output. A transmission gate has an input coupled to the output of the first latch and an output that is an output of the SRPG cell. A second latch has an input coupled to the output of the transmission gate and an output that also is an output of the SRPG cell. A second inverter transmission gate has an input coupled to the output of the second latch.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: August 26, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yifeng Liu, Zhe Chen, Shayang Zhang, Jian Zhou
  • Publication number: 20140218081
    Abstract: A semiconductor device includes a latch circuit. The latch circuit includes a sampling section that latches a differential input signal applied from a differential input node to the gates of a differential pair of transistors, a common adjusting section that adjusts a common potential of the differential input signal by adjusting based on a current control signal the amount of current that is drawn from the differential input node, and a common control section that controls the current control signal so that the differential pair of transistors operate in a saturated region, and supplies the controlled current control signal to the common adjusting section.
    Type: Application
    Filed: April 3, 2014
    Publication date: August 7, 2014
    Applicant: PANASONIC CORPORATION
    Inventor: Akinori SHINMYO
  • Patent number: 8797077
    Abstract: A master-slave flip-flop circuit includes: a master circuit to receive input data in a first state of a reference clock and hold the input data in a second state of the reference clock to output intermediary data; and a slave circuit to receive the intermediary data in the second state and hold the intermediary data in the first state to output data, wherein the master circuit includes: a feedback two-input NOR gate to receive an output of the master circuit and a first clock; an input three-input NOR gate to receive the input data, a second clock, and a third clock; and a synthesis two-input NOR gate to receive an output of the input three-input NOR gate and an output of the feedback two-input NOR gate.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: August 5, 2014
    Assignee: Fujitsu Limited
    Inventor: Ryuhei Sasagawa
  • Patent number: 8786344
    Abstract: A storage cell having a pulse generator and a storage element is proposed. The storage element input is connected to receive a data input signal. The storage element output is connected to provide a data output signal. The storage element is operable in one of a data retention state and a data transfer state in response to a storage control signal received from the pulse generator. The pulse generator is connected to receive a clock signal with rising and falling clock signal edges and is adapted to provide control pulses in the storage control signal. Each control pulse has a leading edge and a trailing edge. The control pulses have a polarity suited to invoke the data transfer state on their leading edges. The novel feature is that the pulse generator is adapted to initiate a rising-edge control pulse when receiving a rising clock signal edge and to initiate a falling-edge control pulse when receiving a falling clock signal edge.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: July 22, 2014
    Assignee: Oticon A/S
    Inventor: Jakob Salling
  • Patent number: 8786345
    Abstract: One embodiment of the present invention sets forth a technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations, The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant, The output signal Q is set or reset at the rising clock edge using a single- trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: July 22, 2014
    Assignee: NVIDIA Corporation
    Inventors: Jonah M. Alben, William J. Dally
  • Patent number: 8760208
    Abstract: An apparatus may include a storage circuit that may have a first terminal and a second terminal and may have two cross-coupled inverters. The apparatus may include a feedback circuit coupled to the first terminal. The feedback circuit may include electronic logic elements to determine if the storage circuit is in a metastable state. The feedback circuit may couple at least one of the first and second terminals to one of a voltage reference and a voltage source if determined that the storage circuit is in a metastable state.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: June 24, 2014
    Assignee: Intel Corporation
    Inventors: Charles E. Dike, Mark E. Schuelein
  • Patent number: 8742804
    Abstract: A semiconductor device with low power consumption and a small area is provided. By using a transistor including an oxide semiconductor for a channel as a transistor included in a flip-flop circuit, a divider circuit in which the number of transistors is small, power consumption is low, and the area is small can be achieved. By using the divider circuit, a semiconductor device which operates stably and is highly reliable can be provided.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Fujita, Yukio Maehashi
  • Patent number: 8736334
    Abstract: A current mode logic latch may include a first hold stage transistor coupled at its drain terminal to the drain terminal of a first sample stage transistor. A second hold stage transistor is coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. A first hold stage current source is coupled to a source terminal of the first hold stage transistor. A second hold stage current source is coupled to a source terminal of the second hold stage transistor. The hold stage switch is coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: May 27, 2014
    Assignee: Fujitsu Limited
    Inventors: Shuo-Chun Kao, Nikola Nedovic
  • Patent number: 8730404
    Abstract: In an embodiment, the present invention includes a latch circuit having a first input to receive a data signal and a second input to receive a clock signal. This latch circuit may have a first pair of transistors including a first transistor gated by the data signal and a second transistor gated by an inverted data signal and a second pair of transistors including third and fourth transistors gated by the clock signal. The first transistor may be coupled to the third transistor at a first inter-latch node and the second transistor coupled to the fourth transistor at a second inter-latch node. A reset circuit may be coupled to the latch circuit to maintain the first and second inter-latch nodes at a predetermined voltage level when the clock signal is inactive.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: May 20, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Clayton Daigle, Abdulkerim L. Coban
  • Patent number: 8717079
    Abstract: The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: May 6, 2014
    Assignee: Mediatek Inc.
    Inventors: Cheng-Hsing Chien, Yung-Chieh Yu, Jia-Yi Xu
  • Publication number: 20140118046
    Abstract: A state retention power gated (SRPG) cell includes an input control circuit having an input coupled to an input signal and an output. The input control circuit includes has transistors configured as a first inverter transmission gate. The transistors also connect in series at least one transistor controlled by a power gating signal. A first latch has an input coupled to the output of the input control circuit and an output. A transmission gate has an input coupled to the output of the first latch and an output that is an output of the SRPG cell. A second latch has an input coupled to the output of the transmission gate and an output that also is an output of the SRPG cell. A second inverter transmission gate has an input coupled to the output of the second latch.
    Type: Application
    Filed: August 13, 2013
    Publication date: May 1, 2014
    Inventors: Yifeng Liu, Zhe Chen, Shayang Zhang, Jian Yuan
  • Patent number: 8653876
    Abstract: The present invention provides a clamp circuit including, a switching section including first and second switching elements connected parallel between a current supply source and a clamp capacitor; a first control section that controls the first switching element to connect the current supply source and the clamp capacitor, when the voltage of an input signal input through the clamp capacitor is lower than a first reference voltage; and a second control section that stores voltage information based on the input signal when the voltage of the input signal is lower than a second reference voltage, and that controls the second switching element to connect the current supply source and the clamp capacitor for a period predetermined based on the voltage information, when the input signal is equal to or higher than the first reference voltage.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: February 18, 2014
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Takatsugu Kai
  • Publication number: 20140035645
    Abstract: A system and method to perform scan testing using a pulse latch with a blocking gate is disclosed. In a particular embodiment, a scan latch includes a pulse latch operable to receive data while a pulse clock signal has a first logical clock value and a blocking gate coupled to an output of the pulse latch. The blocking gate is operable to propagate the data from the output of the pulse latch while the pulse clock signal has a second logical clock value.
    Type: Application
    Filed: August 1, 2012
    Publication date: February 6, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Venkatasubramanian Narayanan, Kashyap R. Bellur
  • Patent number: 8643422
    Abstract: This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: February 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tao Wen Chung, Chih-Chang Lin, Tsung-Ching Huang, Derek C. Tao
  • Patent number: 8624632
    Abstract: Sense amplifier-type latch circuits are provided which employ static bias currents for enhancing operating frequency. For example, a sense amplifier-type latch circuit includes a latch circuit that captures and stores data during an evaluation phase of the sense amplifier-type latch circuit, and outputs the stored data to differential output nodes. An input differential transistor pair has drains connected to the latch circuit and sources commonly connected to a coupled source node. A static bias current circuit is connected to the coupled source node to provide a static bias current which flows through the differential transistor pair and cross-coupled inverters of the latch during a precharge phase. A switch device, which is connected to the coupled source node, is turned off during the precharge phase and turned on during the evaluation phase by operation of a clock signal to increase current flow through the differential transistor pair.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventor: John F. Bulzacchelli
  • Patent number: 8604855
    Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: December 10, 2013
    Assignee: NVIDIA Corporation
    Inventors: William J. Dally, Jonah M. Alben, John W. Poulton, Ge Yang
  • Patent number: 8593192
    Abstract: A semiconductor integrated circuit includes a first retention flip-flop configured in a first type in which a retention flip-flop is able to retain data based on one of a low-level clock signal and a high-level clock signal, and unable to retain data based on another one of the low-level clock signal and high-level clock signal, and a second retention flip-flop configured in a second type in which a retention flip-flop is able to retain data based on the low-level clock signal and also able to retain data based on the high-level clock signal.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: November 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Yasuhiro Oda