Abstract: A clock circuit with delay functions includes a first clock tree and a delay module. The first clock tree provides a first clock signal and includes a first clock root and a plurality of first sub-trees. The delay module is coupled to the first clock root or a designated sub-tree among the plurality of first sub-trees for delaying the first clock signal. The delay module includes at least two delay segments, wherein each delay segment includes a delay and a connection net. The delay time caused by each delay segment is substantially the same.

Abstract: Provided is a signal generating apparatus that generates an output signal having a designated phase, comprising a phase difference detecting section that outputs a control signal corresponding to a phase difference between a reference signal having a prescribed period and the output signal; an oscillating section that generates a periodic signal having a frequency corresponding to the control signal; and a phase shifting section that outputs the output signal to have a phase that is shifted from the phase of the periodic signal by a designated phase amount.

Abstract: A technique includes providing transmitters that are each associated with a data bit line of a bus, and each transmitter is clocked by an associated transmit clock signal. The technique includes determining a baseline offset to apply to a base clock signal to synchronize the base clock signal to a source clock signal of a source that supplies data to the transmitters. For each transmitter, an associated phase offset is determined to compensate for an associated skew. The phase of each transmit clock signal is controlled based on the associated phase offset and the baseline offset.

Abstract: A phase shifter according to an embodiment of the present invention includes: an AC component amplifying unit; and a dividing circuit. The AC component amplifying unit has positive gain slope characteristics and deforms a waveform of an input differential clock signal to output the deformed differential clock signal. The dividing circuit includes a T-flipflop having two D latches connected in series and receives the deformed differential clock signal defoemed by the AC component amplifying unit to generate at least two output signals having a phase difference of 90 degrees with a frequency of ½ of the deformed differential clock signal.

Abstract: A delay circuit includes a first delay module, a delay measurement unit and a fault judge unit. The first delay module has a first delay circuit with at least one delay stage. The delay measurement unit is used for measuring a first delay amount and a second delay amount of the first delay chain respectively corresponding to a first number and a second number of delay stages. The fault judge unit is used for determining if the first delay chain has delay faults or not according to the first and second delay amounts.

Abstract: In one embodiment, the present invention includes an electronic circuit comprising a first stage having a first differential inductive element and a second differential inductive element, and a second stage coupled to an output of the first stage, the second stage having a first differential inductive element and a second differential inductive element, wherein the first and second differential inductive elements of the first stage couple magnetically to generate a first phase error, wherein the first and second differential inductive elements of the second stage couple magnetically to generate a second phase error, and wherein the second phase error cancels the first phase error.

Abstract: A multi-phase correction circuit adjusts the phase relationship among multiple clock signals such that their rising edges are equidistant in time from one another.

Abstract: One aspect relates to a clock signal synchronizing device, in particular to a delayed locked loop (DLL) with capability to correct static duty-cycle offset and to filter clock-jitter. One aspect relates to a clock signal synchronizing method with capability to correct static duty-cycle offset and to filter clock-jitter. In accordance one aspect, there is provided a clock signal synchronizing device including a delay circuit having a variable delay time and delaying an incoming clock signal or a signal generated therefrom to output a delayed clock signal. Also included is a negator for inverting the delayed clock signal to output an inverted delayed clock signal. Also included is a delay control circuit for controlling the delay circuit to adjust the phase relation between the incoming clock signal and the inverted delayed clock signal and a phase interpolator.

Abstract: An AC-coupling phase interpolator and a DLL using the same are provided. The AC-coupling phase interpolator includes a coupling capacitor generating and outputting a coupling signal by AC-coupling to an interpolation signal obtained by phase-interpolating an input signal. Thereby, it is possible to correct duty of an input signal and adjust the level of an output signal.

Abstract: A method of processing a signal is disclosed. The present invention includes receiving (a) downmix signal being generated from plural-channel signal and (b) spatial information indicating attribute of the plural-channel signal in order to upmix the downmix signal and including phase shift flag indicating whether phase of a frame of at least one channel of the plural-channel signal is shifted; obtaining inter-channel phase difference (IPD) coding flag indicating whether IPD value is used to the spatial information from a header of the spatial information; obtaining IPD mode flag indicating whether the IPD value is used to frame of the spatial information from the frame based on the IPD coding flag; obtaining the IPD value of parameter band in the frame, based on the IPD mode flag; upmixing plural-channel signal by applying the IPD value to the downmix signal; and shifting the phase of the frame of the at least one channel of the plural-channel signal based on the phase shift flag.

Abstract: A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.

Abstract: Eight or more transition points are generated during a given period, and are used in tracking movement of an interferometer reflector. Duty cycles of generated square waves are used to establish precise intervals between the transition points, and precise wave-phase relationships.

Abstract: The present invention relates to an electronic transmitter for serially transmitting bit sequences. The electronic transmitter includes a detection device 10 and a transmitting device 12. The detection device 10 is adapted to detect a predefined bit sequence for transmittal. The predefined bit sequence is susceptible to inter-symbol-interference. The transmitting device 12 is adapted to transmit serially the detected predefined bit sequence in such a way, that a duration for transmittal of a particular bit in said predefined bit sequence is longer than a duration of transmittal of remaining bits in said predefined bit sequence.

Abstract: Various embodiments provide a Phase Interpolator (PI) that receives input clocks, and outputs intersymbol interference-equalized, phase-shifted output clocks. In one embodiment, the Phase Interpolator comprises two PI Conditioners and a PI Mixer. In one embodiment, a PI Conditioner receives input clocks and is controlled by a different phase-shifted input clock by using a suitable circuit element, such as a flip-flop. Collectively, the input clock-controlled PI Conditioner and Mixer act in concert to control the band limiting effect of the PI Conditioner which, in turn, equalizes intersymbol interference.

Abstract: A phase interpolator includes a first circuit to generate a first signal having a first phase delay and a second signal having a second phase delay and a phase mixer. The phase mixer is coupled to receive the first and second signals from the first circuit. The phase mixer includes multiple current drivers each including a current driver input coupled to selectively delay one of the first or second signals and a current driver output coupled to output a phase delayed signal. The current driver outputs of the current drivers are coupled together to combine the phase delayed signals from the current drivers to generate an output phase delayed signal having a phase interpolated from the first and second signals.

Abstract: The present invention provides a phase shifter comprising a first multiplier unit that outputs a first output signal obtained by multiplying an input signal input thereto by a multiplication value calculated based upon a first digital control signal also input thereto and specifying a phase shift quantity for the input signal, a second multiplier unit that outputs a second output signal obtained by multiplying an orthogonal input signal input thereto and having a phase perpendicular to the phase of the input signal by a multiplication value calculated based upon a second digital control signal also input thereto and specifying the phase shift quantity, and an adder/subtractor unit that executes addition or subtraction by using the first output signal and the second output signal based upon a third digital control signal corresponding to the phase shift quantity.

Abstract: A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.

Abstract: A delay device for adjusting phase under a SMIA (Standard Mobile Imaging Architecture) standard is provided. More particularly, the delay device is used to adjust a phase of a clock signal, which carries data, under the SMIA standard. The delay device includes plural delay cells, which are disposed on a circuit board by means of APR (Automated Placement and Routing) method, and one or more delay multiplexers (MUX) connected with the delay cells. Through selective pins controlling the route selection in the delay multiplexer, the delay device can produce plural delay times to adjust the phase relationship between data and clock, as supposed to using PLL.

Abstract: A phase interpolation circuit and method are provided that are capable of operating in a low voltage and capable of generating a substantially exact phase-interpolation signal, where the phase interpolation circuit is configured to output a phase interpolation signal having a phase between phases of at least two input signals and comprises an interpolation unit configured to discharge an output node by a first interpolation control signal in case a first input signal of two input signals having different phases is inputted to the interpolation unit when the output node has been precharged to a power supply voltage level, the interpolation unit additionally discharging the output node by a second interpolation control signal in case of input of a second input signal of the two input signals; a comparison unit for comparing a reference voltage level and a voltage level of the output node of the interpolation unit to output a signal corresponding to the comparison; and a short pulse generation unit for generatin

Abstract: A method, circuit, and system are disclosed. In one embodiment, the method comprises receiving a differential clock signal from two clock signal lines into a first differential pair of transistors of a first size, receiving the differential clock signal from the two clock signal lines into a second differential pair of transistors of a size smaller than the first size, converting the differential clock signal into a single-ended clock signal, outputting the single-ended clock signal through an inverter, and synchronizing any differential clock phase error by controlling the transconductance between the first differential pair of transistors and the second differential pair of transistors.

Abstract: A method of phase angle control including the steps of generating a first periodic function having a first amplitude and generating a second periodic function having a second amplitude, which second periodic function is phase shifted relative to the first periodic function by a first phase angle. The method further includes generating a first positive feedback periodic function and generating a second positive feedback periodic function which is phase shifted relative to the first positive feedback periodic function by a second phase angle. In addition, the method includes generating a first control function, a first weighting function, a second weighting function, and linearly combining the product of the first positive feedback periodic function and the first weighting function with the product of the second positive feedback periodic function and the second weighting function to generate a second control function.

Abstract: A phase shift circuit includes a 45° phase corrector that performs vector synthesis of signals supposed to have a 45° phase difference, out of a plurality of sets of orthogonal phase signals having an about 45° phase difference and an equal amplitude, the orthogonal phase signals in each set having undergone 90° phase correction, and outputs signals resulting from the vector synthesis, whereby a phase error between the orthogonal phase signals in the different sets is eliminated by the vector synthesis to make it possible to correct their phase difference to accurately 45°.

Abstract: Eight or more transition points are generated during a given period, and are used in tracking movement of an interferometer reflector. Duty cycles of generated square waves are used to establish precise intervals between the transition points, and precise wave-phase relationships.

Abstract: A memory module having an array of memory devices, mounted thereon, that operate synchronously with a clock signal, wherein provisions are made to be able to fine-tune the clock phase in accordance with its use conditions. The memory module, having an array of memory devices mounted thereon that operate synchronously with the clock signal, includes; a phase-locked loop circuit which produces an output clock signal adjusted so that the phase of a feedback signal obtained by passing the output clock signal through a feedback loop matches the phase of an input clock signal; and a switching unit which selectively changes a load in the feedback loop in accordance with an external signal.

Abstract: The apparatus measures timing variations, such as the jitter or wander in a timing signal (100) of a telecommunications network. A recovered clock signal is sampled and digitized to produce a series of digital clock samples which are then processed (135) with reference to a local digital reference signal to produce digital baseband frequency in-phase (I) and quadrature (Q) components (165, 170) these being further processed (145) to produce the digital phase information of said clock signal to determine (175) the required parameters of the network. The step of digitally processing said clock samples with reference to a local reference signal can be conveniently and cheaply implemented using a digital signal down-converter IC (135), for example of a type existing for digital radio receiver implementations. For jitter measurement, the local reference signal may be generated by a phase-locked loop (as in FIG. 2). For wander measurements an external reference clock is used (as in FIG. 3).

Abstract: Provided is a multi-phase clock generator which is not influenced by a mismatch and of which a maximum frequency is not limited. The multi-phase clock generator includes a first delay line, a second delay line, a phase detector, and an up/down counter. The first delay line generates a first clock signal by delaying an input clock for a first delay time. The second delay line generates a second clock signal by delaying the input clock for a second delay time in response to a control signal. The phase detector detects a phase difference between the first and second clock signals. The up/down counter generates the control signal in response to an output of the phase detector.

Abstract: By forming adjacent wiring 4 adjacent to signal wiring 3 and using a control circuit 13 comprising a 2-input NAND 20 circuit or the like to input a signal S4 corresponding to a signal S3 in the signal wiring 3 to the adjacent wiring 4, it is made possible to change the delay of the signal S3 in the signal wiring 3 in several picoseconds, by using crosstalk with the signal S4 in the signal wiring 4.The inventive delay control circuit device can be provided by simply adding adjacent wiring 4 and a control circuit 13 to signal wiring 3. This implements a delay control circuit device for semiconductor integrated circuits that is capable of controlling a signal delay in several picoseconds without increasing the circuit scale.

Abstract: There is provided a shift clock generator for phase-shifting a shift clock by inserting insertion pulses into the shift clock, wherein an insertion pulse generating section has a compensation memory for storing compensation data for calculating a number of insertion pulses to be inserted into the shift clock with respect to a phase difference preset value based on a phase shift amount, a number-of-pulses calculating section for integrating the compensation data stored in an address range of the compensation memory to calculate a number-of-insertion pulses data based on the phase difference preset value and a pulse generating section for generating the insertion pulses based on the number-of-insertion pulses data.

Abstract: A method and apparatus are disclosed for dynamically reducing clock skew among various nodes on an integrated circuit. The disclosed clock skew reduction technique dynamically estimates the clock delay to each node and inserts a corresponding delay for each node such that the clock signals arriving at each node are all in phase with a global clock (or 180° out of phase). Delays attributable to both the wire RC delays and the clock buffer delays are addressed. A feedback path for the clock signal associated with each node allows the round trip travel time of the clock signal to be estimated. When the length of the feedback path matches the length of the primary clock path, the clock skew present at the corresponding node can be estimated as fifty percent (50%) of the round trip delay time. Dynamic adjustments to the delay control circuit are permitted as operating conditions shift.

Abstract: In a clock phase corrector appropriately correcting the phase of a data sampling clock signal, a series of shift registers responds to respective sampling clock signals to store received data sequentially. The stored data are duplicated by a comparator register in response to corresponding clock signals to output a demodulated signal. A corrector shift register is provided to store sampled data in response to a clock signal. The data thus stored are then held in a reception register as intended reception data. A comparator compares the demodulated signal with the intended reception data. Based upon a result from the comparison, a bit adder produces the number of inconsistent bits. Another comparator compares the number of inconsistent bits with the number of error acceptance bits stored in an error acceptance memory to generate a phase detection signal, in response to which a timing control adjusts the phase of a data sampling clock signal.

Abstract: A delay circuit includes a phase vernier having a plurality of logic components. Each logic component includes a selectable injection input capable of adjusting a phase of an input to the phase vernier.

Abstract: A multi-phase clock signal generator provides multiple clock signals from an input clock signal, the multiple clock signals being inverted from one another and having substantially the same delay and duty cycle characteristics. Methods of generating multiple clock signals are also provided.

Abstract: Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers have a smaller phase difference, thereby providing finer delay adjustments. Multiple stages of phase mixers can be provided in digital delay-locked loop circuitry to provide additional hierarchical delay adjustment.

Abstract: An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores a value that represents a timing offset to adjust the time at which the data is sampled. The clock circuit generates the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal. The clock circuit includes an interpolator that phase mixes a set of reference clock signals such that the internal clock signal is phase offset in accordance with the value.

Abstract: Techniques for dynamically shifting the phase of clock signals are provided. A circuit generates a plurality of periodic clock signals. Each clock signal has the same period, the same duty cycle, and a different phase. The clock signals are provided to the inputs of two multiplexers. The output signals of the multiplexers are transmitted to a phase selection circuit that generations phase selection signals. The multiplexers each select one of the clock signals in response to the phase selection signals. When the phase selection signals change value, each multiplexer selects a different clock signal in order to shift the phase of its output signal forward or backward by an incremental value. A directional signal determines whether the multiplexers shift the phases of their output signals forward or backward in time.

Abstract: The invention is related to analog to digital conversion of a multi-level analog signal at a very low sampling rate. The analog signal is sampled by a recovered clock to produce a succession of samples of the analog signal. The low sampling rate may be within an order of magnitude of the symbol rate of the analog signal. Each sample is converted to a digital word. A phase detector reference circuit determines from peak values of the analog signal at least two allowable levels of the analog signal including a reference-crossing level. The phase detector defines a zero band of amplitude ranges of the analog signal including the reference-crossing level. It further defines an error band of amplitude ranges of the analog signal extending from said zero band to a fraction of the amplitude of the next allowable level. The phase detector then infers either a positive or negative phase error for each pair of successive samples of the analog signal.

Abstract: Clocking scheme to clock a monolithic integrated circuit, having a basic clock rate (c0) generated by a clock source which is coupled to N intermediate clocks (c1 through cN) which are delayed relative to each other, wherein the individual delays (t) are distributed within a period T of the basic clock rate. Each of the N intermediate clocks (c1 through cN) supplies at least one of M data-processing blocks (D1 through DM). To effect a transfer of data between a transmitting data-processing block (D2) and a receiving data-processing block (D1), the delay of the intermediate clock assigned to the intermediate clock (c2) is greater than the delay of the intermediate clock (c1) assigned to the receiving data-processing block.

Abstract: Circuits and methods are provided that reduce, if not prevent, the adverse effects of transient noise on phase adjustments made by digital delay lock loop (DLL) circuits, which typically generate a periodic output signal having a particular phase relationship with a periodic input signal. A digital low pass filter of a DLL circuit includes circuitry, such as, for example, a thermometer register, coupled to receive the outputs of a DLL phase detector. The low pass filter prevents the DLL circuit from making frequent changes to the phase of the DLL output signal.

Abstract: A bi-directional input/output (IO) cell for transmitting and receiving data signals simultaneously over a single line. The bidirectional IO cell having an IO node adapted to connect to the line. A driver has an output connected to the line and an input for receiving a core output signal. A first differential amplifier has a first input connected to the IO node and a second input connected to a high voltage reference circuit. A second differential amplifier has a first input connected to the IO node and a second input connected to a low voltage reference circuit.

Abstract: A switched coupler type digital phase shifter using a quadrature generator is disclosed. A switched coupler type digital phase shifter includes: a coupling unit for receiving one input signal and generating a first signal and a second signal having 180 degree phase difference based on the received input signal; a quadrature signal generation unit for generating a third signal to a sixth signal having 90 degree phase difference to each other based on the first signal and the second signal outputted from the coupling unit; and a switching unit for selectively outputting one of the third signal to the sixth signal outputted from the quadrate signal generation unit in response to a control signal. The present invention can increased integration of the multi-bit digital phase shifter by implementing multi bit phase variant with only one phase shifter. Also, the insertion loss can be minimized.

Abstract: A phase shift circuit and a phase shifter are achieved which are small in size and wide in bandwidth. The phase shift circuit includes a capacitor, and a series circuit composed of a switching element which exhibits capacitivity when it is in an off-state and an inductor connected in series with this switching element, the series circuit being connected in parallel with the capacitor. The capacitor and one terminal of the series circuit are connected with a high frequency signal input/output terminal, and the other terminal thereof is connected with ground.

Abstract: A circuit and method for suppressing the effect of noise on a data strobe signal DQS in a double data rate (DDR) SDRAM is provided. The circuit includes a data input latch circuit for receiving data to be stored and for latching the data in a memory array in response to a control signal; and a control signal generator for generating the control signal in response to a data strobe signal wherein the control signal has a predetermined minimum pulse width of the data strobe signal. The control signal generator includes a reset/set flip-flop for generating the control signal, wherein the flip-flop is set by the data strobe signal; and a low pass filter for receiving the data strobe signal and for outputting a reset signal to the flip-flop if the data strobe signal is greater than the predetermined minimum pulse width.

Abstract: An embodiment of this invention pertains to a digital circuit that shifts the phase of a clock signal. In this embodiment, multiple delay units, e.g., buffers, shift the clock signal multiple times and store a level of the clock signal within corresponding memory devices, e.g., flip-flops when triggered by the phase shifted clock signals. These levels may be at a high level (e.g., the clock signal has the value “1”) or a low level (e.g., the clock signal has the value “0”). A “phase selection table” stores multiple entries, each of the entries includes multiple clock level values. Each of the entries specifies values used to determine when the phase shifted clock signals transition from the high level to the low level. This transition point signifies a 180 degree phase shift. Using this transition point, other phase shifts can be determined.

Abstract: Disclosed is an interpolating circuit for producing an output signal having a delay time corresponding to a value obtained by performing interior division of a phase difference between entered first and second signals by a preset interior division ratio. The interpolating circuit includes a waveform synthesis unit and a bias control unit. The waveform synthesis unit includes an OR gate, which receives the first and second signals, for outputting the logic OR between these two signals; a first switch element inserted between a node, which is connected to an output terminal, and a first power supply and turned on and off by the output signal of the OR gate; a series circuit comprising a first constant-current source and a second switch element turned on and off by the first signal; and a series circuit comprising a second constant-current source and a third switch element turned on and off by the second signal; the series circuits being connected in parallel between the output node and a second power supply.

Abstract: Disclosed is a method and apparatus for converting an unstable receiver enable signal RXEN, which is based on a master clock which undergoes timing adjustments, to a stable receiver enable signal RXEN′ which is based on an externally applied clock signal. An externally applied clock signal at a frequency fc is divided by a factor N to produce N uniformly phase spaced clock signals. A clocking edge of a master clock signal which generates the receiver enable signal RXEN is associated with one of the N clocking signals which has a pulse which substantially envelopes the edge of the master clock signal which generates the RXEN signal. A new receiver enable signal RXEN′ is generated by the associated new clock signal. The receiver enable signal RXEN is therefore converted from a signal which has adjusted timing to RXEN′ which has no timing adjustment.

Abstract: According to a feedback control method, the response process of set point tracking control is divided into three, tracking, convergence, and stabilization phases. The phase is switched to the tracking phase at set point change start time as the tracking phase start time. The manipulated variable which causes the controlled variable to tracking the set point is continuously output in the tracking phase. The phase is switched to the convergence phase at, as the convergence phase start time, specific set point tracking control elapsed time at which the controlled variable does not exceed the set point in the tracking phase. A manipulated variable which converges the controlled variable to the vicinity of the set point is continuously output in the convergence phase. The phase is switched to the stabilization phase at, as the stabilization phase start time, time at which the controlled variable reaches a preset situation in the convergence phase.

Abstract: An oscillator generates an oscillation signal, and a phase shifter outputs a phase shift oscillation signal corresponding to a difference between a frequency of the oscillation signal and a target frequency. A multiplier outputs a multiplied signal corresponding to a multiplied value of the phase shift signal and the oscillation signal, and an error signal generator outputs an error signal according to the multiplied signal. The output frequency of the oscillator is controlled according to the error signal.

Abstract: A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.

Abstract: A device for controlling a clock signal phase to reduce the clock skew is disclosed. The device includes a clock signal generator disposed in a chip for generating the clock signal, a pad circuit disposed in the chip, electrically connected between the clock signal generator and an external circuit, and including an output buffer and an input buffer, wherein the output buffer transmits the clock signal to both of the external circuit and the input buffer, and the input buffer further transmits the clock signal to a logic circuit module of the chip, and a phase adjustment device disposed in the chip and electrically connected between an output end of the input buffer and the logic circuit module of the chip for adjusting the clock signal required for the operation of the logic circuit module.

Abstract: A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.