Abstract: A host interface includes; a phase shift detector, a phases shifter, and control logic controlling operation of the phase shift detector and the phase shifter. The host interface sends a command and a clock to a device, receives a response from the device, communicates data to the device synchronously with the clock, and samples data received from the device synchronously with a modulated clock. The phase shift detector provides a shift value based on the response, and the phase shifter modulates a phase of the clock based on the shift value to generate the modulated clock.

Abstract: A buffer circuit, a frequency dividing circuit, and a communications device are disclosed. The buffer circuit includes a buffer, a first control circuit, and a second control circuit. The buffer is coupled to a frequency divider, and the buffer is configured to receive a first signal output by the frequency divider, and output a fourth signal by using an output terminal of the buffer circuit when driven by the first signal, where the first signal is obtained by the frequency divider by performing frequency division on a group of differential signals, and the differential signals include a second signal and a third signal. The first control circuit is configured to perform delay control on a rising edge of the fourth signal based on the second signal. The second control circuit is configured to perform delay control on a falling edge of the fourth signal based on the third signal.

Abstract: A system for data and clock recovery includes a timing error detector, a phase detector, and a phase increment injector. The phase increment injector may be used to determine an increment to affect an output of the phase detector or a clocking element. A sign of the increment is determined from a sign or direction of an accumulated version of a clock and data recovery gradient value.

Abstract: A delay locked loop includes a main delay circuit including a plurality of unit delay lines that generate a plurality of internal clocks by delaying an input clock, delay amounts of the plurality of unit delay lines being adjusted in response to code signals; a sub-delay circuit including a plurality of sub-delay lines that generate a plurality of phase clocks by respectively delaying the input clock and the plurality of internal clocks; a phase detector configured to compare phases of the plurality of phase clocks and provide a phase detection signal according to a result of the comparison; and a digital circuit configured to update the code signals corresponding to the plurality of unit delay lines one by one at a time when the phase detection signal is provided to the digital circuit.

Abstract: According to one embodiment, in a semiconductor integrated circuit, a variable delay circuit is electrically connected to the correction circuit and configured to change a delay amount of the second clock. An adjustment circuit is electrically connected to a summer circuit. The adjustment circuit is configured to perform sampling of values in a plurality of edge periods and values in a plurality of data periods of data output from the summer circuit, and adjust a delay amount of the variable delay circuit such that timing of the second clock supplied from the variable delay circuit to the correction circuit becomes close to target timing according to a plurality of sampling results.

Abstract: A dynamic tap weight generator circuit includes a clock generator circuit having a first output and a second output. There is a current interpolator circuit coupled to a first current source and a second current source and to the first and second outputs of the clock generator circuit and operative to provide a first output and a second output providing a differential output current between a current of the first current source and a current of the second current source across a symbol transmission interval. A 2:1 current multiplexer is coupled to a first and second outputs of the current interpolator circuit. A tap weight driver is coupled to an output of the 2:1 current multiplexer and configured is to dynamically adjust a tap weight of an equalizer dynamically during each clock cycle of the clock generator.

Abstract: A time-to-digital converter includes a delay unit into which a first signal is input and a sampling unit into which a second signal is input. The delay unit includes a first delay chain, a second delay chain, and a third delay chain that are connected in series in sequence. The delay unit delays the first signal. The first delay chain includes at least one first delayer. The second delay chain includes at least three second delayers. The third delay chain includes a third delayer. The delay duration of the first delayer and the delay duration of the third delayer are greater than delay duration of the second delayer. The sampling unit samples output signals of first delayers in the first delay chain, second delayers in the second delay chain, and third delayers in the third delay chain at a preset time point of the second signal.

Abstract: Various embodiments provide for determining a delay of a data signal with respect to a data strobe signal within a memory system comprising a memory controller and a memory module. In particular, some embodiments adjust a phase between a data signal and a data strobe signal such that a data eye of the data signal arrives at a receiver latch of a memory module can be centered on a transition of the data strobe signal. By centering the data eye of the data signal with the transition of the data strobe signal, various embodiments can ensure that the data strobe signal transition falls between the leading and trailing edges of the data eye, which in turn permits the memory module to obtain correct data from the memory controller during a write operation.

Abstract: A delay line circuit includes a plurality of delay units configured to receive an input signal and to provide a first output signal. The plurality of delay units is configured to selectively invert or relay the input signal to produce the first output signal based on a first instruction received from a delay line controller. A phase interpolator unit includes an offset unit configured to selectively add a speed control unit in the phase interpolator unit based on a second instruction received from the delay line controller. The phase interpolator unit is further configured to receive the first output signal and provide a second output signal.

Abstract: Embodiments are disclosed that relate to multi-phase clock generators and data samplers for use in high speed I/O circuitry. One disclosed example provides a multi-phase clock generator including a delay line having a plurality of delay elements, the delay line being configured to receive an input clock signal and output a plurality of output clock signals having different phases compared to a phase of the input clock signal. The multi-phase clock generator further includes a control circuit configured to control the delay line based at least in part upon rising edges and falling edges of one or more output clock signals output at one or more locations along the delay line.

Abstract: A radar data processing system is disclosed. The system includes a microcontroller and a data receiver-transmitter integrated circuit coupled to the microcontroller. The data receiver-transmitter integrated circuit includes a sensor and a dedicated error indicator pin. The data receiver-transmitter integrated circuit includes an inner safety monitor and the microcontroller includes an outer safety monitor. The inner safety monitor configured to receive and collate sensor data from the plurality of sensors and send, through the dedicated error indicator pin, a function warning signal to the outer safety monitor when the sensor data from the sensor is indicative of a functional irregularity.

Abstract: A method of operating a system on chip (SoC), an integrated circuit including the SoC, and a system including the same are provided. The method includes: delaying a data strobe signal; obtaining a setup margin and a hold margin by adjusting a delay of the delayed data strobe signal; and determining a data valid window using the obtained setup margin and the obtained hold margin.

Abstract: An apparatus relates generally to clock and data recovery. A fractional-N phase-locked loop is for receiving a reference signal, and for providing a proportional signal and an integral signal. A ring oscillator of the fractional-N phase-locked loop is for receiving the proportional signal and the integral signal, and for providing an oscillation signal at a clock frequency substantially greater than a reference frequency of the reference signal. A data-to-frequency control word converter is for receiving data input and the oscillation signal, and for providing a frequency control word. A fractional-N divider of the fractional-N phase-locked loop is for receiving the frequency control word and the oscillation signal, and for providing a feedback clock signal to a phase-frequency detector of the fractional-N phase-locked loop. The phase-frequency detector is for receiving the reference signal and the feedback clock signal, and for adjusting a phase and frequency of the oscillation signal.

Abstract: Disclosed herein is a device that includes: a plurality of delay circuits each including an input node, an output node, a first power node and a second power node, and a control circuit. The delay circuits are coupled in series with the input node of a leading delay circuit receiving a first clock signal and the output node of a last delay circuit producing a second clock signal. The control circuit coupled to receive the first and second clock signals to control an operating voltage supplied between the first and second power lines. The first power nodes of the delay circuits are connected in common to the first power line, and the second power nodes the delay circuits are connected in common to the second power line.

Abstract: The problem was that the noise superimposed on a touch electrode via the human body can incur erroneous touch determination by a touch sensor circuit. The invention provides a semiconductor device including a terminal to which a touch electrode may be coupled; a source voltage drop circuit generating a constant voltage; a phase shift circuit generating a phase shifted clock in response to a first clock and a phase control signal; and a switching circuit to which the constant voltage is supplied. The switching circuit generates drive pulses for applying the constant voltage to the terminal in response to the phase shifted clock. The phase shift circuit varies the phase of the drive pulses based on the phase control signal.

Abstract: A data output timing control circuit for a semiconductor apparatus includes a phase adjustment unit. The phase adjustment unit is configured to shift a phase of a read command as large as a code value of the delay control code in sequential synchronization with a plurality of delayed clocks obtained by delaying the external clock as large as predetermined delay amounts, respectively, delay the shifted read command as large as the variable delay amount, and output the result of delay as an output enable flag signal.

Abstract: A data output timing control circuit for a semiconductor apparatus includes a phase adjustment unit. The phase adjustment unit is configured to shift a phase of a read command as large as a code value of the delay control code in sequential synchronization with a plurality of delayed clocks obtained by delaying the external clock as large as predetermined delay amounts, respectively, delay the shifted read command as large as the variable delay amount, and output the result of delay as an output enable flag signal.

Abstract: A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators.

Abstract: A circuit device includes a clock generator outputting a clock signal having a first frequency; plural phase controllers inputting the clock signal having the first frequency, and outputting clock signals having the first frequency and having phases advanced or delayed with respect to a phase of the clock signal; a selector inputting the plural clock signals having the first frequency output from the plural phase controllers, sequentially selecting pulses of the plural clock signals, and outputting a clock signal having a second frequency; a pattern generator generating a test pattern based on the clock signal having the second frequency; and a circuit inputting the clock signal having the second frequency and the test pattern generated by the pattern generator, operate based on the clock signal having the second frequency, and outputting operation results.

Abstract: A voltage level shifter formed by single-typed transistors comprises two input terminals, two power supply terminals, a plurality of thin-film transistors, and an output terminal. Another voltage level shifter formed by single-typed transistors comprises two input terminals, an output terminal, two power supply terminals, two input units, a first thin-film transistor, a disable unit, a feedback unit, and a second thin-film transistor. The voltage level shifters are formed by single-typed TFTs. When integrating the voltage level shifters into a substrate of a TFT display, the manufacturing processes are simplified. Besides, power is saved.

Abstract: Disclosed herein is a semiconductor device that includes: a measurement circuit which measures propagation time of an internal clock signal; a delay adjustment circuit which adjusts the propagation time of the internal clock signal on the basis of a result of measurement by the measurement circuit; and a data output circuit which outputs a data signal in synchronization with the internal clock signal.

Abstract: Disclosed are a shift register and a display device which can suppress noise of output of each stage without causing an increase in circuit scale. In at least one example embodiment, each stage of the shift register includes a first output transistor, a second output transistor, a first capacitor, a second capacitor, an input gate, a first switching element, a second switching element, a third switching element, a fourth switching element, and a fifth switching element.

Abstract: An object of the present invention is to provide a level shift IC with a reduced number of input signals over the conventional case. A level shift IC includes an amplitude converting unit including four level shifters; and a different-phase signal generating unit at a stage previous to the amplitude converting unit, including delay circuits. The different-phase signal generating unit generates, by the delay circuits, first and second delayed input signals from first and second input signals of different phases. Therefore, four input signals of different phases are obtained, and the amplitude converting unit increases the amplitudes of the input signals by the amplitude converting unit and thereby generates first to fourth output signals with different phases and increased amplitudes.

Abstract: A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected.

Abstract: In one embodiment of the present invention, a multiple phase pulse generator includes n stages, where each stage includes a first sub-stage and a second sub-stage. The first sub-stage includes a first memory element and the second sub-stage includes a second memory element. The first memory element of each stage is arranged to be set by the preceding stage. The first sub-stage is arranged to supply a stage output pulse while the first memory element is set. The second memory element is arranged to be set by the stage output pulse. The second sub-stage is arranged to hold the first memory element reset after the stage output pulse while the second memory element is set.

Abstract: A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.

Abstract: A timer circuit, comprises a delay indication circuit, a frequency indication circuit, and a plurality of counters. The delay indication circuit is for providing a delay time indication. The frequency indication circuit is for providing a frequency indication of a frequency of a clock signal. Each counter of the plurality of counters includes a load input to receive an initial value, and an indication output to provide a count complete indication of the counter. During operation a set of the counters of the plurality of counters is coupled in series to provide an indication that a delay time has expired. At least a portion of the frequency indication is provided to the load input of one counter of the set and at least a portion of the delay time indication is provided to the load input of another counter of the set.

Abstract: Disclosed is a level shift circuit including a first level shift circuit that is connected between a first power supply terminal and first and second output terminals and receives first and second input signals from the first and second input terminals, respectively, and sets one of the first and second output terminals to a first voltage level, based on the first and second input signals; a second level shift circuit that is connected between a second power supply terminal and the first and second output terminals, and sets the other of the first and second terminals to a second voltage level; and a circuit that performs control to disconnect a current path in the second level shifter between the second power supply terminal and one of the first and second output terminals that is driven to the second voltage level at a time point when the first and second input signals are supplied to the first and second input terminals for a predetermined period including the time point when the first and second input sig

Abstract: A plurality of delay paths are connected in parallel between two synchronous operation circuits operating in synchronism with a clock signal CLK, and enable transmission of a signal. A delay detection unit detects the respective delay times of the plurality of delay paths, and a control unit selects one delay path from among the plurality of delay paths based on the detection results from the delay detection unit, and controls the blocking of signal transmission in the delay paths other than the selected one delay path.

Abstract: A synchronization circuit includes a measurement unit configured to measure a difference between an initial delay amount of an input clock signal and an initial delay amount of a feedback clock signal and generate a phase difference detection signal, an initial delay time setting unit configured to generate an initial delay time setting signal in response to the phase difference detection signal, a shift register configured to generate a shift signal in response to the initial delay time setting signal, and a delay chain having an initial delay time set in response to the shift signal.

Abstract: A method for source synchronous communication. The method includes dynamically adjusting a delay that is applied to a data signal and a remote clock signal until a delayed remote clock signal is synchronized with a local clock signal, and capturing data from a delayed data signal associated with the delay in a local domain.

Abstract: One embodiment provides a host controller which performs a phase shift correction of a sampling clock when sampling a signal received, includes a phase shift judging section which judges whether or not it is necessary to shift a phase of the sampling clock, and up/down counts a counter in accordance with a shift direction when judging that it is necessary to shift the phase, a limit value storage section which stores a variance range limit value of the phase shift, and a shift limit judging section which judges whether or not a value of the counter exceeds the limit value of the phase shift, notifies a host device of an error when judging that the counter value exceeds the limit value, and shifts the phase of the sampling clock in accordance with the counter value of the counter when judging that the counter value does not exceed the limit value.

Abstract: A circuit includes a phase detection circuit and a phase change circuit. The phase detection circuit compares a phase of a first periodic signal to an input signal to generate a gain signal. The phase change circuit provides phase shifts to the first periodic signal in first and second directions when the gain signal has a first value. The phase change circuit increases phase shifts provided to the first periodic signal in the first direction in response to the gain signal changing from the first value to a second value. The phase change circuit provides phase shifts to the first periodic signal in the second direction when the gain signal has the second value that are smaller than the phase shifts provided to the first periodic signal in the first direction when the gain signal has the second value.

Abstract: A display device includes a demultiplexer. The demultiplexer programs time-divided and sequentially input data currents to at least two signal lines. The demultiplexer includes first and second sample/hold circuits for alternately sampling data currents and holding sampled data corresponding to the sampled data, and third and fourth sample/hold circuits for respectively sampling the sampled data held by the first and second sample/hold circuits and programming the current which correspond to the sampled data to the two signal lines.

Abstract: A voltage level shifter formed by single-typed transistors comprises two input terminals, two power supply terminals, a plurality of thin-film transistors, and an output terminal. Another voltage level shifter formed by single-typed transistors comprises two input terminals, an output terminal, two power supply terminals, two input units, a first thin-film transistor, a disable unit, a feedback unit, and a second thin-film transistor. The voltage level shifters are formed by single-typed TFTs. When integrating the voltage level shifters into a substrate of a TFT display, the manufacturing processes are simplified. Besides, power is saved.

Abstract: Clock spreading systems and methods are disclosed. In one embodiment of the invention, a clock spreading system is provided in an integrated transceiver system that comprises a base band control system and a transceiver coupled to the base band control system. The clock spreading system provides a spread clock output signal derived from a clock reference signal for clocking one of the base band control system and the transceiver. The clock spreading system is configured to provide a periodic phase modulated spread clock output signal during receiving of data in a receive mode and a pseudo-random phase modulated spread clock output signal during transmitting of data in a transmit mode.

Abstract: A charge domain filter circuit includes a first signal output portion, at least one second signal output, portion, a third signal output portion, and an adder portion. The first signal output portion outputs a first signal that is sampled at a specified time interval. Each second signal, output portion outputs a second signal that is sampled after a specified delay after the first signal is sampled. Where a plurality of the second signal output portions is included, the second signals are sampled in succession. The third signal output portion outputs a third signal that is sampled after a specified delay after the last second signal is sampled. The adder portion adds the first, second, and third signals together and outputs the result. The capacitance ratio of the sampling capacitors in the first signal output portion and the second signal output portion is one of continuously or discretely varied.

Abstract: Clock signals are supplied, with a phase shift of 1/n cycles between adjacent clock signals. A data acquisition unit acquires serial data at a timing of each of the clock signals. A phase detection unit detects the phase of the transition edge of the serial data using n bits of data. An effective bit number determination unit determines the effective bit number, which is the number of bits to be acquired, based upon the phase of the transition edge of the serial data in the current data-bit acquisition step and the phase of the transition edge of the serial data in the previous data-bit acquisition step. A data-bit output unit outputs the effective bit number of the bits of data acquired at a timing of each clock signal having a predetermined phase relation with the transition edge of the serial data.

Abstract: A register receives an input signal and provides output signals that represent true complementary logic values of the input signal. One implementation of the register includes: a first stage circuit and a second stage circuit. After the output signals are derived, the second stage circuit provides feedback signals to block further propagation of the logic value of the input signal from the first stage circuit to the second stage circuit.

Abstract: Clock spreading systems and methods are disclosed. In one embodiment of the invention, a clock spreading system is provided in an integrated transceiver system that comprises a base band control system and a transceiver coupled to the base band control system. The clock spreading system provides a spread clock output signal derived from a clock reference signal for clocking one of the base band control system and the transceiver. The clock spreading system is configured to provide a periodic phase modulated spread clock output signal during receiving of data in a receive mode and a pseudo-random phase modulated spread clock output signal during transmitting of data in a transmit mode.

Abstract: A multiphase clock circuit in which bit errors are propagated only for the duration of the clock cycle in which a bit error occurs. The circuit recovers automatically from bit errors and is capable of operating at high frequency with high clock precision. The multiphase clock circuit can generate a plurality of clock pulse streams, each pulse stream at the same clock frequency, with fixed phase relationships among the streams. The multiphase clock circuit includes a master clock signal of frequency fc which is applied to a divide by N frequency divider circuit for producing a base clock signal of fc/N. The base clock signal is sequentially applied to the data input of a series chain of N clocked data flip-flops (DFFs) each of which is simultaneously clocked by a clock signal of frequency fc to produce N clock signals of base frequency fc/N separated from each other by a constant time delay T=1/fc.

Abstract: Performing a hash algorithm in a processor architecture to alleviate performance bottlenecks and improve overall algorithm performance. In one embodiment of the invention, the hash algorithm is pipelined within the processor architecture.

Abstract: The present invention provides a shift register which can operate favorably without providing a level shift portion.

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs.

Abstract: The present invention is an electronic device comprising a counter driven by an input clock signal for counting clock cycles and providing a count. A clock signal generating stage provides a first set of phase shifted clock signals having m different phases. The electronic device determines n least significant bits of the count of the counter from the logic states of the first set of m phase shifted clock signals.

Abstract: The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.

Abstract: An interface circuit includes a variable delay circuit and a delay adjustment circuit to automatically detect a data valid window of a DQ signal and adjust an optimum delay amount of a DQS signal, and a fixed delay circuit to delay the DQ signal by a delay amount tFIXDLY satisfying tFIXDLY>tMINDLY+tSKEW?tSETUP where a minimum delay amount in the variable delay circuit is tMINDLY, a skew between the DQ signal and the DQS signal is tSKEW, and a setup time of the DQ signal is tSETUP.

Abstract: A phase interpolator receives an input clock signal and varies the phase of an output clock signal in accordance with a phase control signal.

Abstract: A display device includes a demultiplexer. The demultiplexer programs time-divided and sequentially input data currents to at least two signal lines. The demultiplexer includes first and second sample/hold circuits for alternately sampling data currents and holding sampled data corresponding to the sampled data, and third and fourth sample/hold circuits for respectively sampling the sampled data held by the first and second sample/hold circuits and programming the current which correspond to the sampled data to the two signal lines.

Abstract: When certain digital circuit devices receive data bus signals, I/O interfaces need to sample the data signals during a time when these signals are both valid and stable. Typically, the data signals are sampled at a time corresponding to a point halfway between rising and falling edges of a reference clock signal associated with the data bus, which sampling time corresponds to a 90-degree phase shift of the reference clock signal. In one embodiment of the invention, a delay count generator determines a delay value corresponding to a quarter cycle (i.e., 90 degrees) of the reference clock signal. In making this determination, a counter counts the number of clock cycles of an internally generated, relatively high-frequency clock signal, where the number corresponds to a specified portion (e.g., one half) of a period of a divided-down version of the reference clock signal. That number can then be used to generate the 90-degree delay value.