Abstract: The present invention provides a method and apparatus for updating serial devices. The apparatus includes a plurality of serial registers. The apparatus further includes a device adapted to provide a signal and a plurality of parallel registers, wherein each of the parallel registers is adapted to access at least one of the plurality of serial registers at substantially the same time in response to detecting the signal.

Abstract: Phase shifter circuits and methods use counters to define the positions of the output clock edges. A plurality of counters are each clocked by a count clock relatively much faster than the input clock. A first counter counts for one input clock period, and a delay value is determined based at least in part on the counted value. In some embodiments, the delay value has a maximum value that depends on the counted value. The delay value is provided to a second counter, which counts from zero to the delay value and generates a pulse one delay value after the beginning of the input clock period. A third counter running at the same clock rate generates a pulse after an additional delay. The pulses from the counters are used to provide output clock edges at predetermined times during the input clock cycle. Some circuits also perform a duty cycle correction.

Abstract: A clock generation apparatus includes a first clock generation circuit which generates a clock signal by making state transition in synchronization with a master clock signal after exiting from a predetermined state in response to a timing signal supplied from an exterior of the apparatus, a counter which counts clock pulses of the master clock signal after exiting from a reset state in response to the timing signal, and a reset circuit which resets the counter and sets the first clock generation circuit in the predetermined state in response to the count of the counter reaching a first predetermined value.

Abstract: A system and method in which delay strobe variation in a double data rate device is calibrated by first individually calibrating all slave strobe delay devices at system startup. Thereafter, a master strobe delay device is activated periodically to determine an incremental delay adjustment. This incremental delay adjustment is then used to by the slave strobe delay devices to modify the calibration value performed by the slave strobe delay devices upon startup. In this manner, individual on-die variations are compensated for each slave strobe delay device and variations due to voltage and temperature changes are compensated for without effecting the normal operation of the slave strobe devices.

Abstract: An improved DDLL containing a majority filter counter circuit is disclosed. The majority filter counter circuit is located between the phase detector and the shift register of the DDLL. The majority filter counter circuit receives shifting commands from the phase detector and filters the shift commands from reaching the shift register until a predetermined number (e.g., 16) have been received from the phase detector before transmitting a shift command (either shift right or shift left) to the shift register. Once the shift register receives the shift command, the shift register directs the delay line to shift by one tap in either a shift right or a shift left direction depending upon the phase relationship between CLKIn and CLKOut. By waiting for e.g., 16 shift commands, the majority filter counter circuit ensures that a premature shift command is not delivered to the shift register in the case of a noise event.

Abstract: A system is described for providing pulses to test a semiconductor device, such as a memory device. The system includes several voltage sources, each voltage source being coupled to an output terminal through a pass gate. A control logic circuit provides a control signal to each of the pass gates to render the pass gates conductive in a sequence. A voltage generated by each voltage source is coupled to the output terminal in a sequence to generate a series of pulses at the output terminal. Each of the voltage sources may be a programmable digital-to-analog converter receiving a voltage control signal and generating a voltage based on the voltage control signal.

Abstract: A clock forming unit, a selection processing unit, and a dithering control unit are provided. In the clock forming unit, m-phase clock signals whose phases are mutually deviated by a predetermined amount at a desired frequency are formed. The clock signals formed in the clock forming unit are supplied to the selection processing unit. A control signal is supplied from the dithering control unit to the selection processing unit. In the selection processing unit, by sequentially selecting one of the m-phase clock signals in response to the control signal from the dithering control unit, the phase is fluctuated forward and backward with a predetermined relation within a range of a precision that is permitted by a communication system serving as a supplying destination. A second clock signal in which a peak on a spectrum is spread is obtained from the selection processing unit.

Abstract: A method for determining a digital phase in a signal comprises sampling a reference signal for a low going edge. If the low going edge is not detected the reference signal is sampled again. If low going edge is detected (78) a counter is initialized (70). The reference signal is again sampled if a high going edge is not detected the reference signal is resampled until the high going edge is detected (79). When a high going edge is detected (79) a counter is started (73). A resulting signal is then sampled if the level of the resulting signal is high the resulting signal is sampled until a low going edge is detected (78). If a low going edge is not detected sampling of the resulting signal continues. If a low going edge is detected (78) sampling is continued until a high going edge is detected (79) at which point the counter is stopped (76). The counter updates a register (96).

Abstract: A circuit including a counter, a state machine and an update circuit. The counter may be configured to present a first control signal and a second control signal in response to a reset signal and a third control signal. The state machine may be configured to generate a select signal in response to (i) the reset signal, (ii) the first control signal and (iii) the second control signal. The update circuit may be configured to generate a fourth control signal in response to the select signal.

Abstract: A method and apparatus for generating an output clock signal having a frequency fO derived from a reference clock signal having a frequency fR, such that f 0 = M N ⁢ f R , is satisfied, wherein M and N are integers and M<N. In the method, a plurality of intermediate clock signals are provided having a frequency fX, such that f X = 1 X ⁢ f R , wherein X is an integer close in value to N/M, and having a predetermined phase relationship with respect to one another.

Abstract: In one embodiment of the invention, a delay circuit generates a plurality of delay strobe signals from a plurality of data strobe signals during an operational mode and a calibration signal from a reference signal by an interval during a calibration mode. The plurality of delay strobe signals clocks a plurality of data into a plurality of registers. A calibrator adjusts the interval according to a timing relationship between the calibration signal and the reference signal.

Abstract: A time period (Td) is generated with a high accuracy and a high resolution. At a starting instant (ti) of the time period (Td), an analog integration operation (3) is started to generate an integration value (ios). At a certain instant (t1), the analog integration operation is interrupted to start counting (2) clock pulses (Clk). A selected number (N;N2) of clock pulses (Clk) is counted to obtain a sub-period (T2). The analog integration operation is resumed at the end of the sub-period (T2) at the integration value (ios) reached at the start of the sub-period (T2). The analog integration operation finishes at an end instant (td) of the time period (Td) at which the integration value (ios) crosses a reference value (Ref).

Abstract: A phase-locked loop circuit is constituted in such a manner that a delayed signal created by causing an input signal to loop through a delay stage a plurality of times is compared in terms of phase with the input signal, and an amount of delay in the delay stage is controlled in accordance with the comparison result of the delayed signal and the input signal. Therefore, the circuit size can be reduced with a reduced number of delay units constituting the delay stage.

Abstract: A fractional divider divides an input by a non-whole number M.N, where M is the integer part and N is the fractional part of the divisor. A delay line generates a group of multi-phase clocks from an input clock. A mux selects one of the multi-phase clocks as a selected clock. The selected clock increments a counter that counts to the integer part M. The selected clock also increments a rotational state machine. The rotational state machine makes the mux select a different one of the multi-phase clocks for the first N clocks so that the phase of the selected clock is rotated for N cycles. When multi-phase clocks having slightly higher delays are chosen, the selected clock's period increases, adding a fraction. When multi-phase clocks having slightly smaller delays are chosen, the selected clock's period is reduced, effectively subtracting a fraction. The delay line is part of a delay-locked loop that compares the phase of the last multi-phase clock to the input clock.

Abstract: Circuitry for adjusting the phase of an incoming periodic signal, typically a clock signal, throughout the entire period of the periodic signal. Phase adjustment circuitry has high resolution and employs only the number of delay elements in a delay chain necessary to span at least the period of the incoming signal or at least half the period in the case of dual chains receiving complementary clocks. Phase adjustment circuitry includes a delay chain of having a plurality of taps, a boundary detector for indicating when a tap is at a phase boundary of the incoming periodic signal, and selection circuitry for selecting one of the taps from the delay chain based on the boundary detector output and the selection circuitry input such that the selected tap is the desired phase adjustment of the incoming periodic signal and that the delay of the incoming signal is adjustable across its phase boundaries.

Abstract: A clock timing recovery circuit for recovering the clock timing from a baseband signal obtained by detection of a received signal. The clock timing is rapidly established using a clock signal which has been phase-shifted from the desired clock timing to sample the baseband signal, and by obtaining the optimum phase from the sampled signal obtained as a result. A clock-timing recovery circuit according to this invention does not require oversampling and provides easy optimization of circuit constants.

Abstract: A system is provided for generating an accurate and stable output clock signal of a desired output frequency in response to a system clock signal having a system clock period. The system uses an accurate and stable reference clock signal. The system comprises a measuring circuit and a ratio counter. The measuring circuit receives and processes the system clock signal and produces a measurement, referred to as the system clock measurement, that is indicative of the system clock period. The ratio counter receives the system clock signal and the system clock measurement and generates the output clock signal. The system is resistant to noise in the output clock signal caused by asynchronicity between the system clock signal and the reference clock signal. The system is resistant because it employs at least one of a lock-on unit and a synchronizing controller in operating the clock measuring circuit.

Abstract: An integrated circuit and method produce a first clock signal (CLOCK) from a reference clock (REFCLK) but at a different frequency. A variable delay line (32) produces the first clock signal by introducing a variable delay in the reference clock signal that is controlled by a programming signal generated in a counter (34). The programming signal is incremented by a second clock signal (UP) while transitions of a fixed delay clock signal lead transitions of the first clock signal. When the programming signal reaches the count of a rollover code (ROLLOVER), the programming signal is reset to a zero count to begin a new sequence. A calibration circuit (36, 38, 40, 42) determines the count of the programming signal needed to produce the rollover code when the variable delay is at least as great as one period of the reference clock signal.

Abstract: The present invention provides a method of and an apparatus for producing an output signal which is, relative to a periodic input signal, delayed by a predetermined phase angle phi. Initially, the phase angle phi between 0 and 2.pi. is divided by 2.pi. and multiplied by a predetermined positive integer number Z, whereby an integer phase number F between 0 and Z in obtained after rounding. Then, timing-pulse are, beginning with zero, counted between a first and a second input pulse, and an integer relative phase number P is obtained from the number N of the timing-pulses by multiplying by the phase number F, dividing by Z and rounding. Following the second input signal, the timing pulses are, beginning with zero, counted until the relative phase number P in reached. At last, an output pulse is emitted upon reaching the relative phase number P.

Abstract: A digital phase shifter phase shifts an input signal by a predetermined phase angle. A length of a cycle of the input signal is determined. Then an output signal is generated which is phase delayed from the input signal by a phase amount. The phase amount is approximately equal to the length of the cycle of the input signal multiplied by the predetermined phase angle.

Abstract: A first pseudo random number generating circuit sequentially provides an output signal to a matching detecting circuit in response to a clock signal. A second pseudo random number generating circuit generates an initial value, and then, sequentially provides an output signal to a storage device in response to an output signal from the matching detecting circuit and the clock signal. Data with the output signal as an address is provided as an output signal from the storage device. When the matching detecting circuit detects matching between the output signals, the matching detecting circuit provides the output signals to the second pseudo random number generating circuit and an AND logic circuit. As described above, when the output signal of the matching detecting circuit is provided, the output signals from the storage device are provided as respective output control signals.

Abstract: A self-calibration circuit for sensors and transducers that produce pulse-train outputs of the type having a count-until-disabled counter (250) which counts the number of pulses corresponding to a known value of the sensed or transduced quantity in a variable frequency pulse train during the time that a known number of pulses are counted in a reference pulse train by a frequency divider (210); the count accumulated by the count-until-disabled counter being stored, after accumulation, in a settable-divisor frequency divider (220 or 240) which can provide both calibrated sensor pulse-train outputs and calibration pulse-train outputs having the same frequency as the calibrated sensor pulse-train output at known values of the sensed parameter.

Abstract: The apparatus and method described herein provides for generating a delayed reference in response to a received reference. The occurrence of a first event in the received reference is detected and a delay period started in response thereto. At the end of the delay period a reset is generated. A delayed version of the received reference is then generated in response to the reset. In addition, a delayed signal is generated to steer a companion delay to the same value.

Abstract: A clock is phase shifted by an amount controlled by the value of a control signal by establishing at least several discrete delay times to be imposed on the clock. The control signal value controls selection of the imposed discrete delay time. An analog-to-digital converter of a phase locked loop responds to intelligence representing variable phase bits and the selected phase shifted clock to control the signal value. The selected replica is derived by at least several cascaded substantially equal time delay units. In one embodiment, a multiplexer responds to the clock, and the signal value, which is Gray coded, to control connections from one of the delay units to an output terminal. In another embodiment, the number of cascaded delay units interposed between the clock and an output terminal is controlled by the signal value.

Abstract: A digital phase detector that stores four sequential digital samples in a shift register. The contents of the shift register is evaluated at one half the clock frequency which generated the digital samples. The digital phase detectors predicts what the value should be for each of the two middle samples in the shift register. The predicted value and the actual value of each middle are used to generated a correction signal. The correction signals for the two middle samples are then added to produce a total correction signal which is to be used in controlling the phase and frequency of the voltage controlled oscillator in the phase locked loop generating the clock that controls the generation of the digital samples.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means.

Abstract: A waveform formatter for use in testing a semiconductor device is capable of reducing a total size of circuit configuration. The waveform formatter includes a plurality of clock generators in which at low-speed operation, clocks are used to generate waveforms and control signals of drivers, while at high-speed operation, all clocks are used to generate waveforms for drivers. The waveform formatter further includes a parallel-serial converter for converting parallel signals to a serial signal, a data selector for selecting the parallel signals or the serial signal, and a waveform combining circuit for accepting output signals of the clock generators through a format control unit and for generating waveforms and control signals for the drivers using the clocks from the clock generators.

Abstract: The use of three identical delay line circuits enables one of said delay circuits to be connected as a minimum delay reference and a second delay circuit to then be continuously compared to said minimum delay reference delay circuit to provide a code which calibrates the second delay line circuit by indicating and controlling continuously the length of the second delay line circuit to provide an exactly 360-degree phase shift of the reference signal under variable temperatures, pressures and voltages. Then, by maintaining the length of the third identical delay line at said determined 360-degree length, and by being able to select any tap output of the third identical delay line circuit responsive to a command, the third delay line circuit provides an adjustable, feedback calibrated, delay line circuit.