Abstract: A phase interpolator circuit may comprise a multiplexer circuit (MUX) coupled to a plurality of clock signals at MUX inputs and may provide a first clock signal and a second clock signal at MUX outputs that are out of phase with each other, a digital to analog converter circuit (DAC) to convert a digital input to first and second DAC current outputs such that a sum of the first and second DAC output currents comprises a substantially constant current value, a weighted averager circuit coupled to the MUX and the DAC, and a variable capacitive load circuit coupled to the first and second DAC current outputs. The weighted averager circuit may operate to sum weighted first and second clock signals and to output a phase interpolated clock signal, wherein the first clock signal is weighted according to a first DAC output current and the second clock signal is weighted according to a second DAC output current. Other apparatus, systems, and methods are disclosed.

Abstract: A first-phase clock signal is generated in response to a first input clock signal. A second-phase clock signal is generated one clock cycle of the first input clock signal after generating the first-phase clock signal in response to the first input clock signal. A third-phase clock signal is generated one and one half clock cycles of the first input clock signal after generating the second-phase clock signal in response to a second input clock signal. A fourth-phase clock signal is generated one clock cycle of the first input clock signal after generating the third-phase clock signal in response to the second input clock signal.

Abstract: Integrated circuit serializer circuitry is provided that converts parallel data to serial data on an integrated circuit. A two-phase global serializer master clock generator uses a four-phase internal clock to generate a two-phase global serializer master clock. The two-phase global serializer master clock is distributed globally on the integrated circuit using a distribution path. The integrated circuit has multiple serial communications channels each of which has an associated serializer. Each serializer contains circuitry that derives a number of clock signals from the two phases of the global serializer master clock. Each serializer uses the derived clocks in converting parallel data to serial data for transmission over its associated serial communications channel. The serializers each contain two smaller serializers that convert first and second sets of parallel data to first and second serial outputs. A 2:1 serializer in each serializer merges the first and second serial outputs.

Abstract: A single-ended to differential converter uses a cross-coupled latch that maximizes the output zero-crossing symmetry and is self compensating over PVT variations. An in-phase driving signal is provided by an always-on transmission gate coupled to the input. An out-of-phase driving signal is provided by an inverter coupled to the input. The in-phase and out-of-phase driving signals each drive an input of the cross-coupled latch. The in-phase driving signal from the always-on transmission gate starts to bring the cross-coupled latch into conduction, and when the out-of-phase driving signal arrives, the simultaneous driving of the cross-coupled latch causes a rapid and symmetric transition of both outputs of the cross-coupled latch.

Abstract: Systems and methods are disclosed to provide static and/or dynamic phase adjustments to a data signal relative to a clock signal. For example, the data signal may be delayed by a coarse delay and/or a fine delay to match the timing of the clock signal independently for each input path (e.g., per input pad). The delay may be as a function of positive and/or negative clock edges.

Abstract: Multiphase clock generators and methods are provided. A multiphase clock generator has a first clock divider for generating a first-phase clock signal from a first input clock signal. A first logic gate is connected to an output port of the first clock divider. A second clock divider is connected to an output port of the first logic gate. The second clock divider is for generating a second-phase clock signal from the first input clock signal. A second logic gate is connected to an output port of the second clock divider. A third clock divider is connected to an output port of the second logic gate. The third clock divider is for generating a third-phase clock signal from a second input clock signal.

Abstract: A phase splitter circuit includes a first signal generator and a second signal generator. The first signal generator generates a first signal in response to an input signal. The second signal generator generates a second signal in response to the input signal. The phase of the first signal is different from that of the first signal. In particular, the phase splitter circuit has a means that is capable of controlling the first and second signals such that transition times thereof are equal. As a result, the phase splitter circuit may fulfill not only delay matching of each element, but also equality of the transition times of output signals.

Abstract: So as to generate multiple output signals whose phases are evenly spaced about 360 degrees, and having a frequency equal to that of an input signal, a phase multiplier circuit includes three or more instances of a phase multiplier subcircuit and additional circuitry configured in a negative feedback loop. Each phase multiplier subcircuit includes a difference circuit, a loop filter transistor, and a voltage-controlled delay circuit. The difference circuit converts to a phase current a delay from an input signal to the delay circuit to an output signal from the delay circuit, and subtracts from the phase current a bias current proportional to the smallest positive delay from the output signal with the largest phase to the output signal with the smallest phase. The subtracted current is integrated by the loop filter transistor, and steady-state operation is achieved when for each phase multiplier subcircuit, the bias current is equal to the phase current.

Abstract: A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

Abstract: A direct conversion receiver having a DC offset eliminating function that eliminates a DC offset component in which an oscillator generates a local frequency signal, A first phase shifter shifts a phase of the local frequency signal from the oscillator by 90°, a first frequency mixer mixes the received radio frequency signal and the local frequency signal from the oscillator, a first low pass filter low-pass filters an output signal of the first frequency mixer, a second phase shifter shifts a phase of the received radio frequency signal by 90°, a second frequency mixer mixes output signals of the first and second phase shifters, a second low pass filter low-pass filters an output signal of the second frequency mixer, a subtracter subtracts an output signal of the second low pass filter, and a DC offset component generated by a direct conversion receiver is eliminated. Accordingly, the receiver prevents a dynamic range of the direct conversion receiver to be narrowed in order to increase a resolution thereof.

Abstract: A master DLL circuit (3) generates a first delay signal (CKD) by delaying the master clock signal by a first delay time (T0) and generates a first pulse signal (Smp) having a pulse width (T0) of the first delay time, and generates a first control signal (Scp) which is changed in accordance with the first pulse signal (Smp), and adjusts the first delay time (T0) in accordance with the first control signal (Scp). Each slave DLL circuit (D1 to Dm) delays, by a second delay time (td), a delay internal clock signal, and outputs the delayed delay internal clock signals (CK1 to CKm) which form the multiphase clock signals. Each slave DLL circuit generates a second pulse signal (Ssp) having a pulse width (td) of the second delay time, and generates a second control signal (Scp1) which is changed in accordance with the first and second pulse signals (Smp, Ssp), and adjusts the second delay time (td) in accordance with the second control signal (Scp1), thus reducing a skew value of the multiphase clock signal.

Abstract: A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

Abstract: The present invention provides an inverter controller comprising a drive circuit that generates a plurality of switch drive signals for inverter applications. In some exemplary embodiments, the drive circuit operates by reversing the command level of an error signal. In other embodiments, the drive circuit operates by using a half period of a sawtooth signal. In still other embodiments, the drive circuit operates by using a double period opposite shifting pulses method. The present invention also provides a PWM signal generator circuit that generates periodic PWM switch drive signals symmetrical to the minimum or maximum of a sawtooth waveform.

Abstract: Multiphase clock generators and methods are provided. A multiphase clock generator has a first clock divider for generating a first-phase clock signal from a first input clock signal. A first logic gate is connected to an output port of the first clock divider. A second clock divider is connected to an output port of the first logic gate. The second clock divider is for generating a second-phase clock signal from the first input clock signal. A second logic gate is connected to an output port of the second clock divider. A third clock divider is connected to an output port of the second logic gate. The third clock divider is for generating a third-phase clock signal from a second input clock signal.

Abstract: A phase shift control voltage distribution scheme for a phased array utilizes analog voltage-proportional phase shift devices, to which respective input signals are supplied and from which phase-shifted output signals are produced. A voltage supply unit has a plurality of voltage outputs supplying respectively different analog voltages. A switch network coupled between voltage outputs of the multiple voltage supply unit and the voltage control inputs of the plurality of voltage-controlled phase shift elements, is operative to selectively couple any of the different voltages supplied by the multiple voltage supply unit to the voltage control inputs of any of the voltage-controlled phase shift elements.

Abstract: Disclosed is an apparatus for generating two constant width and symmetrical drive signals from two separate, but complementary, pulse width modulated control signals while also generating two pulse width modulated drive signals corresponding to said pulse width modulated control signals. The constant width drive signals are generated through the use of a toggle or latch set/reset circuit actuated by a given characteristic of each of the control signals.

Abstract: A multi-phase clock generation circuit includes a clock generation circuit, first frequency divider circuit, first clock selection circuit, second to nth frequency divider circuits, second to nth clock selection circuits, and clock selection control section. The clock generation circuit generates 2n (n is a positive integer) reference clock signals having the same frequency and different phases. The frequency divider circuit frequency-divides one of the reference clock signals by 2 to generate clock signals 180° out of phase with each other. The first clock selection circuit selects one of each of the clock signals and a corresponding reference clock signal and outputs the selected signals as clock pulses. Each of the second to nth frequency divider circuits frequency-divides a clock pulse to generate clock signals 180° out of phase with each other.

Abstract: A phase splitter is formed by first and second branches that generate respective first and second complimentary output clock signals from an input clock signal. The first branch includes two series connected inverters, the first of which receives the input clock signal and the second of which outputs a non-complimentary output clock signal. The second branch includes three series connected inverters, the first of which receives the input clock signal and the third of which outputs a complimentary output clock signal. An inverter is coupled from the output of the second inverter in the second branch to the output of the first inverter in the first branch to increase the slew rate of the signal applied to the input of the second inverter. In one embodiment, first and second parallel pairs of diode-coupled transistors are coupled from the output of the third inverter in the second branch to the outputs of respective first inverters in the first and second branches.

Abstract: An apparatus for generating quadrature phase signals in a half-rate data recovery circuit, which is adapted to generate a first and a second clock signals having the same frequency and being 90 degrees out of phase with each other. The apparatus for generating quadrature phase signals mainly comprises a base selector, a first phase interpolator and a second phase interpolator. The base selector generates, based on a region control signal, a pair of phase region boundaries for the first clock signal as well as a pair of phase region boundaries for the second clock signal by using a plurality of reference clock signals. The first and second phase interpolators perform, based on a position control signal, weighted average processes for the two pairs of phase region boundaries, respectively, to thereby obtain the first and the second clock signals.

Abstract: A quadrature signal generator includes a polyphase filter where four resistive elements and four variable capacitive elements are connected alternately in series to form a loop; and a phase corrector that variably controls the capacitance of the variable capacitive elements.

Abstract: A clock controller and clock generating method are provided for AC self-test timing analysis of a logic system. The controller includes latch circuitry which receives a DC input signal at a data input, and a pair of continuous out-of-phase clock signals at capture and launch clock inputs thereof. The latch circuitry outputs two overlapping pulses responsive to the DC input signal going high. The two overlapping pulses are provided to waveform shaper circuitry which produces therefrom two non-overlapping pulses at clock speed of the logic system to be tested. The two non-overlapping pulses are a single pair of clock pulses which facilitate AC self-test timing analysis of the logic system.

Abstract: The invention relates to a phase-interpolation circuit and a phase-interpolation signal generating circuit applying the phase-interpolation circuit. The phase-interpolation circuit can avoid short-circuit current effectively. In addition, an inter-phase signal can be interpolated between the rising edge and the falling edge of the clock pulse. The phase-interpolation signal generating device can generate multiphase clock signals which not only have linearly distributed phases but also maintain good 50% duty cycle of the multiphase clock signals.

Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Abstract: In a non-overlap clock generator circuit providing two-phase clock signals, the clock-to-Q delay of memory elements is used to define the non-overlap times. The non-overlap time can be programmed in increments of the clock-to-Q delay of a standard memory element.

Abstract: A phase splitter. The splitter includes a transistor having a gate receiving an input signal, a drain and source outputting a first and second output signal with a first and second phase, respectively, a current source providing a current flowing from the drain to the source of the transistor, and a feedback tuning circuit receiving the first and second output signal, and tuning the current according to the first and second phase.

Abstract: A phase splitter circuit including a clock delay section, a signal converter section and a signal generator section. The clock delay section uses a clock signal to produce first and second delayed clock signals that are time delayed versions of the clock signal. The second delayed clock signal is delayed more than the first. The signal converter section converts a static logic signal to a dynamic logic signal dependent upon the clock signal and the first delayed clock signal. The signal generator section produces a pair of complementary dynamic logic output signals dependent upon the dynamic logic signal and the first and second delayed clock signals. One of the output signals has a logic value equal to that of the static logic signal during an evaluation phase of the clock signal. A method for generating a pair of complementary dynamic logic signals from a static logic signal.

Abstract: An approach for precise signal interpolation. For one aspect, each of the linear resistive elements in a first array of selectable linear resistive elements receives a first input signal. Each of the linear resistive elements is coupled to provide an output signal on a first output signal line. A variable bandwidth-compensating circuit is coupled to the first output signal line to compensate the bandwidth of the output signal.

Abstract: The invention provides an improved differential output structure with minimal skew and introduces less process variations. According to one embodiment of the invention, a differential output structure is provided and comprises an input line, an output driver and a sync circuit. The input line includes first and second paths. The first path has an input end for receiving input signals. The first path also has an output end and includes at least one driving element. The second path has an input end operably coupled to the input end of the first path for receiving the input signals. The second path also has an output end. The output driver is operably coupled to the output ends of the first and second paths and is configured to provide differential outputs. The sync circuit is operably coupled between the first and second paths and is configured to synchronize the speed of signals traveling on the two paths.

Abstract: An approach for precise signal interpolation. For one aspect, each of the linear resistive elements in a first array of selectable linear resistive elements receives a first input signal. Each of the linear resistive elements is coupled to provide an output signal on a first output signal line. A variable bandwidth-compensating circuit is coupled to the first output signal line to compensate the bandwidth of the output signal.

Abstract: The present invention provides a semiconductor switching circuit and a semiconductor device using the switching circuit that can maintain sufficient isolation characteristics even when dealing with high frequency signals. The semiconductor switching circuit includes a first semiconductor switching element connected between a first terminal and a second terminal, a second semiconductor switching element, one end of the second switching element being connected to one of the first and second terminals, and an open stub connected to the other end of the second switching element.

Abstract: A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

Abstract: The invention relates to a balanced circuit arrangement for converting an asymmetric analogous input signal (S1) into a symmetrical output signal (S2, S3). A first amplifier (2) is provided, whereby the non-inverting input thereof is connected to the analogous input signal (S1) and the output signal (S2) thereof is fed back to the inverting input thereof in a negative feedback. Moreover, a second amplifier (3) is provided, whereby the non-inverting input thereof is connected to ground, the inverting input thereof is connected to the output signal (S2) of the first amplifier (2) by means of a series resistor (R2) and the output signal (S3) thereof is fed back to the inverting input thereof in a negative feedback and by means of a negative feedback resistor (R1). The negative feedback resistor (R1) and the series resistor (R2) are provided with the same resistance value. The aim of the invention is to process higher maximum levels of the source signal and to suppress noises of the second amplifier.

Abstract: The polyphase signal generator includes a first delay circuit which adds a first predetermined phase delay to an input signal, a first phase interpolation circuit which generates a first output signal having an output phase prescribed according to a phase difference between the input signal input to one terminal of the first output signal generation unit and a signal input to another terminal of the first output signal generation unit which is output from the delay addition unit, and a second phase interpolation circuit which generates a second output signal having an output phase prescribed according to a phase difference between a signal input to one terminal of the second output signal generation unit which is output from the delay addition unit and an inverted signal of the input signal input to another terminal of the second output signal generation unit.

Abstract: A semiconductor integrated circuit includes a clock signal source for generating two-phase clock signals having spacing periods, a two-phase clock wiring for transmitting the two-phase clock signals to a plurality of internal circuits constructing the integrated circuit, and a waveform correction circuit having a plurality of MOS transistors of the same conductivity type connected between the two-phase clock wiring and a preset potential node and constructed to attain spacing periods of the two-phase clock signals. The waveform correction circuit corrects the blunted portions of the two-phase clock signals to stably attain spacing periods, and when it is distributed and arranged in portions far apart from the clock signal source, a problem of racing and the like can be effectively suppressed.

Abstract: In a phase difference signal generator, a first delay circuit has a delay time of nx where n ix 2, 3, . . . and x is a voluntary real number, the delay circuit receiving a first input clock signal having a phase of 0° to generate a first phase difference signal. At least one k-to-(n−k) weighted phase interpolator has a first input for receiving an output signal of said first delay circuit and a second input for receiving a second input clock signal having a phase of &thgr; to generate an output signal having a phase of (n−k)x+k&thgr;/n where k is 1, 2, . . . , n−1. At least one second delay circuit is connected to the k-to-(n−k) weighted phase interpolator. The second delay circuit has a delay time of kx to generate a k-th phase difference signal.

Abstract: A phase splitter circuit includes a first signal generator and a second signal generator. The first signal generator generates a first signal in response to an input signal. The second signal generator generates a second signal in response to the input signal. The phase of the first signal is different from that of the first signal. In particular, the phase splitter circuit has a means that is capable of controlling the first and second signals such that transition times thereof are equal. As a result, the phase splitter circuit may fulfill not only delay matching of each element, but also equality of the transition times of output signals.

Abstract: A buffer having first and second input terminals and an output terminal. The buffer also includes a fast edge driver having an input terminal and an output terminal, with the input terminal connected to the first input terminal of the buffer, and the output terminal connected to the output terminal of the buffer. A shielding circuit is provided having an input terminal and an output terminal, with the input terminal connected to the second input terminal of the buffer. The buffer further includes a recovery circuit having an input terminal and an output terminal, with the input terminal connected to the output terminal of the shielding circuit, and the output terminal connected to the output terminal of the buffer.

Abstract: The present invention relates to a tunable quadrature phase shifter comprising an input (IN) for inputting an input signal (vin), splitting means (10) for splitting the input signal into two essentially orthogonal first and second signals (i1, i2), adding means (6) for adding said first and second signals (i1, i2), subtracting means (7) for subtracting said first and second signals (i1, i2), a first output (OUT+) for outputting a first output signal (vo1) based on the output signal from said adding means (6), and a second output (OUT−) for outputting a second output signal (vo2) based on the output signal from said subtracting means (7), wherein that said splitting means (10) is provided as an all-pass.

Abstract: An integrated circuit device with reduced noise is described. In traditional simultaneous output switching integrated circuits the noise is proportional to the number of concurrently switching outputs. This excessive supply noise can cause the integrated circuit to malfunction through the loss of data. In the present invention, switching supply noise is reduced in the device without increasing the number of input-output pins by synchronously skewing the output driver. In a preferred embodiment, flip-flops are used to control the phase of the switching outputs in order to reduce the noise and instantaneous power by the number of phase assignments.

Abstract: The invention relates to a phase-interpolation circuit and a phase-interpolation signal generating circuit applying the phase-interpolation circuit. The phase-interpolation circuit can avoid short-circuit current effectively. In addition, an inter-phase signal can be interpolated between the rising edge and the falling edge of the clock pulse. The phase-interpolation signal generating device can generate multiphase clock signals which not only have linearly distributed phases but also maintain good 50% duty cycle of the multiphase clock signals.

Abstract: A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

Abstract: A phase splitter is formed by first and second branches that generate respective first and second complimentary output clock signals from an input clock signal. The first branch includes two series connected inverters, the first of which receives the input clock signal and the second of which outputs a non-complimentary output clock signal. The second branch includes three series connected inverters, the first of which receives the input clock signal and the third of which outputs a complimentary output clock signal. An inverter is coupled from the output of the second inverter in the second branch to the output of the first inverter in the first branch to increase the slew rate of the signal applied to the input of the second inverter. In one embodiment, first and second parallel pairs of diode-coupled transistors are coupled from the output of the third inverter in the second branch to the outputs of respective first inverters in the first and second branches.

Abstract: A transimpedance circuit adapted for use in a subscriber line interface circuit includes sense resistors installed in closed loop, negative feedback paths of respective sense amplifiers. Voltage drops across the sense resistors are applied to first and second differential coupling circuits for applying differential currents to complementary polarity inputs of an operational amplifier. The inputs of the amplifier are also coupled to a linearity compensator, that is configured to provide sufficient overhead voltages in the presence of worst case voltage swing conditions. The compensator has a differential amplifier configuration, that closes a negative feedback loop from the output of the amplifier and one of its inputs, relative to a reference voltage balancing path coupled to the amplifier's other (complementary) input.

Abstract: A multiphase clock generator includes oscillator, selector circuit and frequency divider circuit. The oscillator generates a first multiphase clock having a first phase difference. The selector circuit receives the first multiphase clock from the oscillator and outputs a second multiphase clock including a plurality of clock signals. In the second multiphase clock, the phase of each clock signal is shifted from that of the previous one by a second phase difference. The second phase difference is n times as long as the first phase difference, where n is a predetermined positive integer. And the frequency divider circuit receives the second multiphase clock from the selector circuit, divides the frequency of the second multiphase clock by a predetermined number and then outputs a group of clock signals with the divided frequency as a third multiphase clock.

Abstract: A system and corresponding method for generating multiple phases within a single clock cycle of an input signal is disclosed. The method includes the steps of generating a plurality of output signals from an input source signal, where each of the plurality of output signals represents a phase-shifted version of the input signal. Next, select a pair of signals from the plurality of output signals to act as clock signals, where the selected pair of clock signals define the operating region within which the multiple phases are bounded. Then, provide a pair of complementary weighted bias currents in response to a control signal, where each of the complementary bias currents is used to generate the multiple phases of the present invention. Thereafter, the pair of weighted bias currents presented to a node are adjusted in response to the selected pair of clock signals, where the selected pair of clock signals operates to adjust the rate of change of the weighted bias currents.

Abstract: There is disclosed a 90-degree phase shifter so configured that an input signal is supplied through a variable gain amplifying circuit and a phase adjusting circuit to a low pass filter and also supplied through another variable gain amplifying circuit and another phase adjusting circuit to a high pass filter, so that the low pass filter and the high pass filter generate output signals, respectively, which have a 90-degree phase difference therebetween. An amplitude error and a phase error between the output signals are detected, so that the variable gain amplifying circuits are gain-controlled by the detected amplitude error, and the phase shift amounts of the phase adjusting circuits are controlled by the detected phase error. Thus, the amplitude error and the phase error attributable to the variation in the device characteristics and the parasite component can be removed, so that it is possible to obtain the output signals having the 90-degree phase difference with no amplitude error and no phase error.

Abstract: A sense amplifier drive circuit has a sense amplifier amplifying data carried on a bit line and a bit line bar, a sense amplifier drive unit selectively applying an overdrive voltage or an internal power supply voltage to the sense amplifier, and a control signal generator combining a sense amplifier enable bar signal and a refresh enable signal, and generating control signals to control the sense amplifier drive unit. With the construction, an overdrive voltage is not supplied to the bit line and bit line bar during a refresh operation, and current consumption inevitably occurring during the refresh operation is much reduced.

Abstract: A phase interpolater circuit includes a first adjustable current supply to generate a first current that is based on the amplitude of a first controlled voltage and a first current mirror circuit to generate a second current that is based on the first current. The phase interpolater circuit further includes a first current steering switch to steer the second current to one of first and second nodes to generate a first voltage transition at one of the first and second nodes, the second current being steered to the first node when a first input signal is in a first state and to the second node when the first input signal is in a second state.

Abstract: A phase adjusting circuit including an input level adjuster using two detection signals having different phases and adjusting an amplitude of at least one detection signal to a predetermined level and a signal processor for signal processing including at least one of addition and subtraction on the two detection signals after level adjustment to generate a pair of output signals having a phase difference of 90 degrees or a single output signal having a phase difference of 90 degrees with respect to one of the detection signals, and a position measuring apparatus including an output level adjuster, a scaling signal generator, a detector, an A/D converter, and a memory in addition, wherein the position measuring apparatus cancels a phase error so that a signal having a phase difference of 90 degrees can be obtained.

Abstract: A synchronous memory device and system are described which communicates bi-directional data via a bus and data clock. To capture data from the bus, a memory device latch circuit is described which operates in response to internally generated clock signals. A pulse generator circuit is described which produces these internal clock signals, and insures accurate latching of data by minimizing signal skew between the internal clock signals to avoid wasting valuable timing. The pulse generator circuit has at least two propagation paths that are symmetrical and operate in response to clock signals which are 90 degrees out-of-phase. A second pulse generator circuit is described minimizes skew by having symmetrical clock paths and also corrects duty cycle error present on the data clock. This second circuit uses three clock signals which have relative phases of 0, 90 and 180 degrees.