Abstract: A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.

Abstract: Apparatuses, systems, and methods for data timing alignment in stacked memory. The memory a number of core dice stacked on an interface die. The core and interface die each include adjustable delay circuits along each of a delay and native path. A state machine operates interface and core aligner control circuits to set values of the delay(s) in the interface and core dice respectively. The state machine may initialize the delays and then enter a maintenance state where averaging is used to determine when to adjust the delay in the core dice. If an overflow or underflow condition is met, the state machine may cycle between adjusting the delay in the interface die and adjusting the delays in the core dice without averaging until the overflow and underflow conditions are no longer met and the maintenance state is returned to.

Abstract: A clock delay circuit is configured to generate a delayed clock signal based on an input clock signal, the delayed clock signal delayed by a delay time (TDEL). The circuit includes a current mirror configured to generate starved currents based on the reference current, a plurality of inverters, and a Schmitt trigger configured to generate an output signal in response to the input clock signal, wherein the Schmitt trigger output signal increases from a low signal to a high signal over a period (TCHARGE) correlated with TDEL. Some inverters and the Schmitt trigger are configured to be current starved when the input clock signal is high and are configured to be shorted to ground and the reference current when the input clock signal is low. TDEL is based on TCHARGE and TCHARGE is based on C, NTOP, VST,High, and a supply voltage.

Abstract: A power amplification system comprises a current source configured to provide a bias current, a current mirror configured to mirror the bias current, and a comparator configured to compare the mirrored bias current to a threshold current and, in response to the mirrored bias current exceeding the threshold current, cause a reduction of output power.

Abstract: A delay circuit includes precharge and discharge transistors configured to receive an input signal. The delay circuit also includes a resistor coupled to the precharge transistor having a negative temperature coefficient to thereby form a node. A capacitive device and an inverter are coupled to the node. The inverter produces an output signal. Responsive to the input signal having a first polarity, the precharge transistor is configured to be turned on and the discharge transistor is configured to be turned off to thereby cause current to flow through the precharge transistor to the capacitive device to thereby charge the capacitive device. Responsive to the input signal having a second polarity, the precharge and discharge transistors are configured to change state to thereby cause charge from the capacitive device to discharge through the resistor and through the discharge transistor. The voltage on the node decays to a level which eventually causes the inverter's output to change state.

Abstract: A field-programmable gate array (FPGA) with reconfigurable threshold logic gates for improved performance, power, and area (PPA) is provided. This disclosure describes a new architecture for an FPGA, referred to as threshold logic FPGA (TLFPGA), that integrates a conventional lookup table (LUT) with a complementary metal-oxide-semiconductor (CMOS) digital implementation of a binary perceptron, referred to as a threshold logic cell (TLC). The TLFPGA design described herein, combined with a new logic mapping algorithm that exploits the presence of both conventional LUTs and TLCs within the basic logic element (BLE) block, achieves significant improvements in all the metrics of PPA. The TLCs of embodiments described herein are capable of implementing a complex threshold function, which if implemented using conventional gates would require several levels of logic gates. The TLCs only require seven static random-access memory (SRAM) cells and are significantly faster than the conventional LUTs.

Abstract: A dual rail memory operable at a first voltage and a second voltage is disclosed. The dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal, wherein the data path includes a first level shifter for transferring the input data signal from the second voltage to the first voltage; and a control circuit configured to provide control signals to the memory array, the word line driver circuit and the data path, wherein the control circuit includes a second level shifter for transferring an input control signal from the second voltage to the first voltage; wherein the data path and the control circuit are configured to operate at both the first and second voltages.

Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

Abstract: Aspects of the invention relate to an apparatus having a transmission gate coupled to a delay element and including a first transistor and a second transistor. A first node is coupled to a first gate of the first transistor, a first current source, and a first resistive element, an opposite end of the first resistive element being coupled to a ground potential. A second node is coupled to a second gate of the second transistor, a second current source, and a second resistive element, an opposite end of the second resistive element being coupled to a power supply.

Abstract: Apparatuses and methods for multi-level communication architectures are disclosed herein. An example apparatus may include a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals. A count of the plurality of bitstreams is greater than count of the plurality of multilevel signals. The driver circuit further configured to drive the plurality of multilevel signals onto a plurality of signal lines using individual drivers. A driver of the individual drivers is configured to drive more than two voltages.

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

Abstract: A semiconductor device may include a local power domain configured to selectively provide or prevent power to a logic block of the memory device and a temperature sensor located on the semiconductor device. The semiconductor device may also include timeout circuitry to delay a power down of the local power domain by a timeout time based at least in part on temperature information from the temperature sensor.

Abstract: In generating a mask signal used to recover a clock signal embedded in an interface signal, the mask signal may be generated by comparing a plurality of comparison signals, generated by delaying a plurality of mask rising signals by a predetermined time, with the clock signal and selecting one mask rising signal used to generate a comparison signal close to one portion of the clock signal from among the plurality of mask rising signals.

Abstract: A ramp signal generation device includes a sampling circuit suitable for sampling a ramp current, which flows on a plurality of ramp current paths, and storing a voltage corresponding to the sampled ramp current; a current maintaining circuit suitable for maintaining the ramp current; a current maintaining/transferring circuit suitable for maintaining and transferring a current corresponding to the voltage stored by the sampling circuit; a selection circuit suitable for selecting a ramp current path of the sampling block and the current maintaining/transferring circuit; and a current-to-voltage converter suitable for converting the current transferred from the current maintaining/transferring circuit and generating therefrom a ramp voltage.

Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.

Abstract: A memory system includes a memory device, and a memory controller. The controller adjusts a delay of a data strobe clock, performs at least one of a read test and a write test on the memory device, detect at least one data bit, which reduces at least one margin of a setup margin and a hold margin, from among a plurality of data bits, and adjusts a delay of the at least one data bit to allow the at least one margin to increase.

Abstract: A memory controller includes a clock delay generator, a set of flip-flops, and a control circuit, and is connected to a processor and a memory. The clock delay generator receives a clock signal from the processor, delays the clock signal by a set of delay time intervals, and generates a set of delayed clock signals. The flip-flops receive a test pattern and read data from the memory, sample the test pattern and the read data based on the delayed clock signals, and generate a set of sampled test patterns and a set of sampled read data. The control circuit identifies a sampled test pattern that is equal to the test pattern and the corresponding delayed clock signal as a read clock signal, and outputs the sampled read data that corresponds to the (delayed) read clock signal.

Abstract: A voltage conversion apparatus includes an output unit connected to an input voltage to output an output voltage according to a control signal. A comparator compares a reference voltage to a feedback voltage corresponding to the output voltage and outputs a comparison signal. A delay circuit outputs a delayed signal obtained by delaying either a rising timing or a falling timing of the comparison signal. The delay circuit varies a delay time of the delayed signal on basis of a modulating signal. A control circuit is configured to output the control signal to the output unit. The control signal is based on the delayed signal. The control circuit controls the output unit such that a frequency of the output voltage is tuned to a predetermined value set according to the modulating signal.

Abstract: A communication system includes a sensor apparatus, which includes sensing elements and a transmission circuit, and a microcomputer, which includes a reception circuit, a difference calculator, and a differential calculator. The transmission circuit shifts a transmission time point of one of sensor signals including sensor value detected by one of the sensing elements by a predetermined period with respect to a transmission time point of another one of sensor signals including sensor value detected by another one of the sensing elements. The predetermined period is set shorter than a transmission cycle of the transmission circuit. The difference calculator calculates a difference value so that an offset error among the sensing elements is compensated or a fluctuation caused by a variation in slopes of output characteristics of the sensing elements is reduced.

Abstract: An apparatus for clock deskew includes: a first delay element configured to receive a clock signal from a clock, wherein the delay element comprises multiple delay lines; a first multiplexer coupled to the multiple delay lines; a sensor configured to sense a voltage, a temperature, or both, and to provide a sensor output based at least on the sensed voltage and/or the sensed temperature; and a converter configured to receive the sensor output, and to generate a converted signal; wherein the first multiplexer is configured to provide a delay line output from one of the multiple delay lines based at least in part on the converted signal.

Abstract: A delay circuit includes precharge and discharge transistors configured to receive an input signal. The delay circuit also includes a resistor coupled to the precharge transistor having a negative temperature coefficient to thereby form a node. A capacitive device and an inverter are coupled to the node. The inverter produces an output signal. Responsive to the input signal having a first polarity, the precharge transistor is configured to be turned on and the discharge transistor is configured to be turned off to thereby cause current to flow through the precharge transistor to the capacitive device to thereby charge the capacitive device. Responsive to the input signal having a second polarity, the precharge and discharge transistors are configured to change state to thereby cause charge from the capacitive device to discharge through the resistor and through the discharge transistor. The voltage on the node decays to a level which eventually causes the inverter's output to change state.

Abstract: Methods and systems for compensating for temperature variation in the performance of electronic circuits and systems are disclosed. In some embodiments, the systems are configured to store compensation parameters determined in calibration, where the compensation parameters are used by the systems to modify performance. In some embodiments, the systems are part of an automatic test equipment (ATE) system.

Abstract: Master and slave devices may be coupled to a control data bus. A method includes controlling data transmissions over a bus using a master device. A clock signal is provided by the master device on a clock line (SCL) of a serial bus, a receive clock generated from transitions on the SCL line when a slave device is transmitting data on the SDA line, is calibrated using a delay based on a duration of time measured between an edge of the clock signal provided on the SCL line and at least one transition produced on the SDA line by a slave device in response to the edge of the clock signal. Data, including double data rate data, may be reliably received using the calibrated receive clock.

Abstract: A leakage current-based delay circuit is provided, wherein the delay circuit may include a first transistor circuit and a second transistor circuit, each transistor circuit may include a p-type transistor, an n-type transistor, an n-node between a drain node of the p-type transistor and a gate node of the n-type transistor, and a p-node between a gate node of the p-type transistor and a drain node of the n-type transistor. The p-node of the second transistor circuit may be charged based on a power source voltage through the first transistor circuit during a first time interval of an input signal, and the n-node of the second transistor circuit may be discharged based on a ground voltage through the first transistor circuit during the first time interval.

Abstract: A semiconductor device includes a calibration code generation circuit suitable for generating a calibration code by adjusting a period of a short-term oscillation signal oscillating at a period less than a reference period, based on a reference oscillation signal oscillating at the reference period; and a delay circuit suitable for setting a delay value based on the calibration code.

Abstract: A delay circuit may include a fine timing measurement unit suitable for measuring fine timing information on whether an input signal corresponds to the timing of any one of an even cycle or an odd cycle based on a clock, a coarse delay unit suitable for delaying the input signal whose fine timing has been measured by the fine timing measurement unit in synchronization with a frequency divided clock and outputting a delayed signal, and a fine timing application unit suitable for applying the fine timing information to the delayed signal of the coarse delay unit.

Abstract: Methods and systems for compensating for temperature variation in the performance of electronic circuits and systems are disclosed. In some embodiments, the systems are configured to store compensation parameters determined in calibration, where the compensation parameters are used by the systems to modify performance. In some embodiments, the systems are part of an automatic test equipment (ATE) system.

Abstract: A clock generating device measures a frequency ratio between a clock signal (32.768 kHz+?) and a reference frequency value based on a clock signal (25 MHz); generates a clock signal obtained by masking a portion of clocks of the clock signal based on a measurement result of the frequency ratio; and updates a compensation value of a frequency temperature characteristic of the clock signal when a difference between the measurement result of the frequency ratio and an average value of N (N is a natural number) measurement results is greater than a reference value of the frequency ratio.

Abstract: An object is to provide a programmable logic device which can hold configuration data even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, and can operate with low power. A transistor in a memory portion of a programmable switch includes a material which allows a sufficient reduction in off-state current of the transistor, such as an oxide semiconductor material which is a wide bandgap semiconductor. When the semiconductor material which allows a sufficient reduction in off-state current of the transistor is used, configuration data can be held even when a power supply potential is not supplied.

Abstract: Systems and methods for improving timing closure of new and existing semiconductor products by balancing sensitivities. More specifically, a method is provided for that includes defining at least one set of correlated parameters for a semiconductor product, the at least one set of correlated parameters comprising a first parameter and a second parameter. The method further includes measuring performance of embedded devices within the semiconductor product. The method further includes closing timing of the semiconductor product using the measured performance of the semiconductor product. The closing the timing of the semiconductor product comprises calculating a sensitivity to the first parameter based on the measured performance of the embedded devices within the semiconductor product and balancing the sensitivity to the first parameter with a sensitivity to a second parameter such that timing degradation is shifted from the first parameter to the second parameter.

Abstract: A clock generation device measures a frequency ratio between a clock signal CK1 (32.768 kHz+?) and a reference frequency value based on a clock signal CK3 (25 MHz), generates a clock signal CK2 obtained by masking at least one clock pulse of the clock signal CK1 based on the measurement result of the frequency ratio, and controls the measurement interval of the frequency ratio based on the difference between the measurement result of the frequency ratio and an average value of N (N is a natural number) measurement results of the frequency ratio.

Abstract: Technologies are generally described for quadrature-based injection-locking of ring oscillators. In some examples, an external signal may be injected into a ring oscillator. Phase signals may be measured from within the ring oscillator and used to determine a mean quadrature error (MQE) that characterizes the difference in frequency between the external signal and the ring oscillator's natural frequency. A control signal may then be generated from the MQE and used to adjust the ring oscillator natural frequency to reduce the difference between the ring oscillator natural frequency and the external signal.

Abstract: Circuits, apparatuses, and methods are disclosed for oscillators. In one such example oscillator circuit, a plurality of delay stages are coupled in series. A variable delay circuit stage is coupled to the plurality of delay stages and is configured to delay a signal through the variable delay circuit stage by a variable delay. The variable delay increases responsive to a rising magnitude of a supply voltage provided to the variable delay circuit stage.

Abstract: There are provided a pulse generator capable of securing a maximum transfer rate of an IR-UWB signal, while maintaining low power consumption characteristics of an all-digital scheme, and a method for generating a fine pulse. A bandwidth of a fine pulse is determined by adjusting a difference in delay time between two adjacent pulses and a pulse is generated by selecting only one of a rising edge and a falling edge of an input pulse, and thus there is no need to remove an unnecessary batch of pulses afterwards and a transfer rate is enhanced.

Abstract: A programmable delay circuit block includes an input stage having a cascade input and a clock input, wherein the input stage passes a signal received at the cascade input or a signal received at the clock input. The programmable delay circuit block further may include a delay block configured to generate a delayed signal by applying a selected amount of delay to the signal passed from the input stage and a pulse generator configured to generate a pulse signal having a pulse width that depends upon the amount of delay. The programmable delay circuit block also includes an output stage having a cascade output and a clock output. The output stage is configured to pass an inverted version of the pulse signal or the delayed signal from the cascade output and pass the signal received at the clock input, the inverted version of the pulse signal, or the delayed signal from the clock output.

Abstract: An electronic device includes a first circuit, and a delay circuit electrically connected to the first circuit. The delay circuit includes a resistor, a capacitor, and a process, voltage or temperature (PVT) compensation circuit electrically connected to the capacitor.

Abstract: A controllable delay element includes a delay element to provide a variable delay from an input signal to an output signal. The variable delay can be controlled by a digital delay input. The delay element has a delay range that is controlled in response to a delay range input. The delay range of the delay element can be calibrated to a desired range of delays in response to a relative delay between a first timing reference and a second timing reference. A common timing reference is applied to a plurality of receivers and a strobe receiver. The delay through the strobe receiver is adjusted to measure the delay mismatches between the plurality of receivers. The mismatches are used to select a value for the delay through the strobe receiver.

Abstract: Apparatus including functional components of circuitry defined on a semiconductor chip, the functional components including a component having modifiable operating characteristics, a performance measuring circuit providing an output indicative of operating characteristics of the circuitry defined on the semiconductor chip during operation of the circuitry, and computer implemented software means for controlling a value for an operating characteristic of the component having modifiable operating characteristics in response to the output provided by the performance measuring circuit.

Abstract: A semiconductor device includes conducting lines of a first group and a second group arranged in parallel, a plurality of first internal elements respectively coupled to the conducting lines of the first group and the second group and a plurality of first contact pads arranged between and along the conducting lines of the first group and the second groups, wherein at least a part of the plurality of first contact pads are respectively coupled to control terminals of the plurality of first internal elements, and the part of the plurality of first internal elements receive a plurality of first control signals through corresponding control terminals, respectively.

Abstract: Apparatuses and methods for changing a signal path delay of a signal path responsive to changes in power provided to the signal path are disclosed. An example apparatus includes a signal path and signal path delay compensation circuit. The signal path includes a plurality of signal driver circuits coupled in series. The signal path delay compensation circuit includes an adjustable path delay circuit and a bias circuit. The adjustable path delay circuit is coupled to an output of a signal driver circuit of the plurality of signal driver circuits and includes a latch circuit. The bias circuit is configured to change a resistance to switching a latched signal level of the latch circuit responsive to changes in power provided to the signal path. Additional example apparatuses and methods are also disclosed.

Abstract: A method for controlling a temperature of an electronic device which includes a semiconductor chip is provided. The temperature control method includes measuring a temperature of a measurement point using the electronic device, comparing the temperature of the measurement point with a target temperature varying according to a period of time when the semiconductor chip operates using the electronic device, and decreasing a clock frequency of the semiconductor chip using the electronic device when the temperature of the measurement point is higher than the target temperature.

Abstract: An integrated circuit that equalizes delay across process corners. A delay equalizer circuit is used to adjust and maintain a relatively constant delay across different process corners. The delay equalizer circuit includes a process monitor and a delay compensator circuit coupled to the process monitor. The process monitor may output a compensating bias voltage for a pMOS transistor and a compensating bias voltage for an nMOS transistor. The compensating bias voltages may be used to regulate and maintain a relatively constant delay through the delay compensator circuit across varying process corners.

Abstract: A voltage controlled oscillator (VCO) includes a current controlled oscillator, a voltage-to-current converter, and a sensing circuit. The sensing circuit includes a delay unit, and the sensing circuit is configured to generate a plurality of compensation control signals in response to a time delay of the delay unit. The voltage-to-current converter is configured to generate a current signal in response to a VCO control signal and the plurality of compensation control signals. The current controlled oscillator is configured to generate an oscillating signal in response to the current signal.

Abstract: Aspects of the disclosure provide a circuit having a jittered clock generator. The jittered clock generator is configured to add jitter of a controlled characteristic to a first clock signal of a clock frequency to generate a second clock signal to be used by a transceiver for operating at a radio frequency. The jitter of the controlled characteristic adjusts a clock harmonic at the radio frequency of the transceiver.

Abstract: A transformer arrangement for signal transmission is provided, the transformer arrangement having at least one transformer with a primary coil and a secondary coil and a controller. The controller is configured in a magnetization phase to control a first current to flow through the primary coil to increase until a predefined criterion is fulfilled, wherein the magnetization phase is longer than a time constant of the primary coil of the at least one transformer. The controller is configured in a voltage application phase to apply a voltage to the at least one transformer so that a second current flows through the primary coil, wherein the second current has a polarity which changes during the voltage application phase compared with the first current, wherein the voltage application phase is shorter than two times the time constant of the primary coil of the at least one transformer.

Abstract: The present invention relates to a delay control circuit and technology in which the amount of delay can be regularly maintained although Process, Voltage, and Temperature (PVT) conditions are changed. The delay control circuit of the present invention includes a ZQ calibration unit configured to generate an impedance code into which a change of PVT conditions has been incorporated, a voltage trimming unit configured to control a level of a trimming voltage at a calibration node, and a delay compensation unit configured to compensate for the amount of delay by controlling an effective capacitance value of a capacitor.

Abstract: The temperature compensated timing signal generator comprises a crystal oscillator that generates a reference time signal, and a divider circuit that receives the reference time signal as input and outputs a coarse time unit signal, the coarse time unit signal having an actual frequency deviating from a desired frequency as a function of temperature of the crystal oscillator. The signal generator also includes a high frequency oscillator configured to generate an interpolation signal having a frequency greater than the frequency of the crystal oscillator. A finite state machine computes a deviation compensating signal as a function of temperature, the signal comprises an integer part representative of an integer number of pulses to be inhibited or injected in the divider circuit and a fractional part representative of how much the output of a new time unit signal pulse should further be delayed to compensate for any remaining deviation.

Abstract: The temperature compensated timing signal generator comprises a crystal oscillator that generates a reference time signal, and a divider circuit that receives the reference time signal as input and outputs a coarse time unit signal, the coarse time unit signal having an actual frequency deviating from a desired frequency as a function of temperature of the crystal oscillator. The signal generator also includes a high frequency oscillator that generates an interpolation signal having a frequency greater than the frequency of the crystal oscillator. A finite state machine computes a deviation compensating signal as a function of the temperature signal, the signal comprises an integer part representative of an integer number of pulses to be inhibited or injected in the divider circuit and a fractional part representative of how much the output of a new time unit signal pulse should further be delayed to compensate for any remaining deviation.

Abstract: A system may include a plurality of isolators to transfer data signals across an isolation barrier, one of the signals including a clock signal. A delay circuit may be included to receive the clock signal and provide a delayed clock signal that lags the clock signal by an amount representing a delay across the isolation barrier. The delayed clock signal may be delayed by a round trip propagation delay over the isolation barrier. The delayed clock signal may be used as a reference to read data sent over the isolation barrier.

Abstract: The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes an AVS database. The AVS database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The AVS database allows rapid voltage level decisions. The voltage levels stored in the AVS database may be initial, minimum, learned, populated, explored, backed out, temperature-based, and/or age-based voltage levels according to disclosed embodiments to further avoid or reduce voltage margin. An AVS module may be a software-based module that consults the AVS database to make voltage level decisions. Providing the AVS module as a software-based module may allow flexibility in configuring the AVS module and/or the AVS database.