Abstract: A timing generator includes a reference signal generating unit for generating a reference signal of a predetermined frequency, a variable delay circuit unit for outputting the timing signal which results from delaying the reference signal by a predetermined time, and a delay amount measuring unit for measuring a delay amount of the variable delay circuit unit, whereby the timing generator controls the delay amount of the variable delay circuit unit based on the delay amount measured by the delay amount measuring unit. Since the frequency of the reference signal is continuously modulated within a very small frequency range, the delay amount measuring unit can measure the delay amount of the variable delay circuit unit highly accurately. In addition, since the delay amount of the variable delay circuit unit can be controlled on the basis of the measured delay amount, it is possible to generate the accurately delayed timing signal.

Abstract: Methods and systems for controlling delay relatively independent of process, supply-voltage, and/or temperature (“PVT”) variations include sensing an output signal after a number of inverters and activating different numbers of transistors and/or adjusting strength of transistors in a delay path to compensate for PVT variations. In an embodiment, a waveform is received, delayed, and output to an output terminal using at least one relatively low-power device. Supplemental output power is provided by at least one relatively high-power device until the output waveform exceeds a threshold.

Abstract: A system, method and medium may delay a strobe signal based upon a delay base and a delay adjustment to reduce effects of process variations and/or environmental changes.

Abstract: The digital programmable delay scheme with automatic calibration is an alternative to PLLs, DLLs, fixed delay cells and other methods of delay. The method and circuit sets a delay in a programmable delay cell in an oscillator circuit and uses a reference clock to calibrate the oscillator clock frequency. The programmable delay, once set, may then be used to determine a desired delay for a signal that passes through the programmable delay cell as well as another portion of the oscillator circuit. The circuit preferably uses two counters that are controlled by calibration and control logic in which one counter is clocked by the reference clock and the other is clocked by the oscillator circuit clock. After a predetermined time, the calibration and control logic compares the two count values and determines if the programmable delay cell of the oscillator circuit needs to be adjusted.

Abstract: The present invention is directed to an oil burner system having an electric cord set coupled between a controller and a valve associated with a pump. The electric cord set is operable to activate a solenoid valve associated with the pump for delivery of fuel oil to a nozzle of the burner. The electric cord set comprises a voltage or temperature independent timer circuit operable to activate the solenoid valve a predetermined period of time after a call for ignition signal is generated by the controller, wherein the predetermined time period is substantially constant with respect to variations in line voltage or in an ambient temperature in which the oil burner system resides.

Abstract: A circuit includes an input for receiving an input signal, a delay chain connected to the input for delaying the input signal, and a circuit configuration connected to the delay chain downstream of the input, the circuit configuration for supplying a voltage to the delay chain in response to the input signal.

Abstract: A phase locked loop that may use UP and/or DN signals having programmable active state durations to control the speed of a clock signal.

Abstract: A correction circuit for generating a control signal for correcting a characteristic change of a first transistor includes a control signal adjusting section including a constant voltage reduction element for determining either one of a maximum voltage and a minimum voltage of the control signal and a second transistor for determining a characteristic of the control signal, a gate electrode of the second transistor receiving a prescribed voltage; and a resistor section including two types of resistor elements having resistance values of different temperature dependency characteristics from each other, the resistor elements being connected in series. The constant voltage reduction element, the second transistor, and the resistor section are connected in series between a supply terminal and a ground terminal. The control signal is output from a connection point between the control signal adjusting section and the resistor section.

Abstract: A delay compensation circuit that determines the effects of process, voltage, and temperature (PVT) conditions of a chip by measuring the effective delay time of delay components inside the chip. The delay compensation circuit includes a plurality of sampler modules, each of which receives a delayed clock signal from one of a series of delay cells within a tapped delay circuit. The delay compensation circuit generates an output value based on the total number of sampling modules that lock into a fixed input signal using the delayed clock signals. Since the delay time of each delay cell changes based on variations of PVT conditions, the output values generated by the delay compensation circuit are determinate of PVT conditions in the chip. These output values can be used to design components to compensate for variances in PVT conditions or to control a variable delay component based on detected PVT conditions.

Abstract: Methods and systems for controlling delay relatively independent of process, supply-voltage, and/or temperature (“PVT”) variations include sensing an output signal after a number of inverters and activating different numbers of transistors and/or adjusting strength of transistors in a delay path to compensate for PVT variations. In an embodiment, a waveform is received, delayed, and output to an output terminal using at least one relatively low-power device. Supplemental output power is provided by at least one relatively high-power device until the output waveform exceeds a threshold.

Abstract: Disclosed is a timing control circuit for semiconductor device capable of controlling timing of internal signal after packaging by using a fuse. The disclosed comprises: a signal delay unit comprising delay elements and for delaying externally received signal for a predetermined time and outputting the result; and a fuse unit capable of determining whether to enable or disable after packaging the semiconductor device and then, determining whether to delay the signal by the delay element or not according to whether it is enabled or not, thereby controlling delay time of signal by the signal delay unit.

Abstract: In a switched capacitor filter circuit, a switching transistor is connected to an operational amplifier for input of a switching control signal to the operational amplifier. A noise compensation transistor is provided between the switching transistor and the operational amplifier. The drain and the source of the noise compensation transistor are connected to each other. The noise compensation transistor is applied with an inverted signal of the switching signal, and generates feedthrough noise of the polarity inverted from that generated by the switching transistor in order to cancel the feedthrough noise.

Abstract: A CMOS buffer circuit includes (1) a first CMOS inverter having a first p-channel MOSFET, which has a first threshold value that becomes smaller as the temperature rises and which is rendered ON when a digital signal exceeds the first threshold value, and a first n-channel MOSFET, having a second threshold value that becomes smaller as the temperature rises, that is rendered ON, complementary to the first p-channel MOSFET, when a digital signal exceeds the second threshold value; and (2) a second CMOS inverter having a second p-channel MOSFET, which has a third threshold value that becomes smaller as the temperature rises and which is rendered ON when the first inverted signal exceeds the third threshold value, and a second n-channel MOSFET, having a fourth threshold value that becomes smaller as the temperature rises, that is rendered ON, complementary to the second p-channel MOSFET, when the first inverted signal exceeds the fourth threshold value.

Abstract: A programmable compensated delay for a double data rate (DDR) synchronous dynamic random access memory (SDRAM) interface is provided. A programmable compensated delay apparatus includes a reference delay calibration circuit for providing a measured number of delay elements in one cycle. A programmable delay register provides a desired delay value. A conversion logic is coupled to the reference delay calibration circuit and the programmable delay register for receiving both the measured number of delay elements in one cycle and the desired delay value. The conversion logic provides a number of required delay elements. A delay circuit is coupled to the conversion logic for receiving the number of required delay elements and providing the desired delay. A SDRAM control logic provides a refresh start signal to the reference delay calibration circuit for updating the delay circuit during each DRAM refresh. The DQS clock strobe on the DDR SDRAM is applied to the delay circuit and is delayed by the desired delay.

Abstract: An electronic circuit according to this invention includes a first delay compensation circuit which receives a first power supply voltage and a first signal and outputs a first output signal delayed by a first predetermined time, a second delay compensation circuit which receives a second power supply voltage and the first signal and outputs a second output signal delayed by a second predetermined time, a first logic circuit which receives the first power supply voltage and the second output signal output from the second delay compensation circuit and outputs a first operation result by performing first logic operation, and a second logic circuit which receives the second power supply voltage and the first output signal output from the first delay compensation circuit and outputs a second operation result by performing second logic operation.

Abstract: An active termination technique for reducing the propagation delay of a signal across a transmission line is presented. In accordance with a preferred embodiment of the invention, repeaters along a transmission line are paired with active termination circuits in very close proximity to the repeater in order to prevent signal reflections caused by the repeaters. The repeaters and associated active termination circuits are implemented with at least one PFET and at least one NFET, each having the same transistor gate lengths. The PFETs and the NFETs in the repeater and associated termination are ratioed to vary similarly over process/voltage/temperature variation.

Abstract: An inverter output circuit comprises first though third inverters connected in series. The low-potential output of the first inverter has an offset level. The input threshold voltage of the second inverter is set up at a lower level than the low-level offset potential of the first inverter as the level of supply voltage Vdd falls below a predetermined reference level. Thus, the third inverter is fixed to a predetermined condition if the supply voltage drops below the reference voltage, thereby preventing erratic operations of a load connected to the inverter output circuit caused by, for example, a power shut down and a brownout.

Abstract: A delay circuit includes a delay part delaying a signal by a delay time which can be varied based on a control current, and a control current adjustment circuit adjusting the control current so that the delay time changes linearly based on a variation in a resistance value.

Abstract: A device and method that adjust data due to temperature variations is disclosed. The data is captured in a multi-stage delay line. A first controller parses the data and identifies an Edge1 value and an Edge2 value for bits in the delay line. The edge values are used to generate signals that set a Multiplexer 1 (MUX1) and a Multiplexer 2 (MUX2) to select bits from the delay line. A second controller processes an edge sample from bits in the delay line to determine if the data has shifted in the delay line relative to the current multiplexer settings. An edge sample is a snapshot of the delay line values. The new edge values generated by the second controller are selectively filtered and integrated with initial edge values to generate new settings for the MUX1 and MUX2.

Abstract: Methods and systems for controlling delay relatively independent of process, supply-voltage, and/or temperature (“PVT”) variations include sensing an output signal after a number of inverters and activating different numbers of transistors and/or adjusting strength of transistors in a delay path to compensate for PVT variations. In an embodiment, a waveform is received, delayed, and output to an output terminal using at least one relatively low-power device. Supplemental output power is provided by at least one relatively high-power device until the output waveform exceeds a threshold.

Abstract: A delay circuit is provided including first and second resistive elements electrically coupled in series having first and second resistance values. The first resistance value varies in proportion to temperature and the second resistance value varies in inverse proportion to temperature.

Abstract: A circuit for providing substantially a constant delay of an electrical signal that compensates for voltage, temperature and process variations includes an inverter. A delay cell has an output that is coupled to the inverter. The delay cell includes a charge transistor coupled to a capacitor. A control circuit has an output that is coupled to a gate of the charge transistor. The output has a voltage that is proportional to a trip voltage of the inverter. The delay cell also has a discharge transistor. The control circuit contains a second output that is coupled to a gate of the discharge transistor. The second output has a voltage that is also proportional to the trip voltage of the inverter.

Abstract: A delay circuit includes a first inverter connected to a supply voltage, and has an input for receiving an input signal. A delay regulating transistor is connected between the first inverter and a first voltage reference, and has a control terminal for receiving a biasing voltage. A capacitor is connected between an output of the first inverter and the first voltage reference. A second inverter is connected to the output of the first inverter for outputting a delayed output signal. An auxiliary current path is in parallel to the delay regulating transistor for allowing a portion of a discharge current from the capacitor to flow therethrough. The portion of the discharge current is proportional to the supply voltage. The auxiliary current path includes a diode connected to the first inverter, and a second transistor connected between the diode and the first voltage reference. The second transistor has a control terminal for receiving the biasing voltage.

Abstract: In one embodiment, a digital circuit element has a propagation delay that is substantially constant over a range of supply voltages applied to the digital circuit element. In another embodiment, a digital circuit element may include an input node, an output node, and at least one gate coupling the input node and the output node. A plurality of possible voltage transition curves may be associated with a corresponding change of a first voltage at the input node over time, each voltage transition curve being determined by a corresponding supply voltage and the curves intersecting within a relatively narrow range of voltages. The gate may be operable to change a second voltage at the output node in response to the first voltage reaching a threshold voltage of the gate, and the threshold voltage may be set within the relatively narrow range of voltages in which the voltage transition curves intersect in order to reduce the dependence of the propagation delay on the supply voltage.

Abstract: A time delay circuit including a first transistor having a gate, a drain, a source, and a channel between the source and the drain. The input voltage is applied between the gate and drain and the output is taken between the source and drain. The output voltage follows the gate voltage, and the first transistor gate voltage is substantially constant. The time delay circuit also includes a delay element. The output voltage of the first transistor biases the delay element.

Abstract: Methods and systems for controlling delay relatively independent of process, supply-voltage, and/or temperature (“PVT”) variations include sensing an output signal after a number of inverters and activating different numbers of transistors and/or adjusting strength of transistors in a delay path to compensate for PVT variations.

Abstract: An inverter type delay circuit, voltage-controlled oscillation circuit, and voltage-controlled delay circuit capable of realizing simplification of circuit configuration, reduction of an effect of power source noise, and reduction of jitter, wherein a delay circuit, voltage-controlled oscillation circuit, and voltage-controlled delay circuit comprised of a plurality of delay stages controlled in drive current in accordance with a bias voltage or a control voltage and determined in delay time by the drive current, adding a change of a power source voltage to the above bias voltage or control voltage by a predetermined ratio and supplying a result of the addition to the above delay stages to suppress the power source voltage dependencies of the delay times of the delay stages, or connecting by a predetermined ratio a plurality of delay stages having different power source voltage dependencies, for example, power source voltage dependencies of opposite delay times, to suppress the power source voltage dependenci

Abstract: A digital frequency doubler circuit employs a stable reference clock signal, delayed by a reference delay line, to obtain information related to delay characteristics of a matching input delay line. An input clock signal is delayed by the input delay line, which provides a plurality of variously delayed input clock signals based upon the input clock signal. The reference delay line provides a plurality of variously delayed reference clock signals based upon the stable reference clock signal; the delayed reference clock signals convey information related to the operating characteristics of both delay lines. In response to such information, one of the delayed input clock signals can be selected as a delayed clock output. The reference and input delay lines are configured such that the delay circuit consistently generates a delayed clock output having an actual delay that falls within a specified range of delay.

Abstract: A digital delay circuit employs a stable reference clock signal, delayed by a reference delay line, to obtain information related to delay characteristics of a matching input delay line. An input clock signal is delayed by the input delay line, which provides a plurality of variously delayed input clock signals based upon the input clock signal. The reference delay line provides a plurality of variously delayed reference clock signals based upon the stable reference clock signal; the delayed reference clock signals convey information related to the operating characteristics of both delay lines. In response to such information, one of the delayed input clock signals can be selected as a delayed clock output. The reference and input delay lines are configured such that the delay circuit consistently generates a delayed clock output having an actual delay that falls within a specified range of delay.

Abstract: A precision signal delay apparatus and method for introducing time delay to a signal. Precision delay is introduced by a pair of delay locked loops (DLLs) connected in series each with selectable delay (i.e., a Vernier-type circuit). Nonuniformity in the precision delay is compensated with a delay compensation circuit. The apparatus and method may be used for phase shifting, data delay, precision pulse width modulation, and precision time windowing.

Abstract: A method as well as a bias generator and associated output circuit architecture (300) that protects output skew voltage capabilities for the associated output circuit (304) to a greater extent than that achievable using presently known circuit architectures and techniques. A voltage level detector (306) comprising a differential-pair circuit detects bias voltage levels and provides a signal (308) to skew adjusting assist devices (310, 312) when the bias voltage levels get close to a “choking off” voltage level. The signal (308) turns on the skew adjusting assist devices (310, 312) to assist the skew adjusting devices (102, 104).

Abstract: A low voltage, low power versatile and compact delay circuit for CMOS integrated circuits. The biasing circuit and comparator of the delay circuit are implemented with a relatively few simple transistor stages. This approach makes the circuit compact and allows for operation at very low supply voltages (e.g., 1.5 volts). The time delay of the delay circuit is made to depend only on passive resistive and capacitive components. The time delay is thus insensitive to fluctuations in the supply voltage, as well as fluctuations in temperature. This configuration is particularly advantageous in circuits where several timing elements need to track with one another, as they can all be formed with resistors and capacitors of the same construction. The design also makes the circuit insensitive to process parameters, as well as later environmental effects due to operating temperature, circuit aging, and the like.

Abstract: An apparatus for and method of generating a signal for equalizing propagation delay among parts of a transceiver are disclosed. The parts each have a plurality of channels, and each channel is configured to receive the signal. The apparatus includes a master circuit and a dummy channel circuit. The master circuit is configured to receive and lock to a reference clock signal, and in accordance therewith generate a reference delay signal and an adjusted clock signal. The dummy channel circuit is configured to receive the adjusted clock signal, the reference delay signal and a dummy data signal, and in accordance therewith generate an intermediate data signal, the dummy data signal and one or more control signals. The control signals correspond to a delay between the adjusted clock signal and the intermediate data signal. In this manner a uniform delay may be provided to all parts and channels.

Abstract: A delay circuit having a constant period of delay time independent of changes in operations, temperature and voltage includes a current source for generating a constant current and having PMOS transistors of which gates are commonly connected, wherein the constant current is controlled by sizes of the PMOS transistors; and a unit delay circuit including a CMOS inverter having PMOS and NMOS transistors, wherein non-adjacent PMOS and NMOS transistors are controlled to charge and discharge current when a constant level of the constant current is transmitted from the current source and other adjacent PMOS and NMOS transistors are switched to connect or disconnect a current path through which the current is charged or discharged.

Abstract: Circuit for generating an inverse signal of a digital signal with minimal delay difference between the inverse signal and the digital signal. Two inverter circuits (6, 8; 7, 9) have been connected in series. The output signal of the second inverter circuit (7, 9) is the digital signal. An input signal for the first inverter circuit (6, 8) is supplied to a pass-through circuit (13, 14) with threshold action. The signal present between the first (6, 8) and the second (7, 9) inverter circuit is supplied to a control input (16) of the pass-through circuit with threshold action. The signal which is also present between the first (6, 8) and the second (7, 9) inverters appears with some delay at the output (17) of the pass-through circuit with threshold action, which signal is the inverse of the digital signal and at the same time constitutes the output signal of the pass through circuit (13, 14) with threshold action.

Abstract: In an integrated circuit incorporating a series of sequential cells (SEQ(1)-SEQ(7)) implementing a shift function, clock skew problems are avoided by interconnecting the cells in order starting with the cell (SEQ(3)) having greatest clock latency and ending with the cell (SEQ(7)) having smallest clock latency.

Abstract: A time delay circuit including a first transistor having a gate, a drain, a source, and a channel between the source and the drain. The input voltage is applied between the gate and drain and the output is taken between the source and drain. The output voltage follows the gate voltage, and the first transistor gate voltage is substantially constant.

Abstract: The supply voltage to which a delay circuit's buffer stages are coupled is adjusted in response to changes in temperature according to a predetermined relationship to maintain a substantially constant buffer stage gate delay over temperature variations. Decreasing gate delays resulting from decreases in temperature are offset by decreasing the supply voltage, which in turn increases gate delays. Conversely, increasing gate delays resulting from increases in temperature are offset by increasing the supply voltage, which in turn decreases gate delays. In some embodiments, a control circuit is connected to the reference voltage circuit that supplies VCC to the delay circuit, and adjusts VCC in response to temperature to maintain substantially constant gate delay over temperature. In one embodiment, the control circuit includes a microprocessor and a look-up table containing desired supply voltage versus temperature mappings.

Abstract: A voltage-compensated, constant delay clock buffer for a chip clock distribution circuit employs a variable gain circuit to dynamically control the delay through the first inverter stage. In the presence of no voltage rail collapse the first stage gain is set high which results in a nominal delay through the first stage. As voltage rail collapse occurs local to the clock buffer circuit, the gain on the first stage is reduced to yield a smaller than nominal delay through the first stage in such a way as to compensate for the increased delay in the subsequent stage or stages. The control circuit is responsive to a first voltage rail and a second voltage rail to provide dynamic control of the delay through the first inverter stage. The circuit can compensate the circuit to handle a plurality of second inverter stages with the control circuit adjusting the delay of said first inverter stage, and with the control circuit remaining responsive to a first voltage rail and a second voltage rail.

Abstract: A delay circuit having a constant period of delay time independent of changes in operations, temperature and voltage includes a current source for generating a constant current and having PMOS transistors of which gates are commonly connected, wherein the constant current is controlled by sizes of the PMOS transistors; and a unit delay circuit including a CMOS inverter having PMOS and NMOS transistors, wherein non-adjacent PMOS and NMOS transistors are controlled to charge and discharge current when a constant level of the constant current is transmitted from the current source and other adjacent PMOS and NMOS transistors are switched to connect or disconnect a current path through which the current is charged or discharged.

Abstract: In one embodiment, a digital circuit element has a propagation delay that is substantially constant over a range of supply voltages applied to the digital circuit element. In another embodiment, a digital circuit element may include an input node, an output node, and at least one gate coupling the input node and the output node. A plurality of possible voltage transition curves may be associated with a corresponding change of a first voltage at the input node over time, each voltage transition curve being determined by a corresponding supply voltage and the curves intersecting within a relatively narrow range of voltages. The gate may be operable to change a second voltage at the output node in response to the first voltage reaching a threshold voltage of the gate, and the threshold voltage may be set within the relatively narrow range of voltages in which the voltage transition curves intersect in order to reduce the dependence of the propagation delay on the supply voltage.

Abstract: A CMOS logic circuit is supplied with a power supply potential via current control gate transistors, and has current flowing towards ground via current control transistors. The gate potential of each current control transistor is controlled by a current control circuit. When leakage current is generated in the CMOS logic circuit, self bias to suppress leakage current is generated in the transistor forming a logic gate due to a voltage drop by the current control transistor.

Abstract: A semiconductor device, comprising a stabilized timing circuit for regulating the phase of each of first and second clocks complementary with each other input from an external source and generating each of first and second internal clocks delayed by a predetermined phase, is disclosed. The stabilized timing circuit includes a clock input circuit unit for receiving the first and second clocks complementary with each other, and a dummy input circuit unit for receiving a first feedback clock and a second feedback clock complementary with each other and having the delay time equivalent to the delay time of the first and second clocks in the clock input circuit unit.

Abstract: The delay time of a variable delay circuit is set to a desired value by: sequentially applying a plurality of clocks of different frequencies to a variable delay circuit; finding, for each clock, the amount of change in delay time with respect to change in a delay time selection signal, which is a signal for setting the delay time of the variable delay circuit; finding a linear coefficient of the characteristic of the delay time of the variable delay circuit with respect to the delay time selection signal from the difference in the amounts of change with respect to the difference in clock frequencies; finding an amount of offset with respect to the delay time selection signal that pertains to the variable delay circuit from the amounts of change and frequencies of the clocks; and finding the delay time selection signal from the linear coefficient and the difference between the desired delay time and the offset amount.

Abstract: A delay locked loop circuit prevents occurrence of jitter and has a small chip area when it is realized as a semiconductor integrated circuit. The delay locked loop circuit includes a phase shifter, a compensation delay unit, a component coefficient extractor, a phase inverter, first and second component signal generators, and a phase mixer. In this structure, the delay locked loop circuit generates an output clock signal, the phase of which leads that of an externally-applied input clock signal by a predetermined delay time to compensate for a delay time which inevitably occurs in semiconductor integrated circuits. The phase shifter generates a first clock signal in phase with the input clock signal and a second clock signal having a 90° phase difference with respect to the first clock signal. The compensation delay unit outputs a third clock signal, the phase of which lags that of the input clock signal by a predetermined delay time.

Abstract: A delay circuit for a ring oscillator includes a first electric potential line, a pair of output lines, a pair of two first transistors arranged between the first electric potential line and the pair of output lines, respectively, a second electric potential line, and a pair of two second transistors arranged between the second electric potential line and the pair of output lines, respectively. Respective gates of the first transistors are connected to the pair of output lines, respectively, the first transistors, and the second transistors are connected to each other center-symmetrically, and the output lines are connected to a third electric potential line. Such a circuit can easily realize a differential gain of more than or equal to 1 and an in-phase gain of less than or equal to 1.

Abstract: A first circuit having deteriorated duty is connected to a second circuit having the same circuit arrangement and the same layout as that of the first circuit. The first and second circuits are connected to each other by means of an inversion logic. The difference between a rising time tr and a falling time tf generated in each circuit block of the first circuit is canceled by the circuit block of the second circuit corresponding to that of the first circuit. Accordingly, duty deterioration derived from types of blocks, branching and wiring capacity is prevented without the influence of process variation.

Abstract: A semiconductor integrated circuit chip is divided into a plurality of regions each incorporating a performance variation compensating circuit. The performance variation compensating circuit supplies a power supply to a MOS FET in the region to compensate for threshold voltage variations.

Abstract: A SCSI bus expander provides signal conditioning for transmitted data pulses that is particular to a negotiated data transfer rate. The expander monitors the bus arbitration to determine the devices involved in the transfer, and thereafter monitors the data transfer rate negotiations to determine the transfer rate to be used by that particular combination of devices. An indication of the transfer rate is stored in a memory device at an address determined by the device IDs. The transfer rate is then used to select tap values for tap lines that modify the pulse width and/or a propagation delay of the pulse, so as to correct for signal degradation and to align it better relative to other signals during data transmission. The specific tap values may vary for the different combinations of transmitting and receiving devices involved in the transfer, since the manner in which the pulse characteristics should be modified may be different for different transmission rates.

Abstract: A data transmission circuit is provided for compensating for a difference between data transmission speed occurring at start and end portions of a data line. The circuit minimizes a time delay caused by resistance/capacitance loading of the data line through which data is transmitted, thereby improving data transmission speed. The data transmission circuit of the present invention includes a compensation circuit to compensate for the time delay between the data signals at the start and end portions of the data line. The compensation circuit is adapted to amplify and rapidly develop a data signal at the end portion of the data line through which a data signal is enabled from its high state to its low state and transmitted as a data signal at the end portion of the data line.