Abstract: A spread-spectrum circuit including an inverter, a current source, a control unit and a shaping circuit is provided. An input terminal of the inverter receives an original clock signal. The current source is coupled to a current transmission terminal of the inverter. The control unit includes a control circuit, and changes the current magnitude of the current source according to the original clock signal to control the charging/discharging speed of an output terminal of the inverter, so that the output terminal outputs a voltage signal. The shaping circuit shapes the voltage signal into a spread-spectrum clock signal.

Abstract: A semiconductor integrated circuit includes a first node through which an input signal passes and an adjustment block including at least one delay unit electrically connected to the first node. The semiconductor integrated circuit also includes a correction block configured to generate a control signal which controls whether to activate a delay unit.

Abstract: A device for detecting an approach or a touch related to at least one sensor element, in particular in an electrical appliance, the device comprising an input side and an output side, between which a first signal path with a first input and a first output and a second signal path with a second input and a second output are arranged, wherein the first signal path comprises a delay device with a delay, the delay device configured to delay a digital first input signal at the first input into a digital first output signal at the first output, wherein the delay is dependent on a capacitance value resulting from the approach or the touch related to the sensor element, and wherein the second signal path comprises an XOR-element, which is configured to generate an edge in a digital second output signal at the second output, when the digital first output signal outputted by the delay device exhibits an edge.

Abstract: Methods and apparatuses for optimizing switching delay in integrated circuits are described. Combinational logic gates are modified with precharge circuitry and instantiated in order to reduce switching transitions of circuit elements in a signal path.

Abstract: A method of controlling a clock signal with a print controller is provided. In response to receiving an external signal, the print controller determines the number of cycles of a clock signal generated by a ring oscillator of the print controller during a predetermined number of cycles of the external signal or the number of cycles of the external signal during a predetermined number of cycles of the clock signal and outputs the determined number of cycles to an external circuit. In response to receiving a trim value from clock trim circuitry of the print controller which trims the frequency of the clock signal based on the determined number of cycles from the external circuit, the trim value is stored in memory of the print controller. The clock trim circuitry is controlled to trim the frequency of the clock signal generated by the ring oscillator using the trim value.

Abstract: An internal clock signal driver circuit includes a delay block that delays a rising clock signal and a falling clock signal, and outputs a delayed rising clock signal and a delayed falling clock signal, a rising DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed rising clock signal, and outputs a rising DLL clock signal, and a falling DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed falling clock signal, and outputs a falling DLL clock signal.

Abstract: A pad driving circuit includes an output control circuit, a voltage pump circuit, a first buffer series, and a second buffer series. The output control circuit controls whether a pad circuit can pass an input signal, in which the output control circuit enables the pad circuit to output the input signal when an enable signal is asserted. The voltage pump circuit generates a negative supply voltage having voltage less than a zero volt. The first buffer series, electrically connected between the output control circuit and the pad circuit, drives the pad circuit with a positive supply voltage and the negative supply voltage from the voltage pump circuit. The second buffer series drives the pad circuit with a ground voltage and the positive supply voltage.

Abstract: A delay circuit receives a data input having an input transition and that generates a data output having an output transition. The delay circuit is powered by a voltage source having a voltage. A first delay element is configured to generate a first data signal with a first edge that has a relatively constant delay relative to the input transition irrespective of the voltage of the voltage source. A second delay element is configured to generate a second data signal with a second edge that has a delay relative to the input transition as a function of the voltage of the voltage source. A selection element causes the output transition at the data output to correspond to a latest selected one of the first edge and the second edge. The delay circuit may be employed in a pulse generating circuit.

Abstract: A semiconductor device comprising timer logic for generating a first modulated waveform signal, and delay logic, operably coupled to the timer logic and arranged to provide a first delay in a rising edge of the first modulated waveform signal generated by the timer logic; and provide a second delay in a falling edge of the first modulated waveform generated by the timer logic. The first delay and second delay of the first modulated waveform forms a second, refined modulated waveform signal that comprises a higher frequency resolution than a frequency resolution of the first modulated waveform signal.

Abstract: A delay circuit includes a ring oscillator and a control circuit. The control circuit includes an edge detector that outputs a first control signal in response to a rising edge or a falling edge of an input signal, and a counter that counts the number of pulses of an output pulse signal output from the ring oscillator and outputs a second control signal upon reaching a predetermined count number. The control circuit performs control to make the ring oscillator oscillate in response to the first control signal and to output the input signal in response to the second control signal.

Abstract: For differential signal transmission (especially in high speed applications), intra-pair skew between paths carrying complementary portions of a differential signal can significantly affect performance. Conventional de-skew circuits employ simple filters (i.e., low-pass filters) to operate as delay elements to account for skew; however, these filters can distort the differential signal, which can also adverse affect performance. Here, an all-pass, adjustable delay element and de-skew circuit are provided to allow for compensation of skew without degrading the differential signal as conventional circuit do and, thus, having better performance characteristics.

Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal ?(0) to ?(2i?1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal ?(0) to j(2i?1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal ?(0) to ?(2i?1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

Abstract: A circuit is provided that includes an input for a clock signal, a random event generator for outputting a random signal, in particular random numbers, a settable delay device that is connected to the input for the clock signal and is connected to the random event generator for the purpose of setting a delay of an edge of the clock signal (clk) by means of the random signal.

Abstract: There is provided a jitter injection apparatus that generates an output signal having an injected jitter. The jitter injection apparatus includes a first oscillator that generates a first periodic signal, a second oscillator that generates a second periodic signal having a period different from that of the first periodic signal, and a switching section that switches which of the first periodic signal and the second periodic signal is output at every predetermined timing and outputs the switched periodic signal as the output signal.

Abstract: A circuit for improving the control of a change in state of a signal in an electronic device between a first state and a second state, wherein a first change in state occurs when the state changes from the second state to the first state and a second change in state occurs when the state changes from the first state to the second state and wherein the first and second changes in state have associated therewith a first and a second time delay over which the or each change in state occurs, characterized in that said circuit comprises a determining unit for measuring the first time delay and a calculator for calculating a common delay to replace one or more of the first and second delays to thereby improve the control of the change in state of the signal

Abstract: A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a first logic element having a controllable inertial delay and a second logic element coupled to an output of the first logic element. A first controller provides a control voltage VcR to each first logic element to control a rise time of the first logic element to be equal to T. A second controller provides a control voltage VcF to each first logic element to control a fall time of the first logic element to be equal to T.

Abstract: A serial interface interacting with a transmission pad system circuitry wherein a differential impedance is reckoned across the system voltage source, includes a scheme for controlling transmitter rise-fall transitions (to selectively speed up or slow down transitions) without requiring additional timing controls or affecting reflection coefficient of the transmitter port. The scheme uses at least one pre-charged capacitor, e.g., PMOS capacitor, interacting with the transmitter pad and connected through resistances or otherwise across the differential impedance with a switch. A modified scheme uses first and second parallely connected PMOS capacitors connectable with the transmission pad by switches, which may be NMOS switches. The scheme may be used in a MIPI D-PHY compliant DSI transmitter operating at, for e.g. 800 Mbps, and low signal common-modes. The scheme controls signal transition times of high speed circuitry including transmitters and uses a DATA signal which is already available to the circuitry.

Abstract: A delay circuit includes a ring oscillator and a control circuit. The control circuit includes an edge detector that outputs a first control signal in response to a rising edge or a falling edge of an input signal, and a counter that counts the number of pulses of an output pulse signal output from the ring oscillator and outputs a second control signal upon reaching a predetermined count number. The control circuit performs control to make the ring oscillator oscillate in response to the first control signal and to output the input signal in response to the second control signal.

Abstract: A delay circuit that includes a logic gate through which an input signal passes, a capacitor configured to be charged and discharged at an output terminal of the logic gate and delaying the input signal, and a mirroring unit configured to constantly maintain current output by the logic gate by mirroring current output by a constant current source.

Abstract: Methods and apparatuses for optimizing switching delay in integrated circuits are described. Combinational logic gates are modified with precharge circuitry and instantiated in order to reduce switching transitions of circuit elements in a signal path.

Abstract: The present disclosure is an apparatus for generating a decreasing delay with increasing input voltage to a predetermined voltage value at which point the delay may remain constant. The apparatus may include a circuit comprising a voltage regulator receiving an input voltage and two paths of inverters. At least two paths of inverters may be coupled to an input signal, the input signal may be low voltage (e.g. 0) or high voltage (e.g. 1). A first path may be referenced to a reference voltage while the second path may be referenced to the input voltage. The apparatus may include logic gates for receiving the output of each of the first path of inverters and the output of the second path of inverters to generate a desired output. As the input voltage increases, delay of the apparatus may decrease until the input voltage is approximately the same voltage as the reference voltage, at which the delay may remain constant.

Abstract: A digital controller for dc-dc switching converters can operate under light load conditions. The controller can be suitable for the use in switch-mode power supplies providing regulated output voltage for handheld devices and other low-power electronics. To create long time intervals, compared to the propagation time of digital logic a DPFM/DPAM can use a ring oscillator with two sets of delay cells and two signals racing around the ring.

Abstract: A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.

Abstract: Aspects of the disclosure provide a fine tunable digital delay circuit that can be applied in a high frequency digital circuit. Further, the digital delay circuit can utilize a level restoring technique to enable a wide tunable delay range. The delay circuit can include a delay element configured to receive an input signal at an input node and output a controlled signal having a controlled rise time and a controlled fall time at a controlled node, a first plurality of transistors configured to bias a supply node of the delay element to govern the controlled rise time of the controlled signal, and a second plurality of transistors configured to bias a ground node of the delay element to govern the controlled fall time of the controlled signal. The delay circuit can further include a restoring circuit configured to charge or discharge the controlled node.

Abstract: A delay circuit includes: a current control circuit which has n (n is 1 or larger natural number) control pins and a first output line, and is capable of controlling current outputted from the first output line in response to n control signals inputted to the corresponding n control pins; a current mirror circuit connected with the first output line to produce current mirror current from the current and output the current mirror current from a second output line; a first active element having a gate pin and an input pin, the gate pin is connected with the second output line, and the input pin is connected with the first voltage line; a second active element having a gate pin and an input pin, the gate pin is connected with the first output line, and the input pin is connected with the second voltage line; and an inverter circuit having third and fourth active elements connected in series between an output pin of the first active element and an output pin of the second active element.

Abstract: A ring oscillator includes a first logic block having a first input connected to a specific point along a delay path, a first output and a second output, and a second logic block having a first input connected to the first output of the first logic block, a second input connected to the second output of the first logic block, a third input connected to the end of the delay path, and a first output connected to the beginning of the delay path. The first logic block is arranged to alternately switch its first output and second output from logical HIGH to logical LOW, and vice versa, every time a rising edge is input into its first input. The second logic block is arranged to alternately select its first input and its second input every time a rising edge is input into its third input.

Abstract: An internal clock signal driver circuit includes a delay block that delays a rising clock signal and a falling clock signal, and outputs a delayed rising clock signal and a delayed falling clock signal, a rising DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed rising clock signal, and outputs a rising DLL clock signal, and a falling DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed falling clock signal, and outputs a falling DLL clock signal.

Abstract: A phase shift circuit that includes two, rather than four, delay chains and corresponding selectors is described. This provides a significant area savings and reduces the intrinsic delay of the phase shift circuit, which is particularly beneficial for embodiments in which there is no intrinsic delay matching. In one implementation, the phase shift circuit includes a first delay circuit and a matching delay circuit. The first delay circuit provides a first delay that includes a first intrinsic delay and a first intentional delay. The delay matching circuit provides a matching delay that matches the first intrinsic delay. In one implementation, the phase shift circuit also includes a second delay circuit to provide a second delay that includes a second intrinsic delay and second intentional delay, where the second intrinsic delay matches the first intrinsic delay and the second intentional delay is half as long as the first intentional delay.

Abstract: A clock modulation circuit includes a modulation block that receives a fixed clock generated from a reference clock and buffers the fixed clock so as to generate a modulated clock. A correction unit is provided in the modulation block to correct the duty ratio of the modulated clock.

Abstract: Embodiments of the present invention relate to a method and device operable to determine a duty cycle offset of a periodic signal and correct the periodic signal to a desired duty cycle. Embodiment of the present invention may include a ring oscillator circuit. The ring oscillator includes an odd number of ordered inverting elements. One or more of the inverting elements may be an inverting memory element. Each inverting element's output port (except the last inverting element) may be operably connected to the subsequent inverting element's input port. The last inverting element's output port may be operably connected to the first inverting element's input port, thereby forming a chain or ring. A counter may be incremented by oscillations of an output port of an inverting element during a high portion of a periodic signal and may be decremented by oscillations of the output port of the inverting element during a low portion of the periodic signal.

Abstract: A delay circuit to generate and output a delayed signal delayed from an input signal includes a reference pulse generating circuit to generate a reference pulse train in response to the input of the input signal, the reference pulse generating circuit having a feedback circuit containing a delay portion to determine a time interval between the reference pulses, a counter to output count signals based on a reference clock, the counter receiving the reference pulse train generated by the reference pulse generating circuit as the reference clock, and a delayed signal output circuit to generate and output the delayed signal based on the input signal and the count signals.

Abstract: Compound MOS capacitors and phase-locked loop with the compound MOS capacitors are disclosed. In the phase-locked loop, the compound MOS capacitors of the loop filter are HV (high voltage) devices, and the voltage control oscillator is a LV (low voltage) device. The compound MOS capacitor comprises a HV PMOS capacitor having a base coupled to a source terminal of a low voltage source and a HV NMOS capacitor having a base coupled to a ground terminal of the low voltage source. The gates of the HV PMOS capacitor and the HV NMOS capacitor are connected together to receive a control voltage. The capacitance of the compound MOS capacitor is near constant in any control voltage.

Abstract: A method performed by a quality assurance integrated circuit for a print controller, the quality assurance integrated circuit comprising a memory; a system clock for generating a clock signal; clock trim circuitry for trimming the frequency of the clock signal; and a processor. the method includes, in the processor, in response to receiving an external signal, determining the number of cycles of the clock signal during a predetermined number of cycles of the external signal or the number of cycles of the external signal during a predetermined number of cycles of the clock signal and to output the determined number of cycles to an external circuit; and in response to receiving a trim value based on the determined number of cycles from the external circuit, storing the trim value in the memory and controlling the clock trim circuitry to trim the frequency of the clock signal using the trim value.

Abstract: In accordance with the present disclosure, an electronic circuit of an integrated circuit is configured to receive an input signal that has a falling transition and a rising transition and provide a selectable delay of the input signal transitions on its output. The output of the disclosed circuit can provide a falling transition delayed in response to a falling edge control signal control, and a rising transition delayed in response to a rising edge control signal. The disclosed circuit can have a rising transition control circuit (RTCC), a falling transition control circuit (FTCC) and an output circuit.

Abstract: An apparatus, includes a counter which counts a frequency of input of a first signal, a delay controller which generates a second signal by adding a delay to the first signal, the delay corresponding to the frequency, and a control circuit which halts the counter counting the frequency, when a phase difference between the first signal and the second signal is a predetermined value.

Abstract: A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.

Abstract: An output driver capable of controlling a short circuit current includes a driving unit and a driving control unit. The driving unit receives a first driving signal and a second driving signal in response to a control signal and generates an output signal. The driving unit control unit includes a driving unit copying unit having the same construction as the driving unit and compares an output copying signal generated from the first and second driving signals by the driving unit copying unit with a reference voltage and generates the control signal that controls delays of the first and second driving signals in a test mode.

Abstract: An internal clock generator includes a detector, an internal signal generator and a clock output unit. The detector detects a transition point of an external clock signal and outputting a detection signal. The internal signal generator generates an internal signal in response to the detection signal and a pulse width control signal. The clock output unit outputs an internal clock signal having a pulse width, which is set based on the internal signal. A transition point of an external clock signal is detected and an internal clock signal is generated based on the detection result. It is therefore possible to maintain the pulse width of the internal clock signal to a set value regardless of variation in the pulse width of the external clock signal.

Abstract: Systems and methods for controlling timing of switches in power regulator/power amplifiers.

Abstract: A delay line including a sequence of identical delay cells with improved gain and in built duty cycle distortion control and a method thereof is disclosed. Each delay cell of the sequence includes a current source, four transistors, and a load capacitor. A gate of the current source receives a voltage bias that controls a delay of the delay cell. A drain of the first transistor is connected to the drain of the current source. The first and second transistor gates receive an input clock signal. The second transistor drain is connected to the source of the current source. The third transistor gate and the load capacitor are also connected to the drain of the current source. The fourth transistor drain is connected to the third transistor drain. The fourth transistor gate is coupled to an output of a second consecutive delay cell for duty cycle distortion control.

Abstract: A delay control circuit includes a first delay unit, a signal regulation unit, a selector and a second delay unit. The first delay unit is used for delaying an input signal and generates a delayed input signal. The signal regulation unit is coupled to the first delay unit and outputs a rising edge delay signal and a falling edge delay signal according to the input signal and the delayed input signal. The selector is coupled with the signal regulation unit and outputs one of rising edge delay signal and falling edge delay signal according to the control signal. The second delay unit is coupled to the selector for delaying the output of the selector and outputting an output signal.

Abstract: A new method to sample a digital input signal is achieved. The method comprises sampling a digital input processed through a first digital buffer. The sampling is at the rising edge of a system clock. The switching threshold of a second digital buffer is updated. The digital input processed through the second digital buffer is sampled. The sampling is at the falling edge of the system clock. The switching threshold of the first digital buffer is updated. A digital sampling circuit is achieved.

Abstract: An oscillator circuit includes an enable circuit to generate an initialization signal and includes a ring oscillator responsive to the initialization signal and having a plurality of synchronous elements connected in a loop, wherein each synchronous element comprises a synchronous input terminal, a clock terminal, a first asynchronous input terminal, and an output terminal coupled to the clock terminal of a next synchronous element and coupled to the first asynchronous input terminal of a previous synchronous element. The enable circuit is independent of a delay path of the ring oscillator, and the ring oscillator generates a test clock signal having a period that does not include any signal delays associated with the enable circuit.

Abstract: A ring oscillator comprises a first logic block having a first input connected to a specific point along a delay path, a first output and a second output and a second logic block having a first input connected to the first output of the first logic block, a second input connected to the second output of the first logic block, a third input connected to the end of the delay path and a first output connected to the beginning of the delay path. The first logic block is arranged to, in use, alternately switch its first output and second output from logical HIGH to logical LOW, and vice versa, every time a rising edge is input into its first input. The second logic block is arranged to, in use, alternately select its first input and its second input every time a rising edge is input into its third input.

Abstract: An internal clock signal driver circuit includes a delay block that delays a rising clock signal and a falling clock signal, and outputs a delayed rising clock signal and a delayed falling clock signal, a rising DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed rising clock signal, and outputs a rising DLL clock signal, and a falling DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed falling clock signal, and outputs a falling DLL clock signal.

Abstract: The duty cycle of a signal is modified by passing the signal through a plurality of inverting stages. The inverting stages each have bias circuitry to influence the input switching threshold of inverters. Multiple duty cycle modification circuits produce non-overlapping local oscillator signals in a system.

Abstract: A delay circuit (12) includes a resistor (R1), a capacitor (C), and a discharging circuit (14). The discharging circuit includes a PNP transistor (Q1) and an NPN transistor (Q2). The capacitor has one terminal connected to one terminal of the resistor, and the other terminal connected to ground. The PNP transistor has a base connected to the other terminal of the resistor, a collector, and an emitter connected to a voltage source. The NPN transistor has a base connected to the collector of the PNP transistor, an emitter connected to ground, and a collector connected to the one terminal of the resistor.

Abstract: An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Abstract: Embodiments of a multiphase generator with duty-cycle correction are generally described herein. In some embodiments, the multiphase generator comprises controllable delay stages arranged in series and dual-edge phase detector circuitry. The dual-edge phase detector circuitry may generate a control signal to adjust the delay provided by the delay stages based on corresponding rising edges and corresponding falling edges of same-state signals operated on by the delay stages. Other circuits, systems, and methods are described.

Abstract: A reduced area delay circuit and method are disclosed. The delay circuit uses a constant current source and a constant current drain to charge and discharge a capacitor and thus control the delay time of the delay circuit. The constant current source and drain can be implemented using current mirrors formed by configuring MOSFET transistors in a common source configuration. The delay circuit method includes the steps of receiving an input signal, delaying the input signal by using a constant current source or drain in combination with a capacitor, and then buffering the voltage on the capacitor using two inverters. A programmable delay circuit is also disclosed by adding additional pairs of current mirrors to the delay circuit and selectively enabling the pairs to adjust the delay time.