Abstract: A device for compensating a signal delay introduced by a second circuit is provided. The second circuit is configured to receive a signal and to output the signal with the first delay if the first signal transitions from a first to a second logic level. The second circuit is configured to output the signal with the second delay if the first signal transitions from the second to the first logic level. The device according to the present invention includes a first circuit that is configured to receive the signal. The first circuit is configured to introduce the first delay, if the signal transitions from a second to a first logic level. The first circuit is configured to introduce the second delay if the signal transitions from the first to the second logic level.

Abstract: A reduced area delay circuit and method are disclosed. The delay circuit uses a constant current source and a constant current drain to charge and discharge a capacitor and thus control the delay time of the delay circuit. The constant current source and drain can be implemented using current mirrors formed by configuring MOSFET transistors in a common source configuration. The delay circuit method includes the steps of receiving an input signal, delaying the input signal by using a constant current source or drain in combination with a capacitor, and then buffering the voltage on the capacitor using two inverters. A programmable delay circuit is also disclosed by adding additional pairs of current mirrors to the delay circuit and selectively enabling the pairs to adjust the delay time.

Abstract: An A/D converter samples an analog video signal, having a frequency corresponding to various types of image supply apparatus, and converts the signal into a digital signal. A sampling clock signal supply circuit supplies a sampling clock signal to the A/D converter, and comprises an edge detection circuit for adjusting the phase of the sampling clock signal. The edge detection circuit subjects the video signal and a delayed video signal to subtraction processing to generate edge pulses. A processor selects a sampling clock signal of a desired phase based on edge information determined by these edge pulses. The present device can also adjust a threshold voltage that is input to the comparator, and the phase of the sampling clock signal based on a digital signal, and supply a dedicated video signal for phase adjustment from a personal computer.

Abstract: Digital signal delay lines with electrically programmable and trimmable delay times, including electrically erasable and reprogrammable delay times. Floating gate field effect transistors are programmed to select current, capacitance, and/or threshold and thereby set a delay time determined by acurrent charging of a capacitor up to a threshold voltage. Trimming after packaging avoids package offsets. Temperature and power supply voltage compensation by current combining gives compensation compatible with the electrical programming.

Abstract: A circuit for generating a pulse signal in response to an input signal. The circuit provides a pulse width for the pulse signal. A first logic device receives the input signal and generates a first intermediate signal. A delay device is coupled to the first logic device and receives the first intermediate signal. The delay device generates a second intermediate signal in response to the first intermediate signal after a period of time. The second intermediate signal has the same state as the second intermediate signal. A second logic device is coupled to both the first logic device and the delay device. The second logic device generates the pulse signal in response to the first intermediate signal.

Abstract: A delay line formed by a set of series-connected logic gates produces a sequence of output pulses in delayed response to a sequence of input pulses. The delay provided by a delay line changes with the frequency of its input pulse sequence because of temperature change in the gates due to changing power usage. Therefore a pulse stuffing circuit is provided to monitor the sequence of input pulses supplied to the delay line and to generate one or more stuff pulses when a period between successive input pulses exceeds a target maximum period. Each stuff pulse is sent as an additional input pulse to the delay circuit to decrease the period between input signal pulses. Although the delay circuit adds extra pulses to its output pulse sequence in response to the stuff pulses, the pulse stuffing circuit includes a gating circuit for removing those extra pulses from the output pulse sequence.

Abstract: A first capacitor 7, a resistor 5, and a second capacitor 6 are connected in series between an output node A and a first power supply line 22. In addition, a first switch 8 is connected between the connected point of the first capacitor 7 and the resistor 5 and a second power supply line. A second switch 9 is connected in parallel with the second capacitor 6. The first and second switches 8 and 9 are opened or closed corresponding to the level of the input signal.

Abstract: A clock deskew circuit comprises a variable delay module and a control module. Included in the variable delay module are an input terminal for receiving a digital input clock signal, a control terminal for receiving an analog control signal, and a delay circuit which propagates the input clock signal from the input terminal to a buffer such that certain type signal edges (i.e., rising edges or falling edges) are delayed for a time interval which is varied in a continuous fashion by the magnitude of the control signal. Included in the control module is a feedback lead which receives the delayed clock signal from the buffer of the delay module, another lead which carries the input clock signal, and a control signal generating circuit.

Abstract: A relay control circuit that includes a zero cross detector, a latch, and a delay circuit. The zero cross detector circuit detects when the voltage waveform or current waveform on an AC power line is at the zero crossing. The output of the zero cross detector clocks the latch (flip-flop), which receives a control signal at its data input. The flip-flop latches the control signal on the zero crossing point and outputs the latched signal to the delay circuit. The delay circuit delays the control signal for a predetermined time period depending on the make and break times of the relay so that the relay is switched ON and OFF substantially near the next zero crossing point of the AC voltage waveform.

Abstract: The present invention provides a circuit (10) and method for providing a delayed output signal which is less sensitive to supply variation compared to conventional circuits, has high noise immunity, can be operated at high frequency, and occupies a minimum area on the semiconductor. The delay is provided according to the present invention by separately controlling the discharge currents of a capacitor (26) before and after the trip point voltage of an output inverter (16) of the circuit (10) has been reached. The delay interval is determined primarily by the capacitor value, the voltage difference between the supply and the trip point of the output inverter, and the first discharge current, set by a resistor (24) in series with a transistor (34). The second discharge current is set by a switch (36) having a series of transistors (38, 40).

Abstract: For high-speed single-ended sensing of the small signal delivered from a (static) RAM or ROM cell, a voltage dependent timing delay circuit is disclosed which prevents early triggering of the set signal of the sense amplifier (SSA 66) when applying a high voltage screen test (i.e. 1.5 times V.sub.DD) to the cell. The timing of the SSA signal is achieved by a high precision delay chain comprising inverters, which is loaded by a voltage dependent current sink (70) coupled to the output of the chain. The inverter delay chain controls the input (SE0) for a driver for the SSA line (66). The current sink may be a pull down NFET (70) which is only activated when the supply voltage is above a determined switching threshold therefor. The gate voltage of the NFET is controlled by a bias control circuit (72) in such a manner that during operation at typical voltage levels, the NFET is deactivated, whereas at higher operating voltage levels (such as 1.5 * V.sub.

Abstract: A PLL circuit includes a sampling pulse generator and a loop circuit using a sample and hold circuit as a phase detector. The sampling pulse generator generates a sampling pulse signal at each level transition of an NRZ input signal. The sample and hold circuit samples a clock signal and hold a voltage signal corresponding to a voltage of the clock signal according to the sampling pulse signal. A voltage-controlled oscillator included in the loop circuit generates the clock signal whose frequency is controlled based on tho voltage signal received from the sample and hold circuit through a loop filter. The voltage signal remains at an appropriate level even when the NRZ input signal remains at the same level for a relatively long time. The sampling pulse generator includes a delay circuit for delaying the NRZ input signal and an exclusive-OR circuit receiving the NRZ input signal and the delayed signal.

Abstract: A pulse generator has an input and two outputs at which to respectively generate pulses in relation to different types of signal edges received at the input of the generator. The generator provides two distinct logic circuit blocks of the sequential type, the blocks being mutually independent for generation of the pulses at the two outputs. In this manner it is possible to easily control the characteristics of the pulses. In addition, if two blocks are connected with appropriate and simple logic networks, it is possible in the generation phase to impose conditions between the pulses at the two outputs in a simple manner and with a certain freedom.

Abstract: A digital signal delay circuit includes a first pair of counters for setting a starting point of a digital output signal by counting an adjustably set number of clock pulses corresponding to an intended time delay from a starting point of a digital input signal. The circuit further includes a second pair of counters for setting an ending point of the digital output signal by counting an adjustably set number of clock pulses corresponding to an intended output pulse width from an ending point of the digital input signal. The state of the digital output signal is only determined by the state of the output signal of the last counter in the first pair of counters. The output signal from the last counter in the first pair of counters controls a count starting point of the first counter in the second pair of counters. The output signal from the second pair of counters controls an initializing point on which the state of the output signal from the last counter in the first pair of counters is inverted.

Abstract: Internal node timing on an integrated circuit which is supplied with a clock signal from a system clock, the cycle time of which can be varied is measured by connecting a sequential element such as a latch to the node to measured and clocking it with a delayed measurement clock while increasing the clock cycle time. The output of the sequential element is an output pin of said integrated circuit. The measurement clock has the same cycle time as the system clock but has a latching edge delayed, the delay being at least 1.5 times the nominal system clock cycle time when it is desired to make measurement over both the high phase and low phase. The output pin is observed and the clock cycle time at which the sequential element fails to latch the current value determined. In a further embodiment, two sequential elements are used to make two measurements of this type and the difference between the two measurements is used to compute the time delay between the two nodes being measured. One node may be a clock node.

Abstract: A pulse generating circuit includes a first portion and a second portion. The first portion is coupled to a control signal and a first signal, and generates the rising edge of a pulse signal in response to the control signal transitioning to a first state. The second portion receives the rising edge of the pulse signal and causes the first signal to transition to a second state in response to the rising edge of the pulse. The transitioning of the first signal to the second state causes the first portion to generate a falling edge of the pulse signal.

Abstract: A power short pulse generator for generating a pulse on a rising edge and falling edge of an input signal according to the present invention comprises an input node for receiving the input signal and an output node for supplying an output signal. A first pulldown circuit and a second pulldown circuit are connected in series between the output node and a first supply voltage potential, the first pulldown circuit and the second pulldown circuit each having an input. A third pulldown circuit and a fourth pulldown circuit are connected in series between the output node and the first supply voltage potential, the third pulldown circuit and the fourth pulldown circuit each having an input. A pullup circuit is connected between the output node and a second supply voltage potential, the pullup circuit having an input. A leakage current circuit is connected between the output node and the second supply voltage potential.

Abstract: An astable multivibrator comprising a capacitor connected between a first output signal and a third output signal, an amplification circuit connected between the first and third output signals, a delay for delaying a signal logic-converted from the first output signal and for outputting a second output signal, and a variable resistor connected between the first output signal and an output node of the delay. High frequency oscillation performance is enhanced and a larger voltage operating range is obtained by excluding the effect of feedback current.

Abstract: A variable delay circuit which includes a first power source line for supplying a first power source voltage, a second power source line for supplying a second power source voltage which is smaller than the first power source voltage, an input terminal for receiving an input signal, a selection terminal for receiving a selection signal, an output terminal for outputting an output signal which is delayed relative to the input signal, a pull-up circuit coupled between the first power source line and the output terminal for carrying out a pull-up operation based on the input signal which is received via the input terminal, and a pull-down circuit coupled between the output terminal and the second power source line for carrying out a pull-down operation based on the input signal which is received via the input terminal. The pull-up or pull-down circuit has a delay time which is variable in response to the selection signal which is received via the selection terminal.

Abstract: In a variable delay circuit for delaying an input signal by a variable delay time from a rising edge or a falling edge of the input signal to a rising edge or a falling edge of an output signal in a digital circuit, a data signal input terminal; a first signal input terminal to which a low-level signal of a logic gate is applied; n selector circuits (n=integer larger than 0) selecting either the signal at the data signal input terminal or the signal at the first signal input terminal in response to signals applied to first selector signal input terminals; and an (n+1)-input NOR circuit to which the signal at the data signal input terminal and output signals from the selector circuits are applied. In this variable delay circuit, a delay time shorter than the delay time of a single-stage buffer circuit can be controlled using only digital circuits.

Abstract: Digital signal delay lines with electrically programmable and trimmable delay times, including electrically erasable and reprogrammable delay times. Floating gate field effect transistors are programmed to select current, capacitance, and/or threshold and thereby set a delay time determined by acurrent charging of a capacitor up to a threshold voltage. Trimming after packaging avoids package offsets. Temperature and power supply voltage compensation by current combining gives compensation compatible with the electrical programming.

Abstract: A delay circuit is mainly configured by a plurality of paths, each having a different amount of delay, and at least selector. The selector selects one of the paths on the basis of delay data in such a way that a desired amount of delay is obtained. When an input pulse signal is applied to the delay circuit, the input pulse signal is delivered to the paths, so that pulses respectively transmit through the paths with being delayed by different delay times. For this reason, the pulses should arrive the selector at different timings which are affected by manufacturing process of circuit elements, variation of temperature and deviation of power-supply voltage. The selector is designed to cope with a problem due to different arrival timings of the pulses.

Abstract: A relay control circuit that includes a zero cross detector, a latch, and a delay circuit. The zero cross detector circuit detects when the voltage waveform or current waveform on an AC power line is at the zero crossing. The output of the zero cross detector clocks the latch (flip-flop), which receives a control signal at its data input. The flip-flop latches the control signal on the zero crossing point and outputs the latched signal to the delay circuit. The delay circuit delays the control signal for a predetermined time period depending on the make and break times of the relay so that the relay is switched ON and OFF substantially near the next zero crossing point of the AC voltage waveform.

Abstract: A digital signal transmission circuit for transmitting an input pulse signal to receiving circuits through transmission lines. The digital signal transmission circuit is provided with a phase converting circuit for outputting a first output signal and a second output signal delayed in phase with respect to the first output signal according to the input of the pulse signal, a first transmission line included in the transmission lines, for transmitting the first output signal, a second transmission line included in the transmission lines, for transmitting the second output signal, and a pair of phase decoding circuits for receiving the first and second output signals from the first and second transmission lines and outputting pulse signals according to the state of reception of the first and second output signals.

Abstract: An adjustable timer circuit capable of producing accurate pulse outputs having a wide range of periods. The timer circuit includes a timing capacitor and an associated current source for producing a reference current having a magnitude which is derived from a reference voltage. A current divider is used to divide the reference current down to a smaller current used for charging the timing capacitor. A comparator circuit is provided for comparing the voltage produced across the timing capacitor with a comparison voltage also derived from the reference voltage. The timing capacitor is discharged in response to the comparator output so that subsequent output pulses can be produced. The current divider is adjustable in response to a mode control signal so that different magnitude charging currents can be produced which results in different magnitude pulse width outputs.

Abstract: A pulse signal generator includes a first delay device for delaying an input pulse signal and converting the input signal into a first intermediate signal. A power supply voltage detector detects a power supply voltage and outputs a signal representative thereof. A second delay device serves to delay the first intermediate signal and to convert the first intermediate signal into a second intermediate signal in response to the output signal from the power supply voltage detector. A logic OR operation is executed between the first and second intermediate signals, and an output signal is generated in response to the first and second intermediate signals. The output signal has a pulse width, which is greater than a pulse width of the input signal when the power supply voltage lies in a predetermined range.

Abstract: Delay circuit comprising a delay cell formed by a current source (I) connected between drain and source of two field-effect transistors (PO, NO) whose gates are connected to each other in order to constitute the input of the cell, and an inverter (INV) linked to one or other of the terminals of the current source (I) according to whether the delay is to affect the leading edge or the trailing edge of the signal to be delayed, a capacitor (C) for defining a delay time (Te) proportional to the power supply voltage and inversely proportional to the current (I) delivered by the current source, being connected between the input of the inverter (INV) and earth, characterized in that it furthermore comprises a circuit (Ci, Cu, S1, S3, AMPLO, P1) for regulating the current delivered by the current source in order to make it proportional to the power supply voltage of the circuit.

Abstract: A delay element (10) generates a delay pulse (OUT) the length of which is not dependent on an available system clock. The delay element uses oscillators (12a, 12b, 12c) and edge detectors (16a, 16b, 16c) to generate a delay based on the beat frequency of the oscillators. The delay element is suitable for fabrication as part of a CMOS integrated circuit, and requires less layout area than alternative methods.

Abstract: An integrated detection circuit (10) linearly charges capacitors (14) and (16) over time in response to particular states of an input signal (12). Outputs from the integrated detection circuit (10) are generated by differential pairs (39) when the charge on either of the capacitors (14) or (16) is equal to or greater than a reference voltage input to the differential pairs (39).

Abstract: A method and apparatus for testing and programming signal timing are disclosed which can be incorporated into an integrated circuit device utilizing on-chip timed command signals and pulses. The method of the invention enables nonpermanent testing and retesting of a device at various operational speeds during production testing. During retesting, temporary signal delays are selectively introduced into the circuit of a device which failed a previous test due to non-repairable errors. Once a device passes the production test error-free or with repairable errors, the temporary signal delays are permanently programmed into the device. Specifically, the method utilizes one or a plurality of mode control circuits and test voltage input terminals to nonpermanently select signal delays which may be identified and permanently enabled at a later time.

Abstract: A digital signal transmission circuit for transmitting an input pulse signal to receiving circuits through transmission lines. The digital signal transmission circuit is provided with a phase converting circuit for outputting a first output signal and a second output signal delayed in phase with respect to the first output signal according to the input of the pulse signal, a first transmission line included in the transmission lines, for transmitting the first output signal, a second transmission line included in the transmission lines, for transmitting the second output signal, and a pair of phase decoding circuits for receiving the first and second output signals from the first and second transmission lines and outputting pulse signals according to the state of reception of the first and second output signals.

Abstract: The apparatus and method described herein provides for generating a delayed reference in response to a received reference. The occurrence of a first event in the received reference is detected and a delay period started in response thereto. At the end of the delay period a reset is generated. A delayed version of the received reference is then generated in response to the reset. In addition, a delayed signal is generated to steer a companion delay to the same value.

Abstract: Control signals are provided for data transfer timing compatibility between two systems or two modules which are not synchronous with each other. Specialized circuitry is provided to ensure timing compatibility in that control signals, transmitted from one system to the other, are handled by interface circuitry which directly transmits the front-end transition and delays the back-end transition so it can be synchronized to the receiving systems clock.

Abstract: A timing generator, which is simple in construction and is capable of high speed operation with excellent linearity and low power consumption, wherein a delayed timing signal is generated by delaying an input timing signal. The generator comprises a switch having one end thereof connected to a first voltage source and which is controlled by the input timing signal, a current source provided between the other end of the switch and a second voltage source; a charge injection circuit generating a voltage signal which is turned ON and OFF in accordance with the input timing signal; a capacitor provided between the output end of the charge injection circuit and the other end of the switch; and a comparator generating a delayed timing signal by comparing the voltage at the other end of the switch with a desired voltage, wherein the delay time of the delayed timing signal is adjusted by controlling either the voltage outputted from the charge injection circuit or the current from the current source.

Abstract: A clock is phase shifted by an amount controlled by the value of a control signal by establishing at least several discrete delay times to be imposed on the clock. The control signal value controls selection of the imposed discrete delay time. An analog-to-digital converter of a phase locked loop responds to intelligence representing variable phase bits and the selected phase shifted clock to control the signal value. The selected replica is derived by at least several cascaded substantially equal time delay units. In one embodiment, a multiplexer responds to the clock, and the signal value, which is Gray coded, to control connections from one of the delay units to an output terminal. In another embodiment, the number of cascaded delay units interposed between the clock and an output terminal is controlled by the signal value.

Abstract: An address transition detector stores a first output signal on an output terminal for a first predetermined period of time in response to an initial edge of an internal address signal pulse. The address transition detector stores a second output signal on the output terminal for a second predetermined period of time in response to the trailing edge of the internal address signal pulse. When the trailing edge of the internal address signal pulse is delayed from the leading edge of the internal address signal pulse by an amount greater than the first predetermined period, then output signal consists of two pulses. When the trailing edge of the internal address signal pulse is delayed from the leading edge by a time less than the first predetermined period, then the signal on the output terminal is a single expanded signal. Typically, the first and second predetermined periods are equal.

Abstract: A frame buffer including an array of memory cells, circuitry for accessing the memory cells to derive selected pixel data, and output circuitry for providing data signals at an output port, the output circuitry including circuitry for determining the precise time required for a data signal to rise and fall at the output port, such circuitry being selected to provide the minimum delay between succeeding data signals at the output port.

Abstract: A circuit for the generation of a time-stabilized output pulse Iout comprises a capacitor biased by two completely independent voltages whose bias voltages are fixed by a current generator through current mirrors and are therefore very stable.

Abstract: A transition detection circuit is provided comprising input means receiving the signal to be monitored for generating a first pulse having a first predetermined pulsewidth when a transition occurs in the signal being monitored; and output means responsive to the first pulse from the input means for generating a second pulse having a second predetermined pulsewidth which is less than the first predetermined pulsewidth. The present invention permits a large number of signals to be monitored for transition yet provide a highly precise output pulsewidth, all with a minimum of circuitry. Preferably the input means include a plurality of input channels, each channel being assigned to a different signal being monitored and each channel providing the first predetermined pulsewidth using simple, non-precision time delay circuits. The output state employs a single, high precision time delay circuit to provide the second predetermined pulsewidth.

Abstract: An apparatus for and method of producing a highly accurate and easily recalibratable delay line using only digital components. A serial string of digital gates or buffers is coupled together to permit an input signal to cascade through all of the gates or buffers. The length of time for the signal to cascade is determined by the average propagation delay of the buffers and the number of buffers in the serial string. Taps at the outputs of the buffers permit selection of the desired delay by selecting the output from less than all of the buffers in the string. Calibration is accomplished by passing a calibration pulse of predetermined pulse width through the delay string of buffers. A calibration register records the buffer position of the leading edge of the calibration pulse at the time the trailing edge of the calibration pulse enters the string. The number of buffers thus identified provides a delay equal to the length of the calibration pulse under the current ambient conditions.

Abstract: A pulse generator circuit 20 is disclosed herein. An asymmetric delay element 22 is coupled to one of the inputs of a logic element 24, such as a NAND gate. For the asymmetric delay 22, the time to propagate a transition from a high level to a low level is different then the time to propagate a transition from a low level to a high level. The input of the asymmetric delay element 22 is coupled to another of the inputs of the logic gate 24. The pulse generator circuit 20 of the present invention generates a pulse at its output OUT when a signal applied to its input IN transitions from a first signal level to a second signal level.

Abstract: A programmable delay generator produces a composite delayed pulse from an input pulse, and the leading edge of the composite delayed pulse is controlled by a voltage comparator with a variable reference voltage level supplied from a digital-to-analog converter; however, an OR gate determines the trailing edge of the composite delayed pulse with a delayed input pulse supplied from a delay circuit so that the trailing edge is independently controllable regardless of the time delay introduced by the voltage comparator.

Abstract: A memory has at least one decoder responsive to a synchronizing pulse for providing a selection signal to the memory cells coincident with the partial selection signal for thereby selecting a group of memory cells for an operation. The decoder has a variable time delay characteristic between the synchronizing pulse and the selection signal. The pulse generator has a mimicking circuit responsive to the synchronizing pulse for providing the partial selection signal to the group of memory cells. The mimicking circuit provides a time delay characteristic between the receipt of the synchronizing pulse and the partial selection signal which mimics the variable delay characteristic of the at least one decoder.

Abstract: A delayed-pulse generator formed by a combination of a comparator, a current-mirror circuit, a capacitor, a switching transistor and a constant-current source further has a transistor whose emitter and base are connected together and which is connected in parallel and in forward-direction with respect to the constant-current source. A charging current of a very small value can be set stably without being affected by the leakage current flowing in the switching transistor even in a high temperature operation. Thus, a pulse having a long delay time can be readily obtained. In addition, an erroneous operation caused by the leakage current flowing in the switching transistor can be effectively suppressed.

Abstract: Two edge detectors (12, 13) at the input (10.1) and the output (10.2) of a delay line (10) of the edge detector arrangement (11) generate detection signals of identical shape at the detected signal edges of a signal traveling over the delay line. The delay time of the delay line is selected so that the two detection signals partly overlap in time. A subtraction arrangement (16) generates, from the two detection signals, a difference signal that contains, in the overlap region, a zero crossing that can be detected by a zero crossing detector (17). At the time of this zero crossing, the zero crossing detector generates the switching edge of an edge detection signal that controls, for example, a signal switcher (9).