Abstract: Provided is a semiconductor device with a novel structure in which the power consumption can be reduced. The semiconductor device includes a sensor, a sample-and-hold circuit to which a sensor signal of the sensor is input, an analog-digital converter circuit to which an output signal of the sample-and-hold circuit is input, a control circuit, a battery, and an antenna.

Abstract: A bidirectional transceiver includes a transmitter and a receiver that respectively transmits a local signal to and receives remote signal from a common bidirectional communication channel, thus the bidirectional channel signal is the superimposition of the local and remote signals. The bidirectional transceiver also includes a transmit canceller that substantially removes the local transmitted signal from the superimposed signals on the bidirectional channel before the local receiver. The remote signal is transmitted by a remote transceiver over the bidirectional channel. A sampling phase is set, based on timing information in the received remote signal, and the received signal is sampled. Timing relation of transitions in the local transmit signal relative to the receiver sampling phase is set such that transmit signal cancellation is optimum at receiver sampling phase, by changing the delay applied to the local transmit signal.

Abstract: In an embodiment, an image sensor includes: first and second voltage rails; first and second regulators configured to generate first and second regulated voltage at the first and second voltage rails, respectively; and a plurality of pixels coupled to the first and second voltage rails. Each pixel includes: first and second transistor coupled first and second storage capacitor, respectively. A third transistor is coupled between a control terminal of the first transistor and the first or second voltage rails. The third transistor is configured to limit a slew rate of current flowing between the control terminal of the second transistor and the first or second voltage rails to a first slew rate when the image sensor operates in global shutter mode, and to a second slew rate when the image sensor operates in rolling mode, the first slew rate being smaller than the second slew rate.

Abstract: A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO), a first loop circuit, and a second loop circuit. The first loop circuit includes a first loop filter configured to receive a first signal based on a feedback signal from the VCO and provide a first VCO frequency control signal to the VCO. The second loop circuit includes a compensation circuit configured to receive a reference signal and the first signal, and provide a second VCO frequency control signal to the VCO.

Abstract: In described examples, an electronic circuit for delaying a signal (received at an input node) includes a delay line with multiple tap locations, a tap line proximate to the delay line and coupled to an output node, and multiple groups of switches. Switches in the groups of switches are severally coupled between tap locations corresponding to the respective group of switches, and the tap line. When the signal is propagated through the delay line, a first number of the switches corresponding to a selected tap location are closed, a second number of the switches corresponding to an adjacent tap location are closed, and the signal is transmitted with a delay through the closed switches, to the tap line, to the output node. The delay includes an average, weighted using the first and second numbers, of delays corresponding to the selected and adjacent tap locations.

Abstract: A delay circuit includes: a delay line that delays an input signal in accordance with a delay setting signal and performs output of the input signal as a delayed signal; and a logic circuit processes the input signal to the delay line and the delayed signal.

Abstract: A data reception device comprises: a first data input for receiving a first data signal and a clock input for receiving a clock signal; and a stability detection circuit adapted to generate: a first error signal indicating when a data transition of the first data signal occurs during a first period at least partially before a first significant clock edge of the clock signal; and a second error signal indicating when a data transition of the first data signal occurs during a second period at least partially after the first significant clock edge of the clock signal; and a control circuit configured to generate a control signal for adjusting the sampling time of the first data signal based on said first and second error signals.

Abstract: Frequency characteristics of a peaking stage can vary depending on variations in the process used to fabricate the peaking stage. For example, depending on the batch of wafers and where on a wafer the peaking stage is formed, the capacitors and resistors may have different values, thereby changing the frequency characteristics of the peaking stage. The embodiments herein describe a peaking stage that is invariant of the process variation. That is, one or more of the frequency characteristics of the peaking stages do not vary as the values of a capacitor or resistor change. As such, peaking stages formed in different process corners on the wafer have the same frequency characteristics, and thus, function in a similar manner.

Abstract: A method and apparatus for determining a difference between signal edges in two signals includes a multiple stage converter where each stage determines which of the two signals has an earlier signal edge, outputs a value corresponding to that determination, and then applies a delay to the earlier signal that is equal to half of the delay applied by the next previous stage. The stages examine smaller and smaller intervals to the sought-after signal edge. Each stage includes a plurality of logic elements. If all logic elements in the stage output the same signal, the edge position is clear. If some of the logic elements in the stage vote differently than others in the state due to differences in setup time for the different elements, the edge location has been found within the sensing band of the stage.

Abstract: Systems and methods for providing an approximate differentiation and integration of an input continuous-time signal are provided. The disclosed systems include a continuous-time delay block configured to receive an input continuous-time signal and to delay the input continuous-time signal by a predetermined delay factor to generate a delayed input continuous-time signal, a processing block configured to determine a difference or a sum between two continuous-time signals, and a multiplication block configured to multiply an input continuous signal to provide a multiplied input continuous signal.

Abstract: The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.

Abstract: A delay cell for generating a desired delay exceeding a minimum delay defined in a standard cell library is provided, which includes a delay element and an output inverter. The delay element receives an input signal to generate an internal signal with a propagation delay relative to the input signal, which includes a P-type transistor, a first resistor, a second resistor, and an N-type transistor. The P-type transistor applies a supply voltage to the first resistor by the input signal. The first resistor is coupled between the P-type transistor and the output inverter. The second resistor is coupled to the output inverter and coupled to the ground through the N-type transistor by the input signal. The output inverter receives the internal signal to generate an output signal with the desired delay, which is dominated by the propagation delay, relative to the input signal.

Abstract: A circuit has a supply line, a reference line and circuitry coupled between the supply line and the reference line. The circuitry outputs a regulated voltage and a measurement voltage. An analog-to-digital converter (ADC) generates a digital signal indicative of variations of potential differences between the supply line and the reference line based on the regulated voltage and the measurement voltage. The generated digital signal may be used to control the circuit.

Abstract: In an integrated circuit, a resettable data latch and a second resettable data latch at ends of a pipeline in a frequency-comparison circuit receive input clocks. This pipeline operates asynchronously and includes at least a pair of flow-control elements separated by a NAND-gate detector circuit. Moreover, the resettable data latch and the second resettable data latch selectively generate tokens and spaces based on rising or falling edges of the input clocks. Then, the frequency-comparison circuit moves the tokens and the spaces in the pipeline between the ends based on a difference in fundamental frequencies of the input clocks. Furthermore, arbiter circuits in the frequency-comparison circuit provide output signals based on changes in numbers of tokens proximate to the ends, to indicate how at least one of the input clocks should be adjusted so that the fundamental frequencies converge on a common value.

Abstract: An interpolator includes interpolation cells. Each interpolation cell includes a first driving unit and a second driving unit. The first driving unit includes a first pulling-up circuit for selectively coupling an output terminal to a high voltage, a first pulling-down circuit for selectively coupling the output terminal to a low voltage, and a pair of first switches for selectively enabling/disabling the first pulling-up circuit and the first pulling-down circuit. The second driving unit includes a second pulling-up circuit for selectively coupling the output terminal to the high voltage, a second pulling-down circuit for selectively coupling the output terminal to the low voltage, and a pair of second switches for selectively enabling/disabling the second pulling-up circuit and the second pulling-down circuit. Driving capabilities of the first and second pulling-up circuits are not all equal, and/or driving capabilities of the first and second pulling-down circuits are not all equal.

Abstract: An integrating A/D converter includes: a comparator comparing an input voltage to a reference voltage having a ramp waveform, a voltage value of which linearly varies with time; a higher-order bit counter starting operation or stopping operation triggered by inversion of an output signal of the comparator and outputting higher order bits by performing counting in a cycle of a clock signal; and a time-to-digital converter latching phase information of the clock signal corresponding to plural signals obtained by delaying an output signal of the comparator and decoding the latched values to output lower order bits having higher resolution than the clock cycle.

Abstract: A delay time adjusting circuit is described, in which a reference signal circuit generates at least one reference signal to an A/D conversion circuit, an input signal circuit generates an input signal to the A/D conversion circuit, the A/D conversion circuit compares the input signal with the at least one reference signal to output a digital signal to a digital logic chip, and the digital logic chip determines a delay time based on the digital signal. In this way, the delay time can be determined digitally, and an adjusting accuracy of the delay time can be increased; and also, the delay time can be adjusted through changing the level of the input signal, thus reducing circuit losses and costs.

Abstract: A critical path monitor (CPM) having a set of split paths is configured in an integrated circuit (IC) that includes a corresponding set of critical paths. A first and a second split path is configured with a first and a second simulated delay sections and fine delay sections, respectively. A delay of each of the first and second fine delay sections is adjustable in several steps. The delay of the first fine delay section is adjustable differently from the delay of the second fine delay section in response to a common operating condition change. Differently adjusting the delays of the first and the second fine delay sections causes an edge of a pulse to be synchronized between a first edge detector located after the first simulated delay section and a second edge detector located after the second simulated delay section.

Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.

Abstract: A voltage controlled oscillator (VCO) includes a current controlled oscillator, a voltage-to-current converter, and a sensing circuit. The sensing circuit includes a delay unit, and the sensing circuit is configured to generate a plurality of compensation control signals in response to a time delay of the delay unit. The voltage-to-current converter is configured to generate a current signal in response to a VCO control signal and the plurality of compensation control signals. The current controlled oscillator is configured to generate an oscillating signal in response to the current signal.

Abstract: A circuit for skewing differential signals includes a coarse adjustment stage configured to receive a differential input signal having a true component and a complement component, the coarse adjustment stage configured to impart a first controllable delay to at least one of the true component and the complement component of the differential signal, and a fine adjustment stage configured to impart a second controllable delay to at least one of the true component and the complement component of the differential signal, the second controllable delay having a resolution different than a resolution of the first controllable delay, the first controllable delay and the second controllable delay providing a timing skew between the true component and the complement component of the differential signal.

Abstract: A circuit for skewing differential signals includes a coarse adjustment stage configured to receive a differential input signal having a true component and a complement component, the coarse adjustment stage configured to impart a first controllable delay to at least one of the true component and the complement component of the differential signal, and a fine adjustment stage configured to impart a second controllable delay to at least one of the true component and the complement component of the differential signal, the second controllable delay having a resolution different than a resolution of the first controllable delay, the first controllable delay and the second controllable delay providing a timing skew between the true component and the complement component of the differential signal.

Abstract: A digitally controlled delay device includes at least one delay generating gate device, whose propagation delay is controlled by limiting operating current by means of a tail transistor that is controlled by its gate voltage, a gate control voltage control means for controlling the current limiting transistor gate voltage, and a bank of digitally controlled MOSFET transistors in parallel configuration, and the digital control is adapted to switch the transistors to off and to diode mode connection, current feeding means to feed current through the bank of MOSFET transistors, and the voltage over the bank of parallel transistors is used for gate source control voltage of the tail transistors.

Abstract: In an approach for calibrating a delay line having a plurality of taps, a first clock signal is input to the delay line. A second clock signal is input to a reference circuit having a plurality of taps. In response to determining that output signals of selected taps of the delay line and reference circuit do not align, a next tap of the reference circuit is selected, to determine whether or not the output signals align. In response to determining that the output signals align, reference tap data indicative of the current reference tap is stored in association with a delay tap number of the current delay tap. A next tap of the delay line is selected to determine whether or not the output signals align.

Abstract: An edge alignment apparatus includes: a signal source, for generating a first and a second square wave signals; a phase delay circuit, for receiving the first and the second square wave signals to generate a delayed first and a delayed second square wave signals; a data circuit, for generating a third square wave signal according to the delayed second square wave signal; and a phase calibrating circuit, for receiving the third square wave signal and the delayed first squared wave signal to generate at least one phase tuning signal to the phase delay circuit for tuning a phase difference between the delayed first and the delayed second square wave signals, such that a signal edge of the third square wave signal aligns with that of the first square wave signal. The first, second and third square wave signals have a same frequency.

Abstract: A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to Nth (N is an integer equal to or greater than 2) delay units with binary weights. The delay value control circuit includes a replica delay unit replicating an Ath (2?A?N) delay unit; and a delay control unit configured to compare a phase of a first output signal generated from delaying an input signal with an A?1th delay unit and a phase of a second output signal generated from delaying the input signal with the Ath delay unit and the replica delay unit and configured to control a delay value of the Ath delay unit using a comparison result.

Abstract: A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to Nth (N is an integer equal to or greater than 2) delay units with binary weights. The delay value control circuit includes a replica delay unit replicating an Ath (2?A?N) delay unit; and a delay control unit configured to compare a phase of a first output signal generated from delaying an input signal with an A?1th delay unit and a phase of a second output signal generated from delaying the input signal with the Ath delay unit and the replica delay unit and configured to control a delay value of the Ath delay unit using a comparison result.

Abstract: Circuits, apparatuses, and methods are disclosed for delay models. In one such example circuit, a first delay model circuit is configured to provide a first output signal by modeling a delay of a signal through a path. A second delay model circuit is configured to provide a second output signal by modeling the delay of the signal through the path. A compare circuit is coupled to the first and second delay model circuits. The compare circuit is configured to compare a third signal from the first delay model circuit and a fourth signal from the second delay model circuit, and, in response provide an adjustment signal to adjust the delay of the second delay model circuit.

Abstract: Disclosed is a digitally controlled oscillator which includes a ring oscillator; and a variable resistance bank connected between one power node of the ring oscillator and a power supply terminal and having the resistance value varied according to the number of active bits of a control code. The frequency of an clock signal output by the ring oscillator is changed non-linearly according to the resistance value of the variable resistance bank. The frequency of the output clock signal is changed stepwise linearly according to the number of active bits of the control code.

Abstract: Phase-coherent differential structures contain a phase-coherent transformer having two pairs of phase-coherent coupled differential inductors.

Abstract: Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.

Abstract: A digital controlled delay line (DCDL) includes a signal gated delay line generating a delayed signal, a phase selector, a controller, an input signal and an output signal. The phase selector includes logic gates to couple the delayed signal from the signal gated delay line to the output signal. Preventing signal propagation to unused cells and logic gates reduces power consumption. The number of logic gates in the phase selector the delayed signal passes through is log2 p, wherein p is the number of the signal gated delay cells in the signal gated delay line and p is a power of 2. The number of logic gates is (integer part of log2 p)+1, wherein p is the number of the signal gated delay cells and p is not a power of 2.

Abstract: There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S2) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S6) and a predetermined linearity condition (S7).

Abstract: A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to Nth (N is an integer equal to or greater than 2) delay units with binary weights. The delay value control circuit includes a replica delay unit replicating an Ath (2?A?N) delay unit; and a delay control unit configured to compare a phase of a first output signal generated from delaying an input signal with an A?1th delay unit and a phase of a second output signal generated from delaying the input signal with the Ath delay unit and the replica delay unit and configured to control a delay value of the Ath delay unit using a comparison result.

Abstract: A charge domain filter (CDF) is provided. The CDF includes a switched-capacitor network (SCN) and a clock generator. An input of the SCN receives an input signal. The SCN samples the input signal according to clock signals with different phases. The clock generator is coupled to the SCN for providing the clock signals. The clock generator adjusts phase differences of the clock signals or pulse widths of the clock signals in accordance with a control signal.

Abstract: In an A/D conversion circuit and an imaging device, an upper counter acquires a first upper count value by performing counting using one output signal, which constitutes a first lower phase signal output from a delay circuit, as a count clock. After values of bits constituting the first upper count value are inverted, the upper counter acquires a second upper count value by performing counting using one output signal, which constitutes a second lower phase signal output from the delay circuit, as a count clock, and further performing counting based on an upper count clock output from a lower counter. A modification unit modifies a logic state of a count clock to a predetermined state when the count clock of the upper counter is switched.

Abstract: In a solid-state imaging device, each of a plurality of switches is connected between a pulse output terminal of each delay unit and a pulse input terminal of the next-stage delay unit. Each of a plurality of switches is connected between the pulse output terminal and the pulse input terminal of each delay unit. A plurality of switches is turned on and a plurality of switches is turned off in conjunction with an oscillation operation, and a plurality of switches is turned off and a plurality of switches is turned on in conjunction with a holding operation.

Abstract: A circuit for serializing bits including a clock circuit and a serializer. The clock circuit may be configured to generate a plurality of clock signals from a received master clock signal. A plurality of bits may be transmitted to the serializer in response to a transition of a first clock signal. The serializer may comprise a system of latches and a rotary circuit. The system of latches may be configured to receive a first half of the plurality of bits in response to a first transition of a second clock signal and to receive a second half of the plurality of bits in response to a transition of a third clock signal. The rotary circuit may be configured to receive the plurality of bits from the system of latches and to output each bit at a particular time based on a plurality of rotary clock signals.

Abstract: A delay circuit includes a pulse generation unit configured to generate a pulse signal, which is activated in response to an input signal and has a pulse width corresponding to delay information, and an output unit configured to activate a final output signal in response to a deactivation of the pulse signal.

Abstract: Provided are a ramp wave generation circuit and a solid-state imaging device in which a pulse output unit includes a delay part including a plurality of delay units that delay and output an input signal, and a delay control part that controls a delay time by which the delay unit delays the signal, and outputs a plurality of signals having logic states corresponding to logic states of signals output by the delay units, a time difference between timings at which the logic states of the respective signals are changed being a time corresponding to the delay time.

Abstract: An integrated circuit is equipped with a reception mixer and a signal generator. A multistage delay circuit generates a plurality of clock pulses in response to a reception carrier signal. A phase detection unit detects differences between a voltage level of a specific clock pulse and voltage levels of a predetermined number of clock pulses generated prior to the specific clock pulse to thereby detect a predetermined phase of the specific clock pulse. A selector of a clock generation unit outputs a plurality of selection clock pulse signals respectively having a plurality of phases from the clock pulse signals. A first signal synthetic logic circuit performs logical operations on the selection clock pulses to thereby generate local signals supplied to the reception mixer.

Abstract: A structure for performing cross-chip communication with mesochronous clocks. The structure includes: a data delay line; a remote clock delay line; a structure that captures at least one value of a state of a delayed remote clock signal on the remote clock delay line; and a control that influences a delay associated with the data delay line and the remote clock delay line.

Abstract: A semiconductor device includes an analog circuit with a first delay variation in response to a variation in a power supply potential, and a digital circuit with a second delay variation smaller than the first delay variation. The analog circuit is connected to a first power supply potential. The digital circuit includes a detecting circuit detecting a first delay caused by a first circuit connected to the first power supply potential, and a second circuit generating a control signal to control the analog circuit, the second circuit being connected to a second power supply potential whose potential variation is smaller than the first power supply potential. A second delay caused by the second circuit is controlled in correlation to the first delay.

Abstract: According to an embodiment, a semiconductor integrated circuit includes a first clock domain driven at a first frequency, a second clock domain adjacent to the first clock domain and driven at a second frequency which is different from the first frequency, a signal line provided between the first clock domain and the second clock domain, first and second DF/Fs connected to the first signal line and provided for the first clock domain and the second clock domain respectively and first and second multiplexers provided in correspondence with the first and the second DF/Fs respectively, to select one of the first frequency and the second frequency and output the selected frequency to the first and the second DF/Fs.

Abstract: A method for source synchronous communication. The method includes dynamically adjusting a delay that is applied to a data signal and a remote clock signal until a delayed remote clock signal is synchronized with a local clock signal, and capturing data from a delayed data signal associated with the delay in a local domain.

Abstract: An integrated circuit is equipped with a reception mixer and a signal generator. A multistage delay circuit generates a plurality of clock pulses in response to a reception carrier signal. A phase detection unit detects differences between a voltage level of a specific clock pulse and voltage levels of a predetermined number of clock pulses generated prior to the specific clock pulse to thereby detect a predetermined phase of the specific clock pulse. A selector of a clock generation unit outputs a plurality of selection clock pulse signals respectively having a plurality of phases from the clock pulse signals. A first signal synthetic logic circuit performs logical operations on the selection clock pulses to thereby generate local signals supplied to the reception mixer.

Abstract: Provided is a clock timing adjustment device for adjusting a time difference of clocks and a delta-sigma modulator. The clock timing adjustment device includes a power detection unit and a timing adjustment unit. The power detection unit receives input signals which are generated using pairs of first and second clocks having a plurality of clock time differences and respectively correspond to the clock time differences, detects powers of the input signals, and outputs a control signal corresponding to a clock time difference where the power is minimized. The timing adjustment unit receives a reference clock and the control signal and outputs the first and second clocks having the clock time difference where the power is minimized from the reference clock according to the control signal.

Abstract: An inter-phase skew detection circuit includes a frequency division circuit that frequency-divides N-phase clocks to be measured at predetermined timings so as to generate N+2 frequency-divided clocks; a phase comparison target clock generation circuit that generates N phase comparison target clocks by using predetermined N frequency-divided clocks among the N+2 frequency-divided clocks; a phase comparison reference clock generation circuit that generates N reference clocks by using the N+2 frequency-divided clocks, in accordance with predetermined combinations between the N+2 frequency-divided clocks and an operation criterion; and a phase comparison circuit that detects respective phase differences between the N phase comparison target clocks and the corresponding N reference clocks.

Abstract: In a multi-supply-voltage semiconductor device including multiple blocks each of which has independent clock circuit, and operating with variable power supply, variable delay circuit which changes the amount of delay in accordance with the voltage value of the variable power supply is provided to a clock signal supplied to several blocks from clock generator circuit. This can reduce clock skew between the blocks even when the power supply voltage of variable power supply is changed.

Abstract: A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the circuit. A phase monitor connects to the circuits. The phase monitor detects phase differences between signals output by the circuits. A controller connected to the delay circuitry, the phase monitor, and the controller adjust the delay circuitry to compensate for the phase differences.