Abstract: A delay line including analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setting. The fine delay portion generates a threshold voltage based on a predetermined fine delay setting. A comparator compares the coarse delay ramp signal voltage with the fine delay threshold voltage and generates an output clock signal when the ramp signal voltage surpasses the fine delay threshold voltage. The coarse delay is linearly adjustable based on a 32-bit binary input signal and the fine delay is binary-weight adjusted based on a 5-bit binary input signal. Both the coarse and fine delay portions are controlled by delay line control circuitry which compares a feedback version of the output clock signal with the input clock signal and provides control signals to increment or decrement coarse and fine delay in the delay line.

Abstract: A precision timing generator and an associate method provide a precise clock signal based on a reference clock signal. Using the reference clock signal in a phase locked loop or delay locked loop, a number of clock signals of equal frequency are generated separated consecutively by a known phase. Two of these clock signals of consecutive phases are selected for interpolation for higher precision according to predetermined weights. The resulting interpolated clock signal has a phase offset that is intermediate between the selected clock signals in proportion to the predetermined weights. In one implementation, a second interpolated clock signal is created by selecting and weighting a second group of clock signals using independent selection and weights. The two interpolated clock signals are then combined by logic operations to provide a precise clock signal of predetermined duty cycle and phase.

Abstract: Memory devices used to control delay line circuitry, and that may be implemented in one embodiment to provide a self-tuning delay line device using empirical calibration technique/s to achieve a desired signal delay. The memory control device may be implemented to store electrical characteristics of the delay line circuitry during testing to enable self-calibration of the delay line circuitry.

Abstract: A method and apparatus for a frequency-based slope-adjustment circuit block are described herein.

Abstract: A method and apparatus is disclosed for adjusting at least one of a supply voltage and a clocking frequency applied to digital circuitry of a computing device, wherein the digital circuitry comprises a critical path circuit. A propagation delay frequency representing a propagation delay of the critical path circuit is generated, and a frequency error signal is generated representing a difference between a reference frequency and the propagation delay frequency. At least one of the supply voltage and the clocking frequency is adjusted in response to the frequency error signal.

Abstract: A delay device has series-connected multiplexers in a differential form. First connections of the multiplexers are connected to the output of an upstream multiplexer. Second inputs of the multiplexers are connected to the input connection to which the signal to be delayed can be supplied. A control signal controls the switch setting of one of the multiplexers such that its output is connected to the input of the delay device. The other multiplexers have the other switch setting. In consequence, a specific delay time is set for the delay device. The multiplexers have four current paths which are coupled in pairs. One of the current path pairs can be decoupled from the current source via a transistor.

Abstract: A variable delay line comprises a first blender delay configured to provide a first signal, a second blender delay configured to provide a second signal complementary to the first signal, and a coarse delay configured to delay the first signal if an even number of coarse delay elements are selected and delay the second signal if an odd number of coarse delay elements are selected.

Abstract: A digital DLL device is provided which can reduce an error with respect to a target delay amount. The device provides a delay to an input clock signal so as to equally divide a clock cycle T thereof into N parts, and includes first variable delay sections and second variable delay sections, each of which is formed of an arbitrary number of unit delay buffers connected in series with one another. A phase comparison section makes a compare between the phase of the input clock signal and the phase of an output signal which is the input signal having been delayed while passing through all the first and second variable delay sections, and outputs a result of the comparison. A delay control section calculates a total number of unit delay buffers S required based on the phase comparison result, sets a quotient Q of S divided by N to be the number of unit delay buffers for each of the first variable delay sections, and allocates a remainder R of S divided by N to the second variable delay sections, respectively.

Abstract: The present invention provides a semiconductor integrated circuit device equipped with at least one pulse generator which generates a pulse of a pulse with shorter than a rising time up to the full amplitude of a transfer signal. A first signal and a second signal supplied from outside through a first signal path and a second signal path are respectively transferred to the pulse generator. When a rising time up to the full amplitude at any one of buffers in the first signal path and the second signal path is longer than a pulse width of a pulse to be formed by the pulse generator, the difference in phase between the first signal and the second signal is caused to correspond to a pulse width of a first pulse.

Abstract: An analog finite impulse response (“FIR”) filter generates a continuous time output using a chain of tunable delay elements. The tunable delay elements generate a time delay in an input signal. A calibration circuit, consisting of a control loop, tunes the delay elements to provide precision in the time delay response of the delay elements. The control loop generates a delay adjustment, based on the period of reference signals, and the phase adjustment is used to tune the parameters of the delay elements. The tunable delay elements may comprise any combination of transmission lines, lumped elements and semi-lumped elements.

Abstract: A circuit including a sensing circuit, which includes a first delay circuit and a tuning circuit. The tuning circuit includes a sense counter and a reference counter. The sense counter is coupled to the first delay circuit and is configured to count a number of oscillations provided by the first delay circuit and provide a notification to the tuning circuit when the sense counter reaches a threshold value. The reference counter is coupled to the sense counter and a reference clock. The reference counter is configured to store a reference time which represents a time elapsed for the sense counter to reach the threshold value. Also included in the circuit is a second delay circuit coupled to the sensing circuit.

Abstract: Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers have a smaller phase difference, thereby providing finer delay adjustments. Multiple stages of phase mixers can be provided in digital delay-locked loop circuitry to provide additional hierarchical delay adjustment.

Abstract: A circuit and method of generating delayed tap signals can adjust a delay difference by interpolating two input clock signals as indicated by an offset information signal. In the circuit, first and second tap signals are generated by interpolating first and second clock signals in response to the offset information. A delay difference between output tap signals is adjusted by an amount indicated by the offset information. Thus, tap signals having a fine delay difference can be obtained by adjusting the offset information.

Abstract: A current controlled delay circuit is disclosed. Two currents of constant sum are generated to control the delay of the circuit. The circuit includes a differential pair to switch one of the two currents from one leg of the circuit to another leg of the circuit. The circuit includes a cross-coupled pair to switch the other of the two currents from one leg of the circuit to another leg of the circuit. The circuit may include a fixed or variable load.

Abstract: A circuit modification portion modifies circuit information of an integrated circuit depending on a result of a timing test at a timing test portion to presume delay information at a delay presumption portion by modeling the circuit relating to its modified circuit information. Thereafter updating the circuit information and delay information of the integrated circuit at an information update portion to re-test the timing. This allows to carry out a timing analysis/test of the modified circuit without designing layout with the modified circuit information, which is required in a conventional design method. As a result, the number of designing the layout in the integrated circuit design is reduced to shorten time required for the layout design, which allows to shorten time required for the layout design process (layout design, timing analysis/test, and timing adjustment).

Abstract: The present invention relates to an integrated circuit device and method of adjusting capacitance of a node of an integrated circuit In one embodiment, the device comprises a first digital input, a first parasitic capacitance block, a first output, a second digital input, a second parasitic capacitance block and a second output. The first parasitic capacitance block includes an inverter, a variable capacitance element, and a wire capacitance element. The first parasitic capacitance block has a capacitance that is a function of the first digital input. The first output is responsive to the first parasitic capacitance block, and the second output is responsive to the second parasitic capacitance block.

Abstract: Delay line circuits and methods include a series of unit delay cells, a respective one of which includes an input and an output that are sequentially connected such that an output of a preceding unit delay cell is connected to an input of a succeeding unit delay cell. At least two of the unit delay cells in the series are sequentially activated in response to an activation signal. The sequential activation may be performed by a control circuit that is connected to the series of unit delay cells.

Abstract: A delay circuit, including a plurality of delay blocks connected in series, each having a first complementary input terminal to which a first complementary signal is inputted, a second complementary input terminal to which a second complementary signal is inputted, and a complementary output terminal which outputs a third complementary signal delaying by selecting one of the first and second complementary signals based on logic of a delay selection signal, the complementary output terminal of the delay blocks except for the delay block of last stage being connected to the second complementary input terminal of the subsequent delay block, respectively, a complementary delay signal delaying the first complementary signal in accordance with logic of the delay selection signal being outputted from the complementary output terminal of the delay block of last stage, and the same first complementary signal is inputted to the first complementary input terminals of the plurality of delay blocks, respectively.

Abstract: A clock generator circuit includes a plurality of phase delay elements connected in series. The phase delay elements provide delayed output clock signals relative to an input clock signal. The circuit employs a loop-back path that connects the output of the final phase delay element to the input of the first phase delay element. The loop-back path enables the circuit to maintain an accurate overall phase delay between the input clock signal and the output clock signal generated by the final phase delay element. When implemented to support differential clock signals, the inverted outputs of the phase delay elements also serve as delayed clock signals. In accordance with one practical embodiment, the clock phase generator circuit provides evenly distributed clock phases over one clock period.

Abstract: In a shift clock signal generating apparatus, a delay line includes a plurality of unit delay elements connected in cascade. A reference clock signal propagates in the delay line while being successively delayed by the unit delay elements. Switches have first ends connected with output terminals of the unit delay elements respectively, and second ends connected with a shift clock signal output path. When specified one among the switches is in its on position, a delayed clock signal which results from delaying the reference clock signal by a prescribed time interval is transmitted via the specified switch to the shift clock signal output path as a shift clock signal. The specified one among the switches is determined on the basis of data representing a phase difference of the shift clock signal from the reference clock signal. The specified switch is set in its on position.

Abstract: A variable delay circuit delays a first input signal in accordance with a delay adjustment signal and outputs the delayed signal as a first delay signal. A decision circuit outputs, in accordance with a phase difference between the first delay signal and a clock signal, an increase or decrease signal. A delay adjustment circuit generates, in accordance with the increase or decrease signal, the delay adjustment signal to adjust the variable delay circuit. Accordingly, even when a discrepancy in timing between the first input signal and clock signal occurs due to a change in temperature, a fluctuation in voltage or the like, a first receiver circuit can receive the first input signal in synchronization with the clock signal without fail. Since the valid period of the first input signal relative to the clock signal can be minimized, the transmission rate of the first input signal can be increased.

Abstract: A programmable compensated delay for a double data rate (DDR) synchronous dynamic random access memory (SDRAM) interface is provided. A programmable compensated delay apparatus includes a reference delay calibration circuit for providing a measured number of delay elements in one cycle. A programmable delay register provides a desired delay value. A conversion logic is coupled to the reference delay calibration circuit and the programmable delay register for receiving both the measured number of delay elements in one cycle and the desired delay value. The conversion logic provides a number of required delay elements. A delay circuit is coupled to the conversion logic for receiving the number of required delay elements and providing the desired delay. A SDRAM control logic provides a refresh start signal to the reference delay calibration circuit for updating the delay circuit during each DRAM refresh. The DQS clock strobe on the DDR SDRAM is applied to the delay circuit and is delayed by the desired delay.

Abstract: A voltage controlled delay line having a plurality of delay cells is used to delay a first reference clock by a predetermined delay time to generate an in-phase first delay clock and to delay a second reference clock by the predetermined delay time to generate an in-phase second delay clock. Each delay cell has a first input port, a second input port, a first output port, and a second output port. The first output port of one delay cell and the second input port of another one delay cell having the same phase are electrically connected or the second output port of one delay cell and the first input port of another one delay cell having the same phase are electrically connected so that the first and second input port of each delay cell are not connected to the first and second output port of an adjacent delay cell.

Abstract: A delay device has multiplexers connected in series in a differential configuration. First connections of the multiplexers are connected to the output of an upstream multiplexer. Second inputs of the multiplexers are connected to the input connection to which the signal that is to be delayed can be supplied. A control signal controls the switch position of one of the multiplexers such that its output is connected to the input of the delay device. All the other multiplexers are in the other switch position. This results in the delay device producing a specific delay time. When used in a delay control loop, this results in a jitter-free output signal, even if the operating conditions are fluctuating.

Abstract: A method for “match-delay” buffer insertion is provided to add delays at a node without changing the input capacitance of the node as seen by the upstream node. In one embodiment, a method for inserting a delay in a node in an electrical design associated with a logic gate includes: adding the delay at the node by adding a new logic gate before the node where the new logic gate is the same cell type as the logic gate and is positioned near the logic gate. The method may further include: determining if the delay can be added by adding a new logic gate before the node, and if a new logic gate cannot be added before the node, adding the delay by adding a new logic gate after the logic gate where a combination of the logic gate and the new logic gate giving the delay to be added.

Abstract: A system and method are provided for controlling the phase of a voltage controlled oscillator output. The method comprises: accepting a plurality of VCO outputs coarsely differentiated by phase; selecting one of the VCO outputs; finely modifying the phase of the selected VCO output; and, supplying the phase modified VCO output. In one aspect, accepting VCO outputs coarsely differentiated by phase includes: accepting a first VCO output (I0); accepting a second VCO output (I1), differentiated approximately 90 degrees from the first VCO output; accepting a third VCO output (Q0), differentiated approximately 90 degrees from the second VCO output; and, accepting a fourth VCO output (Q1), differentiated approximately 90 degrees from the third VCO output. Finely modifying the phase of the selected VCO output includes modifying the selected VCO output in the range between +45 and −45 degrees. In one aspect, the output is modified in 16 discrete steps.

Abstract: A delay circuit has a delay that is consistent under varying process and temperature conditions. The delay through a delay path is controlled by inserting resistors on the pull-up and pull-down paths of the delaying inverters. Each resistor has a resistance value that is determined by a varying a number of enabled similarly-sized transistors coupled in parallel across the resistor, rather than by varying the size of a single transistor. In one embodiment, a first transistor in each resistor is always enabled, while additional transistors are enabled using select signals. In one embodiment, the select signals are provided by configuration memory cells in a PLD. Other embodiments include additional delay paths and a multiplexer circuit that selects one of the delay paths. The described delay circuit is particularly useful in a DLL trim unit, where variations between resistors can cause jitter and locking problems in the DLL.

Abstract: The invention features an output driver for integrated circuits that includes a driver that has a data input connected to the integrated circuit, a data output connected to a transmission line leading to the external circuit, and impedance adjusting means for adjusting the output impedance of the driver circuit according to determinable impedance adjusting data. The output driver also includes a dummy circuit having a dummy driver circuit and transmission line, and an impedance control circuit for controlling the output impedance of the driver circuit. The impedance control circuit controls the impedance of the driver circuit by determining the impedance adjusting data (necessary for matching the output impedance of the dummy driver circuit to the characteristic impedance of the dummy transmission line and outputting the determined impedance adjusting data to the impedance adjusting means of the driver circuit.

Abstract: An approach for precise signal interpolation. For one aspect, each of the linear resistive elements in a first array of selectable linear resistive elements receives a first input signal. Each of the linear resistive elements is coupled to provide an output signal on a first output signal line. A variable bandwidth-compensating circuit is coupled to the first output signal line to compensate the bandwidth of the output signal.

Abstract: An edge multiplier circuit comprises a chain of N phase-looped delay cells (130, 131, 132, 133, 134). An order of cells to be delayed is determined by action loops. A first action loop (116, . . . , 128) is utilized for values of j varying from 1 to N, each corresponding to a total delay equal to j times an elementary delay (Te) of a cell. The delay is applied to the chain of N delay cells. An action of the first loop comprises a second action loop (118, . . . , 127) for values of i varying from 1 to N, each corresponding to a rank of a cell in said chain. An action of the second loop calculates a delay error (a (j, i)) output from the cell of rank i relative to an ideal delay that distributes the total delay of the chain equally to each cell.

Abstract: A delay locked loop having short acquisition time to lock. The voltage controlled delay line includes a series of stages with the delay of each stage being variable. However, the initial stage has a fixed delay to avoid latching of the final stage to the first stage of the next cycle. The phase detector has additional logic gating to suppress an extraneous up or down signal during the acquisition time.

Abstract: A delay line receives an input clock signal and includes a cascaded plurality of unit delay circuits. A mode register set stores a value indicative of a column-address-strobe (CAS) latency of the memory device, and an adjustment circuit varies a delay time of the unit delay circuits according to the CAS latency stored in the mode register set. A phase detector detects a phase difference between the input clock signal and an output clock signal of the delay line, and a control circuit which controls an enabled state of the unit delay circuits according to an output of said phase detector.

Abstract: A precision signal delay apparatus and method for introducing time delay to a signal. Precision delay is introduced by a pair of delay locked loops (DLLs) connected in series each with selectable delay (i.e., a Vernier-type circuit). Nonuniformity in the precision delay is compensated with a delay compensation circuit. The apparatus and method may be used for phase shifting, data delay, precision pulse width modulation, and precision time windowing.

Abstract: A clock synchronization circuit. The clock synchronization circuit composed of a digital DLL outputs a clock signal delayed by a variable delay line and a clock signal delayed by an additional delay cell, mixes the two clock signals, and outputs an internal clock signal having a smaller delay than a delay time of a delay cell, thereby rapidly precisely synchronizing an external clock signal and the internal clock signal. In addition, a driving unit and a control unit for adjusting a duty cycle are provided to set up a ratio of 50%, thereby improving operation performance.

Abstract: A clock distribution network is provided which includes variable-delay element. The variable-delay element consists of an inverter and a digitally adjustable resistor. The digitally adjustable resistor includes a plurality of transistors provided in plurality of rows and a plurality of columns. The variable-delay element functions logically equivalent to the inverter in which the delay is varied in accordance with the variance in resistance of the digitally adjustable resistor.

Abstract: The present invention relates to an adjustable clock skew apparatus and method for generating clock signals, which resolves the drawbacks of costing a user much time and effort to adjust clock skews of all components on a motherboard. In order to accomplish the object, the present invention proposes three operating modes: hardware setup, software setup or a mixture of hardward and software setup. A user just needs to adjust a plurality of exterior switches or to adjust a Basic Input Output System (BIOS) of the motherboard to modify the parameter of clock skew, and clock signals with necessary clock skews will be obtained.

Abstract: A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.

Abstract: A delay line comprised of analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setting. The fine delay portion generates a threshold voltage based on a predetermined fine delay setting. A comparator compares the coarse delay ramp signal voltage with the fine delay threshold voltage and generates an output clock signal when the ramp signal voltage surpasses the fine delay threshold voltage. The coarse delay is linearly adjustable based on a 32-bit binary input signal and the fine delay is binary-weight adjusted based on a 5-bit binary input signal. Both the coarse and fine delay portions are controlled by delay line control circuitry which compares a feedback version of the output clock signal with the input clock signal and provides control signals to increment or decrement coarse and fine delay in the delay line.

Abstract: A method for generating a variable delay of a signal, including: providing a clock indicating a sequence of sample times at regular intervals and receiving a sequence of input samples representing input values of the signal at respective sample times indicated by the clock. The method further includes determining the delay with a temporal resolution substantially finer than the clock interval to be applied to the signal at each of the respective sample times. For each of the sample times, responsive to the respectively-determined delay, one or more of the input samples are processed so as to generate a corresponding output sample representing a delayed output value of the signal at the sample time.

Abstract: The variable frequency oscillator is capable of operation at a low power supply voltage and oscillating at a high frequency. A phase locked loop and a clock synchronizer use the variable frequency oscillator and have a wide oscillation frequency range. The variable frequency oscillator has plural delay cells which are cascaded and the output of the final stage delay cell is fed back to the input of the first stage delay cell. Each of the delay cells includes a differential amplifier and a positive feedback circuit, connected with input and output terminals intersecting with each other. The feedback circuit has complementary amplifiers each having an input terminal formed by connecting together gates of a pMOS and an nMOS transistor and an output terminal formed by connecting together the drains thereof.

Abstract: A fixed-length delay generation circuit comprises a first variable delay circuit (VDC), a clock generation circuit, a VDC group including one or more second VDCs, and a delay controller. The clock signal is input to a second VDC disposed at the initial stage in the VDC group. The delay controller outputs a signal by which delay amount in the first and second VDCs are made smaller when a difference between phases of a delay clock signal output from the VDC group and of the clock signal generated by the clock generation circuit is greater than a predetermined value. The delay controller outputs a signal by which delay amount in the first and second VDCs are made larger when the difference between phases of a delay clock signal output from the VDC group and of the clock signal generated by the clock generation circuit is smaller than such value.

Abstract: A synchronous delay circuit apparatus include two sets of synchronous delay circuits 100, 101 each including a first delay circuit chain for period measurement in which input clocks propagate and a second delay circuit chain for period reproduction and delay detection circuits 5, 7 for detecting the propagation delay time caused in propagating clocks from an input node to an output node of a clock propagation path to issue a control signal for halting propagation of the input clock signals to the respective synchronous delay circuits. A delay circuit 6 is introduced in an input of at least one of the delay detection circuits to differentiate a delay time detected in one delay detection circuit 7 from a delay time detected by the other delay detection circuit 5 to differentiate detected period from the delay detected in the other delay detection circuit 5.

Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Abstract: A control signal generation circuit according to the present invention includes a plurality of control circuits supplying different internal control signals as outputs, respectively, and a common delay circuit. The common delay circuit includes a plurality of delay circuits for delaying a control signal serving as a reference. These delay circuits are connected in series and output signals of respective delay circuits can be taken out through taps provided corresponding thereto. Each of the plurality of control circuits sets a signal level of a corresponding internal control signal according to the change in a signal level of a corresponding tap.

Abstract: An apparatus is described comprising a current source and a pair of transistors coupled to the current source. A pair of variable loads are coupled to the pair of transistors such that a first of the pair of transistors drives a first of the pair of variable loads and a second of the pair of transistors drives a second of the pair of variable loads. Each of the pair of variable loads are coupled to a high gain input and a low gain input. Another apparatus is described comprising an oscillator having a high gain input and a low gain input. The oscillator comprises a series of inverters where each inverter output is coupled to the next inverter input in the series. At least one of the inverters comprises a current source and a pair of transistors coupled to the current source.

Abstract: A stable internal clock signal generator capable of suppressing an oscillation caused by a fluctuation in a power source or the like. A shift register 14 stores a binary comparison result indicating whether a phase obtained by a comparison carried out through a phase comparing circuit 13 past (n+1) times is advanced or delayed, a phase control circuit 15 outputs, as a phase control signal to a phase variable circuit 12, the larger number of comparison results obtained by carrying out the comparison (n+1) times, and the phase variable circuit 12 adjusts the phase of an internal clock signal intclk based on the input phase control signal.

Abstract: In an high-frequency LSI chip, a clock signal generating circuit which establish accurate synchronism between an input clock signal and an internal clock signal to prevent an input circuit to cause a synchronization shift. The clock signal generating circuit includes an input circuit for amplifying an input signal and outputting an amplified signal as a first internal signal; a variable delay circuit, on the basis of a control signal, for delaying the first internal signal and outputting a delayed signal as a second internal signal; a phase comparator for finding a phase difference between the input signal and second internal signal and outputting a phase difference signal indicative of the phase difference; and a control circuit for generating the control signal on the basis of the phase difference signal. Thereby the influences of a delay caused by the input circuit, which would not be able to be avoided in the prior art, can be avoided and thus the accurate internal clock signal can be generated.

Abstract: A semiconductor integrated circuit is provided that achieves a lesser degree of inconsistency in the delay time of clock signals that are internally provided. An input clock signal distributed via an input clock supply path is provided to individual timing adjustments circuits. The timing adjustment circuits are each constituted by providing a wiring pattern having serial resistors and gaps in a circuit correction area. The wiring pattern of the semiconductor integrated circuit is corrected by employing a focused ion beam apparatus to achieve an adjustment so that internal input clock signals at the same phase are obtained from the individual timing adjustment circuits. Using the wiring pattern having undergone the adjustment, a semiconductor integrated circuit is manufactured as a product.

Abstract: A control signal generation circuit according to the present invention includes a plurality of control circuits supplying different internal control signals as outputs, respectively, and a common delay circuit. The common delay circuit includes a plurality of delay circuits for delaying a control signal serving as a reference. These delay circuits are connected in series and output signals of respective delay circuits can be taken out through taps provided corresponding thereto. Each of the plurality of control circuits sets a signal level of a corresponding internal control signal according to the change in a signal level of a corresponding tap.

Abstract: A semiconductor device provided with a replica circuit functioning as an equivalent circuit to that of a path configuration selected as a critical path in the semiconductor circuit and an adjustable delay device for example between an output side of the replica circuit and a phase comparator, the delay value of the delay device being adjustable after production of the chip to a value enabling the replica system including the replica circuit to reliably operate with a margin from the critical path delay of the semiconductor circuit, whereby it becomes possible to prevent setting of an excessive margin and becomes possible to increase the margin when the margin ends up smaller than expected and therefore it becomes possible to flexibly and efficiently configure the replica circuit, and a method of constitution of the same.