Abstract: In an embodiment, a unit delay circuit comprises a first path configured to delay a first input signal to output a first output signal when a selection signal is inactivated, a second path configured delay a second input signal to output a second output signal when the selection signal is inactivated, and a third path configured to delay the first input signal to output the second output signal when the selection signal is activated.

Abstract: The present utility model relates to an ultra-low voltage two-stage ring voltage-controlled oscillator applied to a chip circuit. The oscillator includes two-stage delay units. The oscillator includes two delay units that are connected end-to-end, and adjusts a working frequency by adjusting delay time of the delay unit. The delay unit includes PMOS transistors M1, M2, M3, and M4, NMOS transistors M5, M6, M7, and M8, and a load capacitor CL. The two-stage ring voltage-controlled oscillator of the present utility model uses a substrate feed forward bias structure, reduces a threshold voltage of a transistor, reduces a supply voltage, reduces power consumption, has a large tuning range, and is particularly suitable for a system that works at a low supply voltage.

Abstract: The invention provides a clock delay adjusting circuit based on edge addition and an integrated chip thereof.

Abstract: Memory devices may receive data from data processing devices for storage and processing during write operations. The received data may be accompanied by a data strobing signal that informs the memory device that data available in the bus is ready for latching. The data strobing signal may be provided via a tri-stateable or bidirectional connection and, as a result, during initialization of a write operation, the input circuitry may suffer from metastability during an initial transient period. The present application discusses methods and systems that may mitigate metastability by preventing invalid states in the input circuitry when data strobing signal is invalid or disabled. Certain embodiments determine if the data strobing signal is a valid input and, accordingly, adjust the received signal to a fixed value or to a previously received value. The use of latches and differential amplifiers to perform these functions is also discussed.

Abstract: An integrated circuit includes a clock generator to generate a first clock signal, a delay circuit to generate a second clock signal as a delayed version of the first clock signal, and a plurality of series-connected delay elements having a plurality of outputs, wherein each output from an initial output to a last output is configured to provide the second clock signal delayed by an increasing number of series-connected delay elements. The circuit includes a plurality of flip-flops, wherein a first input of each flip flop is coupled to receive the first clock signal and a second input of each flip flop from an initial flip-flop to a last flip-flop is coupled to receive a corresponding output of the series-connected delay elements from the initial output to the last output, respectively. The circuit includes a plurality of sticky flops, each corresponding to a flip-flop of the plurality of flip-flops.

Abstract: Embodiments of the present invention provide a time-to-digital converter, where the time-to-digital converter includes a delay unit, a first sampling unit, and a second sampling unit. The delay unit is connected to the first sampling unit and is configured to receive a first clock signal and delay the first clock signal; the first sampling unit is configured to perform sampling on the first clock signal and generate a first phase signal, so that a first phase-locked module adjusts a frequency of the first clock signal; the delay unit is further connected to the second sampling unit and is configured to receive a frequency-adjusted first clock signal and delay the frequency-adjusted first clock signal; and the second sampling unit is configured to perform sampling on the frequency-adjusted first clock signal and generate a second phase signal.

Abstract: In various embodiments, a printed circuit arrangement may be provided. The printed circuit arrangement may include a processor circuit. The printed circuit arrangement may further include a printed main circuit arrangement in electrical connection with a first input node of the processor circuit. The printed main circuit arrangement may be configured to receive at least one input signal and generate a main circuit signal based on the at least one input signal after a first delay from receiving the at least one input signal. The printed circuit arrangement may further include a printed reference circuit arrangement in electrical connection with a second input node of the processor circuit. The printed reference circuit arrangement may be configured to receive a further input signal, may have a second delay and may be configured such that the second delay adapts to the first delay.

Abstract: A system comprises a semiconductor integrated circuit including a data processing unit that operates in any of a plurality of states, and a selection unit that selects a state from the plurality of states in accordance with a voltage supplied from a power supply unit and makes the data processing unit operate in the selected state, and a power supply unit including a control unit that starts supplying a voltage to the semiconductor integrated circuit based on an initial voltage value setting at startup and makes a voltage to be supplied transit to a predetermined voltage based on information of voltage value in response to a supply voltage having reached the initial voltage value, wherein the selection unit switches the data processing unit to a predetermined state when a supplied voltage has reached the predetermined voltage value from the initial voltage value.

Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

Abstract: In an approach for calibrating a delay line having a plurality of taps, a first clock signal is input to the delay line. A second clock signal is input to a reference circuit having a plurality of taps. In response to determining that output signals of selected taps of the delay line and reference circuit do not align, a next tap of the reference circuit is selected, to determine whether or not the output signals align. In response to determining that the output signals align, reference tap data indicative of the current reference tap is stored in association with a delay tap number of the current delay tap. A next tap of the delay line is selected to determine whether or not the output signals align.

Abstract: A method and apparatus for generating a wave shaped pulse electronic signal of a predetermined format from a square pulse signal generator. A signal is applied from the square pulse generator to circuitry having a plurality of transmission lines. Each transmission line having a certain length creating a certain signal time delay and signal reflection for a signal applied to the circuitry from the square pulse generator so as to create a delay pulse from each transmission line. Each delay pulse is combined from each transmission line to generate the wave shaped pulse electronic signal of a desired predetermined format.

Abstract: A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to Nth (N is an integer equal to or greater than 2) delay units with binary weights. The delay value control circuit includes a replica delay unit replicating an Ath (2?A?N) delay unit; and a delay control unit configured to compare a phase of a first output signal generated from delaying an input signal with an A?1th delay unit and a phase of a second output signal generated from delaying the input signal with the Ath delay unit and the replica delay unit and configured to control a delay value of the Ath delay unit using a comparison result.

Abstract: A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to Nth (N is an integer equal to or greater than 2) delay units with binary weights. The delay value control circuit includes a replica delay unit replicating an Ath (2?A?N) delay unit; and a delay control unit configured to compare a phase of a first output signal generated from delaying an input signal with an A?1th delay unit and a phase of a second output signal generated from delaying the input signal with the Ath delay unit and the replica delay unit and configured to control a delay value of the Ath delay unit using a comparison result.

Abstract: A polyphase clock generator for use in clock data recovery (CDR) includes a phase selector and a four-to-eight phase converter further including a plurality of delay paths, switches, and phase interpolators. The switches switch over the delay paths so as to select a group of delay paths suited to a clock frequency which is determined in advance. A plurality of reference clock signals with a predetermined phase difference (e.g. 90°) therebetween is selectively delayed while passing through the selected group of delay paths. The phase interpolators interpolate the delayed reference clock signals, passing through the selected group of delay paths, into the reference clock signals, thus generating a plurality of clock signals. The phase selector selectively combines the clock signals with a mixing ratio according to clock data recovery, thus generating a plurality of recovery clock signals with a precise phase difference (e.g.) 45°) therebetween.

Abstract: A digital controlled delay line (DCDL) includes a signal gated delay line generating a delayed signal, a phase selector, a controller, an input signal and an output signal. The phase selector includes logic gates to couple the delayed signal from the signal gated delay line to the output signal. Preventing signal propagation to unused cells and logic gates reduces power consumption. The number of logic gates in the phase selector the delayed signal passes through is log2 p, wherein p is the number of the signal gated delay cells in the signal gated delay line and p is a power of 2. The number of logic gates is (integer part of log2 p)+1, wherein p is the number of the signal gated delay cells and p is not a power of 2.

Abstract: A slew rate control circuit configured to control a slew rate of driver circuit comprises a clock delay module that receives a half-rate clock signal and that includes a plurality of delay cells configured to generate a plurality of respective delayed clock signals each having a different time delay from one another. A driver module includes a plurality of multiplexers in electrical communication with a respective data cell to receive a corresponding delayed clock signal. The multiplexers are configured to output a respective full-rate data stream in response to the delayed clock signal. The slew driver module further includes an output stage circuit in electrical communication with each multiplexer to combine each full-rate data stream and to generate a final step-wise driving signal that controls the slew rate.

Abstract: A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to Nth (N is an integer equal to or greater than 2) delay units with binary weights. The delay value control circuit includes a replica delay unit replicating an Ath (2?A?N) delay unit; and a delay control unit configured to compare a phase of a first output signal generated from delaying an input signal with an A?1th delay unit and a phase of a second output signal generated from delaying the input signal with the Ath delay unit and the replica delay unit and configured to control a delay value of the Ath delay unit using a comparison result.

Abstract: A delay cell architecture is provided herein with improved noise performance and increased output swing, while consuming less power and area than conventional delay cell architectures. In one embodiment, the delay cell described herein may include a pair of input transistors, a pair of cross-coupled transistors, a pair of current source transistors, at least one swing limiting transistor and an RC filter. The at least one swing limiting transistor is coupled between the output nodes of the delay cell for controlling the output swing and keeping the current source transistors in saturation. Phase-induced jitter is reduced by connecting the RC filter directly to the mutually-coupled source terminals of the current source transistors. Deterministic jitter is reduced by using a relatively large resistor and relatively small capacitor within the RC filter design. Such a design reduces the amount of area consumed by the delay cell without sacrificing noise performance.

Abstract: A first timing comparator TCP1 latches a data signal at a timing that corresponds to each edge of a first strobe signal. A first delay element delays a first strobe signal so as to output a first delayed strobe signal. A first clock recovery unit makes a comparison between the phase of the first delayed strobe signal and a clock signal, and outputs a first reference strobe signal which is used to perform phase adjustment such that the phases of these signals match each other. A third delay element delays a first reference strobe signal, and outputs the signal thus delayed as the first strobe signal. A delay amount that corresponds to the amount of skew that occurs between the data signal and the clock signal is set for the third delay element.

Abstract: In a solid-state imaging device, each of a plurality of switches is connected between a pulse output terminal of each delay unit and a pulse input terminal of the next-stage delay unit. Each of a plurality of switches is connected between the pulse output terminal and the pulse input terminal of each delay unit. A plurality of switches is turned on and a plurality of switches is turned off in conjunction with an oscillation operation, and a plurality of switches is turned off and a plurality of switches is turned on in conjunction with a holding operation.

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs.

Abstract: A structure for performing cross-chip communication with mesochronous clocks. The structure includes: a data delay line; a remote clock delay line; a structure that captures at least one value of a state of a delayed remote clock signal on the remote clock delay line; and a control that influences a delay associated with the data delay line and the remote clock delay line.

Abstract: Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are selectively coupled through a variable delay line to synchronize two clock signals.

Abstract: A system and method for characterizing process variations are provided. A circuit comprises a plurality of inverters arranged in a sequential loop, and a plurality of transmission gates, with each transmission gate coupled between a pair of serially arranged inverters. Each transmission gate comprises a first field effect transistor (FET) having a first channel, and a second FET having a second channel. The first channel and the second channel are coupled in parallel and a gate terminal of the first FET and a gate terminal of the second FET are coupled to a first control signal and a second control signal, respectively.

Abstract: A delay chain initialization circuit that converts a singled-sided signal to a dual sided-signal. The dual-sided delay chain including a data rail and a complement rail. Each of the data rail and data complement rail include inverter chains that are interconnected through cross-coupled inverter pairs. The delay chain initialization circuit being adapted to produce, at an output, a data signal and a data complement signal that are substantially simultaneous.

Abstract: A reference signal generator circuit for an analog-to-digital converter, the circuit having a signal-generation stage to generate a first reference signal on a first reference terminal, and a filtering circuit arranged between the generator stage and the analog-to-digital converter to determine a filtering of disturbance present on the first reference signal and supply at output on a second reference terminal a second filtered reference signal, the filtering circuit having a switching circuit to connect the first reference terminal to the second reference terminal directly during startup of the reference signal generator circuit and then through the filtering circuit once the startup step is terminated.

Abstract: A dual rail delay chain having cross-coupled inverters that interconnect the two rails. Delay chain embodiments include cross-coupled inverters that are part of a feed forward signal path between the two rails and are of a larger size than inverters associated with the two rails. The large size feed forward cross-coupled inverters contribute to an enhanced resolution of the delay chain.

Abstract: A method for source synchronous communication. The method includes dynamically adjusting a delay that is applied to a data signal and a remote clock signal until a delayed remote clock signal is synchronized with a local clock signal, and capturing data from a delayed data signal associated with the delay in a local domain.

Abstract: A device for detecting an approach or a touch related to at least one sensor element, in particular in an electrical appliance, the device comprising an input side and an output side, between which a first signal path with a first input and a first output and a second signal path with a second input and a second output are arranged, wherein the first signal path comprises a delay device with a delay, the delay device configured to delay a digital first input signal at the first input into a digital first output signal at the first output, wherein the delay is dependent on a capacitance value resulting from the approach or the touch related to the sensor element, and wherein the second signal path comprises an XOR-element, which is configured to generate an edge in a digital second output signal at the second output, when the digital first output signal outputted by the delay device exhibits an edge.

Abstract: A sampling circuit including a number of state elements or flip-flops. The state elements or flip-flops are each clocked by a signal that causes them to sample their inputs at a predetermined time. In sampling a plurality of digital inputs, a captured delay chain value is stored by the sampling circuit. Each flip-flop holds one bit and together the total number of bits represent this captured delay chain value. Each flip-flop is provided with a data and a data complement signal as an input, the data and data complement signal being substantially simultaneous. In operation each flip-flop includes a direct connection of the data and data complement signals to a pair of transistors that further operate to capture the logical value carried by the input.

Abstract: This disclosure relates to dynamic element matching in delay line circuits to reduce linearity degradation and delay line mismatching.

Abstract: A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the circuit. A phase monitor connects to the circuits. The phase monitor detects phase differences between signals output by the circuits. A controller connected to the delay circuitry, the phase monitor, and the controller adjust the delay circuitry to compensate for the phase differences.

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at a boundary of coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from an input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates a final output clock having a phase between phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs.

Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

Abstract: A delay line including a phase detector having two inputs and one output. The first input of the phase detector is connected to an input of the delay line. The second input of the phase detector is connected to an output of the delay line. The output of the phase detector is connected to a control circuit which controls current flow at a control node to produce a control voltage at the node. A voltage-controlled delay unit is responsible to the control voltage to control a delay applied to a signal at an input of the delay line.

Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

Abstract: An apparatus includes a delay line having multiple delay cells coupled in series. The delay line is configured to receive an input signal and to propagate the input signal through the delay cells. The apparatus also includes multiple sampling circuits configured to sample the input signal at different taps in the delay line and to output sampled values. The delay line has (i) a finer resolution closer to a target tap and (ii) a coarser resolution farther away from the target tap on each side of the target tap. For example, taps nearer the target tap can be closer to each other in order to support the finer resolution, and taps farther from the target tap can be farther apart from each other in order to support the coarser resolution. The apparatus can further include an encoder configured to encode the sampled values in order to generate an encoded value.

Abstract: A deskew system includes a first voltage control delay receiving a data signal and generating N-numbered delayed data signals obtained by delaying a phase of the data signal in units of 90/N, where N is a natural number that is not less than 1. In response to a phase control signal, a second voltage control delay receives a clock and generates N-numbered delayed clocks by delaying a phase of the clock in units of 90/N. A skew compensation control unit generates a plurality of skew control signals to compensate for skew between the data signal and the clock based on the data signal, the N-numbered delayed data signals, the clock, and the N-numbered delayed clocks.

Abstract: A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.

Abstract: A delay circuit is disclosed. A switched-capacitor group includes a plurality of switched-capacitor units, each of which have a switching element and a capacitive element charged/discharged by turning on/off the switching element. The switched-capacitor units are connected such that the input signal is input in common to all of the switched-capacitor units and the capacitive elements are charged as well such that the capacitive elements are discharged to allow the output signal to be output from the switched-capacitor units. A switching control unit performs on/off control of the switching elements to cause the capacitive elements to be charged in sequence based on the input signal, causing the capacitive element charged last time to be discharged to allow the output signal to be output in sequence from the switched-capacitor units, and performs control of all of the switching elements to be turned off upon on/off switching of the switching elements.

Abstract: A voltage-controlled oscillation circuit (15) includes a plurality of independent ring oscillation circuits different in the number of stages; and a selector (22) selectively outputting as a feedback clock signal (FB) an output of one of the ring oscillation circuits, so that any of the outputs of the independent ring oscillation circuits is always outputted as the feedback clock signal, which makes it possible to output the feedback clock signal keeping a proper duty ratio even when the operating speed is high, allowing arbitrary adjustment of the delay time before an input signal (DLLI) is outputted.

Abstract: A delay circuit acquiring an output signal delayed from an input signal, comprising: a switched capacitor group that includes a plurality of switched capacitor units, wherein each of the plurality of switched capacitor units has a charging MOS transistor and a discharging MOS transistor, and a capacitive element which is connected to sources of the charging and the discharging MOS transistors; and a switching control unit that performs on/off control of the charging and the discharging of the MOS transistors, to cause each of the capacitive elements to be charged in sequence based on the input signal, and that, upon causing the each of the capacitive elements to be charged in sequence based on the input signal, causes the capacitive element charged last time to be discharged, to allow the output signal to be output in sequence.

Abstract: A delay circuit in a delay locked loop includes a first delay circuit unit for delaying an input signal using a single delay line in response to first control signals and then outputting a first delay signal and a second delay signal, and a second delay circuit unit for delaying the first delay signal and the second delay signal by delay time, which is correspondent to second control signals and third control signals, using a dual delay line and then outputting a third delay signal and a fourth delay signal.

Abstract: Delay lock loop circuits are described, which may include two or more delay stages that each includes a plurality of selectable delay elements. A reference signal drives an input of the first delay stage, which provides a first output. The first output drives an input of the second delay stage, which provides a second output. The circuits further include a first selector register that is associated with the first delay stage. A value maintained in the first selector register determines a number of the selectable delay elements utilized in the first delay stage. The circuits further include a second selector register associated with the second delay stage. A value maintained in the second selector register determines a number of the selectable delay elements utilized in the second delay stage. Modification of the values maintained in the first and second selector registers are synchronized to the first and second outputs, respectively.

Abstract: A delay line including a phase detector having two inputs and one output. The first input of the phase detector is connected to an input of the delay line. The second input of the phase detector is connected to an output of the delay line. The output of the phase detector is connected to a control circuit which controls current flow at a control node to produce a control voltage at the node. A voltage-controlled delay unit is responsible to the control voltage to control a delay applied to a signal at an input of the delay line.

Abstract: Certain exemplary embodiments can provide a system, which can comprise a circuit adapted to cause an actuation of an output device according to a control output. The control output can be generated comprising a control signal, the control signal extracted from a sequence of clock pulses. The sequence of clock pulses can comprise the control signal.

Abstract: A circuit includes a sensing circuit, a control circuit, and a programmable delay circuit. The sensing circuit generates delay compensation signals that change in response to variations in at least one of a process and a temperature of the circuit. The control circuit generates dynamic control signals in response to the delay compensation signals. The programmable delay circuit is configurable to delay a signal transmitted through an external terminal of the circuit by a delay that is selected by the dynamic control signals.

Abstract: A DPC (300) includes: a frequency source (310) for generating a clock signal; a delay line (320) for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device (330) for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices (500, 510, 520) and a combining network. A method for use in a DPC includes: receiving (400) a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting (410) at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating (420) an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.

Abstract: System and method of calibrating delay mismatch for high-spectral purity applications. For example, a method includes measuring the delay of one delay element at a time in a fixed topology by moving a time reference generated by an auxiliary delay-locked loop. The auxiliary DLL may have a replica structure of the primary DLL being calibrated. The calibration method uses one output clock signal of the primary DLL and measures delay mismatch using a reference phase previously measured using the same topology. The calibration method takes into account all delay mismatches in the topology up to the primary DLL output clock signal, including any delay generated by an associated multiplexer.

Abstract: A DLL circuit includes a first delay adjusting circuit that adjusts an amount of delay of a frequency-divided signal CK1, a second delay adjusting circuit that adjusts an amount of delay of a frequency-divided signal CK2, a synthesizing circuit that synthesizes outputs of these delay adjusting circuits to generate an internal clock signal, and supplies the internal clock signal to a real path, a clock driver that receives the output of the first delay adjusting circuit and supplies the output to a replica path, and a clock driver that receives the output of the second delay adjusting circuit. These clock drivers have substantially the same circuit configuration. Accordingly, even when the power supply voltage fluctuates, influences of the fluctuations on the respective frequency-divided signals are almost equal. Thus, deterioration of the function of the DLL circuit due to fluctuations of the power supply voltage can be prevented.