Abstract: In digital circuits, such as memory circuits, it is sometimes necessary to delay one signal a precise amount of time relative a reference signal. One way to do this is to feed the reference signal to a delay-locked loop which generates a set of signals, each delayed a different amount relative the reference signal. However, as circuits get faster and faster, conventional delay-locked loops require the addition of extra interpolation circuitry to generate smaller delays, and thus consume considerable power and circuit space. Accordingly, the inventor devised a circuit which interlaces and synchronizes two delay-locked loops, each including a number of controllable delay elements linked in a chain. In one embodiment, the first loop produces a sequence of clock signals delayed an even number of delay periods relative a reference clock signal, and the second loop produces a sequence of clock signals delayed an odd number of delay periods relative the reference clock signal.

Abstract: In a semiconductor device capable of obtaining an optimum delay time, a plurality of delay circuits are connected in series to one another through points of connections between two adjacent ones of the delay circuits to produce a plurality of reference delay signals derived from the delay circuits. One of the reference delay signals is decided as the optimum delay time with reference to a practical condition. Thus, the delay time can be varied in the semiconductor device.

Abstract: A delay locked loop in accordance with the present invention includes: a first delay delaying an external clock signal; a first pulse generator receiving an output from the first delay, and generating a first input signal in a short-pulse shape; a second delay delaying an inverted external clock signal; a second pulse generator receiving an output from the second delay, and generating a second input signal in a short-pulse shape; a direction control unit generating first and second control signals in order to control a forward or backward delay of the first input signal or the second input signal in accordance with a level of the external clock signal; and a delay chain consisting of a plurality of unit delays having first and second inverters, and delaying the first input signal or the second input signal in the forward and backward directions through the first and second inverters in accordance with the first and second control signals outputted from the direction control unit.

Abstract: A delayed matching signal generator and frequency multiplier using scaled delay networks for providing precisely delayed matching signals and multiplied frequency signals is provided. The system and method of phase shifting a periodic input digital signal comprises a reference delay line, a replica delay line, and a matched characteristics control system. The reference delay line is composed of multiple reference delay stages through which the input signal is propagated, and the replica delay line is composed of replica delay stages scaled in proportion to the multiple reference delay stages by a scaled delay factor wherein the input signal is propagated. The matched characteristics control system is coupled to the reference delay line and the replica delay line for extracting a phase shifted signal from the replica delay line based upon the scaled delay factor and a scaled propagation of the input signal through the reference delay line.

Abstract: A synchronous delay circuit comprises a first delay circuit array 1 allowing a pulse or a pulse edge to progress during a constant time, a second delay circuit array 2 capable of allowing the pulse or the pulse edge to pass in the first delay circuit array by a length in proportion to a length by which the pulse or the pulse edge has progressed, and a latch delay circuit 5 for storing and reproducing a delay time of a clock driver. Thus, the clock pulse progresses in the latch delay circuit 5 and the delay circuit array 1 during the clock period tcK, so that the delay amount of tcK−(td1+td2) can be obtained with no clock driver dummy. Therefore, when the synchronous delay circuit is applied to the device such as ASIC having the clock delay amount different from one chip to another, it is no longer necessary to design the clock driver dummy for each interconnection design modification, and therefore, a design efficiency and a precision can be elevated.

Abstract: An analog delay line uses an analog-to-digital (A/D) converter which converts an analog signal into a plurality of digital signals. Digital delay lines, each including a series of digital delay elements, delay the respective digital signals. A digital-to-analog (D/A) converter converts the digital signals back into a delayed analog signal.

Abstract: A delay locked loop comprising a chain (CHN) of at least two delay elements (DL1-DLN), of which a first delay element (DL1) has an input for receiving a reference signal (phi0), and of which a last delay element (DLN) has an output for delivering an output signal (phiN); a phase comparator (PHCMP) having a first input (PH1) for receiving the reference signal (phi0), a second input (PH2) for receiving the output signal (phiN), and an output for delivering a binary control signal (Bcntrl); and a converter (CNV) for converting the binary control signal (Bcntrl) into an analog control signal (Acntrl) for controlling a delay time of at least one (DL1-DLN) of said delay elements (DL1-DLN). The phase comparator (PHCMP) comprises at least one additional input (Aip) for receiving an output signal (phi1-phiN−1) of at least one of the delay elements (DL1-DLN−1) preceding the last delay element (DLN).

Abstract: Circuits for sequentially addressing memory locations in time with pulses received from a clock are disclosed. The circuits may provide a positive voltage output signal at successive output nodes associated with corresponding stages in the circuit responsive to the application of a clock signal to the circuit stages. The circuit may comprise at least first and second stages wherein said first stage comprises means for providing a positive voltage signal at a first output node in the first stage in response to application of a first positive clock pulse to the first stage, and wherein said second stage comprises means for providing a positive voltage signal at a second output node in the second stage in response to application of a second positive clock pulse to the second stage. Addressing of memory locations that contain pixel information for a video display is one particular application in which sequential addressing may be required.

Abstract: A cascaded delay asynchronous clock (CDAC) for operating control logic (16) to process an event signal. The clock includes a flip-flop (15) for receiving the event signal and generating a clock enable signal and a logic gate (14) connected to the flip-flop (15) for receiving the clock enable signal and generating a clock signal. The clock signal is then communicated to the control logic (16) for use in the control process. The CDAC further includes a plurality of cascaded delays (10) connected in series, such that the first cascaded delay (10) is connected to receive as an input the clock signal, and the last delay (10) is further connected to the logic gate (14). The output of each of the plurality of cascaded delays (10) is fed back to the control logic (16) to generate timing signals. In another aspect of the invention, a variable duty cycle asynchronous clock (VDAC) for operating control logic (40) to process an event signal is disclosed.

Abstract: A clock generation circuit comprises a clock wiring having opposed first and second ends, through which a clock is transmitted from the first end to the second end, and a plurality of clock phase adjustment circuits for generating internal clocks in accordance with the clock supplied from the clock wiring. Each of the clock phase adjustment circuits comprises a first-end side terminal and a second-end side terminal which are connected to a first-end side point and a second-end side point of the circuit, respectively, the points being positioned on both sides of a reference point of the clock wiring; a delay line for delaying a clock supplied from one of the terminals and outputting an internal clock; and a delay control circuit for performing feedback control on a delay of the clock in the delay means in accordance with the phase of the clock supplied from the other terminal so that the phase of the internal clock matches the phase of the clock at the reference point of the cock wiring.

Abstract: A clock/data recovery device employs a phase-locked loop that supplies a single clock signal and a control voltage signal to at least one clock/data recovery circuit. The clock/data recovery circuit has a voltage-controlled delay line or direct phase controlled voltage-controlled oscillator that generates a multiple-phase clock signal, which is used to recover a clock signal and data from a received data signal. The voltage-controlled delay line or direct phase controlled vottage-controlled oscillator has a cascade or ring of voltage controlled logic gates, with propagation delays controlled by the control voltage signal from the phase-locked loop, and additional logic gates that supply the clock signal from the phase-locked loop to a selectable one of the voltage-controlled logic gates.

Abstract: A ring oscillator is formed by connecting three or more odd gate circuits in a ring. Each gate circuit includes a precharge dynamic gate. An output signal from the precharge dynamic gate of one gate circuit is used to precharge the precharge dynamic gates of all the remaining gate circuits. In measuring the gate delay time of the ring oscillator formed by connecting, in a ring, three or more odd gate circuits each including a precharge dynamic gate, the oscillation frequency of the ring oscillator is measured, and the reciprocal of the oscillation frequency is divided by the number of gate circuits constituting the ring oscillator.

Abstract: An input block is provided that includes a user-controlled, variable-delay input circuit. The input circuit is adapted to receive an input signal and to output a delayed version of the input signal on an output node. A number of control signals dictate the amount of delay imposed on the input signal. The control signals, and therefore the amount of delay, are established using a control-signal generator. The generator can be used to actively alter the delay. In one embodiment, the control signal generator is implemented as a feedback circuit that automatically matches the delay period of the delay circuit with the delay period of a distributed clock signal.

Abstract: A structure for handling the refresh of a DRAM array so that the refresh has no effect on the external access. A system clock signal initiates activation and deactivation of elements of the DRAM array using a sequencer which subdivides each system clock signal period into three parts, thus providing four control signals fixed phase relationship per clock period.

Abstract: The present invention is embodied in a method and apparatus for improving a delay line circuit of a Digital Delay Lock Loop (DDLL) circuit. Each delay stage of the delay line consists of three gates, two NANDs and one inverter. The reduction in the total number of gates decreases the unit delay time for each stage, improving the resolution of each stage of the delay line. In addition, the reduction in the total number of gates in each stage significantly reduces the amount of space necessary for the circuitry of the delay line, resulting in an overall decrease in the size of the DDLL circuit.

Abstract: Described is a variable digital delay cell with a first input for receiving a first input signal to be delayed, a first output for providing a first output signal which is delayed with respect to the first input signal, and a control signal for controlling the delay time of the delay cell. The delay cell further includes a second input for receiving a second input signal which is delayed with respect to the first input signal, and a second output for providing a second output signal which is delayed with respect to the first input signal by a fixed delay time. The delay cell according to the invention can be driven as a single device, but also allows a cascading of an `unlimited` number of delay cells without increasing the base delay in comparison to a single delay cell.

Abstract: A delay circuit device having first and second delay circuits arrays so constructed that an output can be taken out from an arbitrary position of a signal transmission path, discriminating circuits receiving an output from two positions which divide the first delay circuit array into three portions, and three control circuits. The first and second delay circuit arrays are so arranged that the direction of signal transmission paths are opposite to each other. An output of the first delay circuit array is connected to an input of the second delay circuit array through the control circuits in the order from the position near to an input of the first delay circuit array and in the order from the position near to an output of the second delay circuit array. A first signal is supplied to the first delay circuit array, and whether or not the first signal is propagated to the output of the two positions is respectively latched in the discriminating circuits.

Abstract: A segmented dual delay-locked-loop (DLL) has a coarse DLL and a fine DLL. Each DLL has a series of buffers, a phase detector, charge pump, and bias-voltage generator. The bias voltage controls the delay through the buffers. The bias voltage of the coarse DLL is adjusted by the phase comparator to lock the total delay through the buffers to be equal the input-clock period. The coarse DLL divides an input clock into M equal intervals of the input-clock period and generates M intermediate clocks having M different phases. An intermediate mux selects one of the M intermediate clocks in response to a phase-selecting address. The selected intermediate clock K and a next-following intermediate clock K+1 are both selected and applied to the fine DLL. The K clock is input to a series of N buffers in the fine DLL while the K+1 clock is directly input to a phase detector. The phase detector compares the K+1 clock to the K clock after the delay through the buffers.

Abstract: An internal clock signal generator of a synchronous memory device is provided. The internal clock signal generator includes first and second inverting portions, a delay portion, first and second switching portions, and first and second logic portions also called input and output logic circuits, respectively. The first inverting portion inverts an external clock signal. The second inverting portion inverts an output signal of the first inverting portion. The delay portion delays an output signal of the second inverting portion. The first switching portion gates an output signal of the delay portion in response to a first control signal. The second switching portion gates the output signal of the second inverting portion in response to a second control signal. The first or input logic portion performs a logic operation with respect to signals input from an external source and outputting the first and second control signals.

Abstract: A programmable phase adjuster spans a clock signal's period with N linearly distributed phase steps. The resulting phase adjust resolution is finer than that of an inverter delay for a given process. Enhancement of the phase resolution of a phase picker CRM architecture enables use of the architecture for recovering clock signals from high data rate data streams in a way that minimizes power and area and allows optimization for multi-channel applications.

Abstract: A cycle measuring circuit 3 measures a cycle of an external clock signal, which is approximately m times a unit time. A number converting circuit 5 and a time converting circuit 7 cooperate, generating a pulse signal delayed by m/2.sup.K times the unit time, or by 1/2.sup.K times the cycle of the external clock signal. A logic circuit 8 generates an internal clock signal which rises in synchronism with the external clock signal and falls in synchronism with the pulse signal thus delayed. Hence, the internal clock signal has the same cycle as the external clock signal and has a desired duty ratio of (1/2.sup.K).times.100%.

Abstract: An interface cell transmits a signal with a delay time corresponding to a delay time control signal. A delay time control circuit consists of a delay chain and a PLL circuit. The delay chain consists of a plurality of series-connected interface cells to a head cell of which a clock signal is supplied, and a delay signal of a clock signal is then fetched from the interface cell at an arbitrary stage. The PLL circuit generates a delay time control signal so as to make phase difference between the clock signal and the delay signal equal. This is true of a delay cell. A phase difference compensation circuit is provided on an output end of a clock line of the integrated circuit to delay an input clock signal based on an input control signal.

Abstract: A synchronous delay circuit contains a first delay circuit for propagating a pulse for a fixed period of time, a second delay circuit for passing the pulse over a length proportional to the length of the first delay circuit along the path that the pulse propagated, and a circuit for outputting a monitor signal when a clock period is propagating through a clock driver. The first delay circuit measures a clock period tCK, and the second delay circuit reconstructs the measured clock period. External clock signals travel through a path from an input buffer through a first switch of a clock driver. The time corresponding to a delay time of the input buffer (td1) and a delay time of the clock divider (td2) is subtracted from the clock period tCK producing a delay circuit with a delay of tCK-(td1+td2). When the clock pulse passes through the delay circuit whose delay is tCK-(td1+td2), the internal clock delay becomes equal to the clock cycle tCK. Thus, the internal clock is free of clock skew.

Abstract: A delay cell for use in binary delay line which includes a delay circuit having N outputs where N.gtoreq.2, each delay circuit coupled to an input through N-1 serially connected unit cells. For each output there are P unit cells having a unit delay of t.sub.P0 and N-1-P unit cells having a unit delay of t.sub.p1. The N outputs are ordered such that each output other than the first is delayed with respect to an immediately preceding output by t.sub.p1 -t.sub.p0, and P goes in succession from N-1 to 0 in unit steps. Each value of P corresponds to only one of the N outputs.

Abstract: A clock circuit including an input terminal (300) for receiving a clock signal and a first pulse generator (302) coupled to the input terminal. The first pulse generator is operable to generate a voltage pulse in response to a logic-low voltage to logic-high voltage transition of the clock signal. The circuit also includes a second pulse generator (304) coupled to the input terminal, the second pulse generator being operable to generate a voltage pulse in response to a logic-high voltage to logic-low voltage transition of the clock signal. A first clock deskewing circuit (306) is coupled between the first pulse generator and a first clock signal output terminal and a second clock deskewing circuit (308) is coupled between the second pulse generator and a second clock signal output terminal.

Abstract: A clock compensation circuit includes a clock tree; a reference clock; a phase detector for detecting relative phase information of the tree clock and the reference clock; a controller, coupled to said phase detector, for determining and controlling the amount of delay necessary to shift the output of the clock tree in phase with the reference clock; and a programmable delay logic coupled to said controller. The programmable delay logic comprises a string of delay elements that selectively participate in a delay string for shifting the tree clock in phase with the reference clock.

Abstract: A clock signal generator having a pre-phase converter for generating in response to an input clock signal a plurality of pre-delay clock signals with different phases; and main phase converters each of which receives one of the pre-delay clock signals, and generates a plurality of main delay clock signals with their phases different from each other, thereby generating multiple main delay clock signals with their phases different from each other.

Abstract: A clock for digital devices. Ordinarily, when multiple digital devices are clocked by a common clock, the clock signals frequently arrive at the digital devices at different times, due to propagation delays. The devices are thus not clocked synchronously. Under the invention, the multiple devices are connected to a common transmission line. A standing wave is generated on the transmission line, and the periodic collapse of the standing wave is used to clock the devices. Synchronous clocking to within about 1.0 nano-seconds has been attained, in a transmission line about ten feet long, wherein a clock signal ordinarily takes about 15 nanoseconds to travel from one end to the other.

Abstract: A direct digital frequency synthesizer featuring an accumulator having a modulo overflow signal addressing a multiplexer. The multiplexer receives a series of delay signals generated from digital circuits. The delay signals establish the phase of a reference oscillator. The number of units of delay are sufficient to resolve expected jitter. The accumulator is a digital counter which increments by only a single digit for each count, such as a Gray code counter. In one embodiment, the delay signals are generated by a charge pump feeding individual logic circuits driving integrated capacitors in a loop. Feedback to the charge pump establishes that the total delay will subdivide a single clock cycle of the reference clock. In a second embodiment, a single shifter or several shifters, with output in phase reversal relation, subdivide a single clock cycle. A clock multiplier and divider are used to assure the synchronism of each clock cycle with the total number of units of delay.

Abstract: A signal detection circuit employs a delay line with edge detection logic for capturing and buffering timing information about an input signal. A plurality of comparators for comparing the input signal to different reference potentials capture amplitude information in the input signal launching bits into respective delay lines. Preferably, each delay line includes a counter for counting detected bit edges.

Abstract: A serial data signal is synchronized to a clock signal in a synchronization circuit (10). Synchronization is accomplished by generating a plurality of delayed versions of the serial data signal using serially connected delay elements (21-27). The delayed versions of the serial data signal are sampled using a set of flip-flops (11-18). The sampled delayed data signals appearing at the outputs of each flip-flop of the set of flip-flops (11-18) are used to determine which delayed data signal is most closely aligned to the clock signal. The output of the multiplexer (40) is an aligned serial data signal. In addition, a drift correction circuit (50) continuously monitors and corrects the alignment between the clock signal and the aligned serial data signal.

Abstract: There is provided a time counting circuit which measures a pulse spacing of a pulse signal with a high accuracy and exhibits high resistance to variations in power-source voltage.A delay circuit ring consists of a plurality of delay circuits connected in a ring configuration and signal transition is caused to circulate around the delay circuit ring by oscillation. A switch-signal generating circuit outputs first and second switch signals based on the time at which a pulse signal to be measured rises. A row of sampling circuits consists of a plurality of sampling circuits connected to the output terminals of the respective delay circuits and samples the output signals from the delay circuits in response to a direction indicated by the first switch signal.

Abstract: A delay line circuit is provided that precisely delays the incoming referenced clock signal by utilizing two delay cells and a sample-and-hold circuit. The circuit eliminates the need for sensing circuitry at the output to determine if the need to monitor the delay line circuit is operating in an undesirable operation. By eliminating the sensing circuitry the reliability of delay line circuit is significantly increased.

Abstract: The present invention provides a delay clock generator where a plurality of stable delay clocks can be generated and digitizing is easy. The delay clock generator comprises first to nth (n: integer not less than 2) delay circuits (11 to 1n) connected in cascade connection for delaying the basic clock (KO) in sequence, a phase comparator (21) for comparing phase of a delay clock from the nth delay circuit (1n) with that of the basic clock, and a delay control circuit (31) for generating a delay control value to make the phase of the delay clock from the nth delay circuit synchronize with that of the basic clock based on a phase comparison result, and for controlling delay amounts of the first to nth delay circuits respectively by the delay control value.

Abstract: The detrimental nonlinear charging currents from an analog input signal through an anti-aliasing filter into a sampling circuit can be minimized by using primary and secondary inputs to the sampling circuit. The secondary input is turned on before the primary input and the charge required to charge the parasitic capacitance inside the sampling circuit and to replenish the channeling charge lost in the previous cycle is supplied primarily through the secondary input. Immediately after the secondary input is turned off the primary input is connected to the sampling node, and only the charge required to fine tune the signal into the sampling capacitor is drawn through the primary input. Therefore, most of the non-linear charge injection is passed through the secondary input, and the signal passed through the primary input is used to fine tune the voltage levels inside the sampling circuit during the actual sampling operation.

Abstract: Systems and methods for accurately skewing periodic signals using a matching pair of voltage controlled delay lines, a frequency comparator, and a common control signal to the delay lines as generated by the frequency comparator. A feedback oscillation is established in a loop including one of the voltage controlled delay lines. The frequency comparator controls the frequency of the loop oscillation in direct proportion to a comparison between the oscillation frequency and a subharmonic of a base clock signal. The base clock signal is sent through the second voltage controlled delay line, which by matching of delay line characteristics and a common control signal introduces a clock period of skew or delay over the length of the second voltage controlled delay line. Taps to nodes in the succession of device stages making up the second voltage controlled delay line provides the clock signals with directly proportioned skews, the skews being defined by precise physical divisions of the delay line.

Abstract: A sampling circuit is not susceptible to an influence of structural components and environmental changes. A phase difference detecting circuit (5) detects a deviation of a sampling clock (.phi.2) from optimal sampling timing and outputs a phase difference signal. On the other hand, a phase reference signal (ORG) which is used as a reference to determine a phase advance and a phase lag is generated by a phase reference detecting circuit (4). In accordance with these signals, a sampling clock shifting circuit (2) shifts the sampling clock (.phi.2) so that the sampling clock (.phi.2) is activated at optimal sampling timing. Sampling is performed in accordance with such a sampling clock (.phi.2), whereby a basic signal is generated from which the phase reference signal (ORG) and the phase difference signal (i.e., an equivalent signal (EQU) and a non-equivalent signal (UPDN)) are generated. By means of feedback control, the sampling clock is automatically activated at optimal sampling timing.

Abstract: A semiconductor integrated circuit detecting a change in the internal propagation delay and self-compensating such a change. A combination of semiconductor integrated circuits can self-compensate a change in the total propagation delay of the circuit. There is provided a ring oscillator composed of dummy device elements separate from an actually-used logic circuit portion. The oscillating pulses of the ring oscillator are counted relative to a reference pulse signal. The semiconductor integrated circuit has a delay time compensation control circuit block which generates control data used to compensate the change in the propagation delay based on the difference between the first-counted value and a subsequently counted value. In a combination of semiconductor integrated circuits, the delay time compensation control circuit block may be provided for each channel. Alternatively, the delay time compensation control circuit block may be provided for common use by many channels.

Abstract: In a computer system, digital signals are transmitted from an output register, propagated along a first signaling path, and received by an input register. The signaling path including an address buffer, a cache memory, a main memory, and an interconnect network. The effects of the intrinsic delays experienced by the digital signals are measured as a delay value relative to a reference clock signal propagated through a second signaling path duplicating the delays of the first signaling path. The delay value is used to selectively delay the digital signal to maintain a fixed relationship between the transmitted and received digital signals. Delay measuring and regulation is provided by driving the reference and digital signals through comparable tapped delay lines, the output taps of a measuring delay line controlling the output taps of a delaying line. Storage latches are provide to hold the measured delay value stable between successive samples.

Abstract: A high speed sampler comprises a meandered sample transmission line for transmitting an input signal, a straight strobe transmission line for transmitting a strobe signal, and a plurality of sampling gates along the transmission lines. The sampling gates comprise a four terminal diode bridge having a first strobe resistor connected from a first terminal of the bridge to the positive strobe line, a second strobe resistor coupled from the third terminal of the bridge to the negative strobe line, a tap connected to the second terminal of the bridge and to the sample transmission line, and a sample holding capacitor connected to the fourth terminal of the bridge. The resistance of the first and second strobe resistors is much higher than the signal transmission line impedance in the preferred system. This results in a sampling gate which applies a very small load on the sample transmission line and on the strobe generator.

Abstract: The delay device 10 includes an ECL gate 11, the current source 16 and two resistive load elements 14, 15 of which are associated with an adjusting circuit 23 producing an adjusting voltage Vd, to cause the polarization current of the current source to vary hyperbolically, and a voltage Vh for keeping constant the voltage at the collectors of the transistors 12 and 13 of the gate 11. The delay device 10 causes the delays between the input signals IN, IN* and output signals OUT, OUT* to vary linearly. The invention is applicable in particular to systems for the transmission of digital data at a very high rate, of more than 1 gigabit per second, for example.

Abstract: A delay locked loop (44) includes an arbiter circuit (86), a VCD circuit (85), and a collapse detector (88). The arbiter circuit (86) receives an input signal and provides a retard signal to adjust the amount of propagation delay of VCD circuit (85), in order to synchronize the phases of the input signal to an output signal of the VCD circuit (85). The collapse detector (88) detects if the output signal of the VCD circuit (85) has failed to change logic states within a predetermined length of time. The delay locked loop (44) can lock the phases of two signals having different frequencies.

Abstract: Disclosed is a digital phase-locked loop circuit which provides a control signal (332, 334) for a delay circuit (304, 306, 308, 310) within the feedback path of the phase-locked loop. The circuit has a first series of delay circuits (304, 306, 308, 310), which have an incremental control signal input (332, 334), to delay an input clock signal (302) to provide the D input (311) to a D flip flop (312). The input clock signal (302) is also connected to a second series of delay circuits (314, 316, 318, 320, 322). The output of this second series (314, 316, 318, 320, 322) is connected to the clock input (323) of the D flip flop (312). The voltage controlled delay signal input for the second series of delay circuits (314, 316, 318, 320, 322) is supplied by a reference control signal (124, 126). The output of the D flip flop (312) is passed through a resistor-capacitor filtering circuit (324, 325) and fed back to the first series of delay circuits (304, 306, 308, 310) as the incremental control signal.

Abstract: All digital, high frequency data separation receiver apparatus and method for ascertaining the correct sequence of received digital data without a phase locked loop or an analogue voltage control oscillator (VCO) method, which employs a series of time delay circuits to establish time rulers to unambiguously determine the sequence of received bits.