Abstract: Temperature-independent delay elements and oscillators are disclosed. In one design, an apparatus includes at least one delay element, a bias circuit, and a current source. The delay element(s) receive a charging current from the current source and provide a delay that is dependent on the charging current. Each delay element may be a current-starved delay element. The delay element(s) may be coupled in series to implement a delay line or in a loop to implement an oscillator. The bias circuit controls generation of the charging current based on a function of at least one parameter (e.g., a switching threshold voltage) of the at least one delay element in order to reduce variations in delay with temperature. The current source provides the charging current for the delay element(s) and is controlled by the bias circuit.

Abstract: Provided is a receiving apparatus that receives a data signal and a clock signal indicating a reference timing to acquire the data signal. The receiving apparatus includes a multi-strobe generating section that generates, based on a pulse of the recovered clock, a plurality of strobes of which phases are different from each other, a first detecting section that detects a position of an edge of the clock signal relative to the strobes based on values of the clock signal that are acquired at respective timings of the strobe, a first adjusting section that adjusts a phase of the recovered clock according to the edge position of the clock signal, and a second adjusting section that adjusts the timing to acquire the data signal according to a phase adjustment amount of the recovered clock made by the first adjusting section.

Abstract: A pulse generator comprising: an input for receiving a trigger; an output node for outputting a signal; a delay line comprising one or more delay units and a plurality of taps; one or more pull-up devices each connected to the output node for increasing the output voltage on the output node; and/or one or more pull-down devices each connected to the output node for decreasing the output voltage on the output node; wherein the taps of the delay line are operably connected to the pull-up and/or pull-down devices such that a trigger passing along the delay line activates one or more of the pull-up and/or one or more of the pull-down devices more than once. Re-use of the pull-up and/or pull-down devices enables longer and more complex pulse shapes, such as high-order Gaussian pulse shapes to be produced while keeping the number of components low, thus reducing chip area, power requirements and parasitic capacitance.

Abstract: The subject matter of this application is embodied in an apparatus that includes a configurable delay circuit comprising a plurality of delay elements, and a lookup table having information for configuring the delay circuit based on one or more conditions. The apparatus also includes a controller to configure the delay circuit according to the information in the lookup table, and a sampling circuit to sample outputs of each of a subset of the delay elements and generate a multi-bit delay signal providing information about an amount of delay caused by the delay elements to an input signal propagating through the configurable delay circuit. Each bit in the multi-bit delay signal indicates whether the input signal has propagated through a corresponding delay element.

Abstract: Process, voltage and temperature corners of an on-chip device under calibration are obtained by comparing the outputs of different on-chip components such as active on-chip components and passive-on chip components in response to an input. A first on-chip delay line including a number of active devices, which generate an array of outputs D[ ]) at different stages of the delay. A second on-chip delay line generates a single output (CLK). A DFF array samples the array of outputs (D[ ]) with the single output clock CLK. The different delay variations in different process and temperature corners cause different outputs from the DFF array. The different outputs from the DFF array provide information about the process and temperature corner that can be for rapid calibration of the on-chip device under calibration within one cycle of the CLK.

Abstract: An open loop type delay locked loop includes a delay amount pulse generation unit configured to generate a delay amount pulse having a pulse width corresponding to a delay amount for delay locking a clock signal, a delay amount coding unit configured to output a code value by coding the delay amount in response to the delay amount pulse, a clock control unit configured to adjust a toggling period of the clock signal in response to a control signal, and a delay line configured to delay an adjusted clock signal outputted from the clock control unit in response to the code value.

Abstract: In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs.

Abstract: A skew signal generator is provided which comprises a fuse signal generating unit for generating a plurality of fuse signals, and an encoder for generating skew signals including skew information of a wafer by encoding the fuse signals.

Abstract: A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal.

Abstract: A programmable delay generator and a cascaded interpolator are provided. The programmable delay generator includes a first delay line and a second delay line, each having a respective plurality of stages of the same number. Each stage of the first line includes a respective delay buffer and has one signal input and one signal output. Each stage of the second line includes a respective selecting element and has two signal inputs, one select input for selecting one of the two signal inputs, and one signal output. The first line and the second line are configured in parallel, are interconnected, and have a same signal propagation direction. Each delay step provided by each stage of the second line is equal to a difference between a delay through one stage of the first line and a delay through one stage of the second line.

Abstract: The present disclosure relates to on-chip self calibrating delay monitoring circuitry.

Abstract: In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.

Abstract: A method and system for power supply management in an integrated chip selectively manages the power supplied to the various circuits within the integrated circuit. The integrated circuit includes a combinational logic block, a memory block, a power supply block, and a control block. The power supply block includes multiple power regulators for generating power supply potentials of various magnitudes. The control block receives a power down signal, a clock disable signal, and a temperature threshold signal, and generates control signals for controlling the magnitude of the potential of the power supplied to the combinational logic block and the memory block by the power supply block.

Abstract: A tunable delay cell (TDC) is disclosed, the TDC is applied to power gating circuit design, and the TDC is connected with control unit. The TDC comprises multiplexer, delay unit, clock signal input line, control signal line, power source terminal and combinational circuit. The signal provided by the control signal line can control the clock signal provided by the clock signal input line whether to be delayed a predetermined time by the delay unit or not. The control unit controls the combinational circuit to be turned off to make the TDC stop working.

Abstract: A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer are reduced by coupling a reduced voltage pre-charge circuit to the multiplexer.

Abstract: A skew signal generator is provided which comprises a fuse signal generating unit for generating a plurality of fuse signals, and an encoder for generating skew signals including skew information of a wafer by encoding the fuse signals.

Abstract: A frequency synthesizer is disclosed. The frequency synthesizer includes a period control word generator, a delta-sigma modulator, and a delay line unit. The period control word generator generates a period control word. The delta-sigma modulator receives the period control word and generates a phase selection signal. The delay line unit generates an output clock based on the phase selection signal. The delta-sigma modulator performs a carry-in operation based on a base number and the base number is adjustable and determined by a calibration process of the delay line unit.

Abstract: A digital delay line includes a plurality of delay cells therein. The delay line is configured to delay a periodic signal received at a first input thereof by passing the periodic signal through a selected number of the plurality of delay cells, in response to a discontinuous thermometer code that encodes the selected number. A code converter is provided, which includes a group bit decoder, a shared bit decoder and a code output cell array, which are collectively configured to generate the discontinuous thermometer code in response to a binary control code.

Abstract: A programmable delay circuit capable of providing a delay with integer and fractional time resolution is described. In one exemplary design, an apparatus includes first and second delay circuits. The first delay circuit provides a first delay of an integer number of time units. The second delay circuit couples to the first delay circuit and provides a second delay of a fraction of one time unit. The first delay circuit may include multiple unit delay cells coupled in series. Each unit delay cell may provide a delay of one time unit when enabled. The second delay circuit may have first and second paths. The first path may provide a shorter delay when selected, and the second path may provide a longer delay when selected. The second path may be coupled to at least one dummy logic gate that provides extra loading to obtain the longer delay for the second path.

Abstract: A delay line including a phase detector having two inputs and one output. The first input of the phase detector is connected to an input of the delay line. The second input of the phase detector is connected to an output of the delay line. The output of the phase detector is connected to a control circuit which controls current flow at a control node to produce a control voltage at the node. A voltage-controlled delay unit is responsible to the control voltage to control a delay applied to a signal at an input of the delay line.

Abstract: An oscillator circuit includes differential variable delay circuits coupled together to form a ring oscillator. Each of the differential variable delay circuits has first and second inputs and first, second, third, and fourth transistors. A constant supply voltage is provided to sources of the first and the second transistors in each of the differential variable delay circuits. A variable supply voltage is provided to sources of the third and the fourth transistors in each of the differential variable delay circuits. Gates of the first and the third transistors are coupled to the first input. Gates of the second and the fourth transistors are coupled to the second input. The oscillator circuit generates a periodic output signal having a frequency that varies based on changes in the variable supply voltage.

Abstract: A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse.

Abstract: A switchable capacitive element having an adjustable capacitance and an improved quality factor is specified. To this end, the characteristic variables of the switchable capacitive element are optimized in accordance with the equations cited in the description.

Abstract: A programmable delay element with a variable delay generator employs feed forward and feedback control signals to corresponding feed forward and feedback control elements integrated within the variable delay generator. The variable delay generator is responsive to a control signal. The variable delay generator uses transfer switches to couple reactive circuit elements to a signal node in accordance with the control signal. The feed forward element couples a fixed voltage to corresponding nodes of the feed back element. The feedback element completes a bypass circuit to apply the fixed voltage to the signal node once the programmable delay element has delayed a source signal. The feed forward element is responsive to a buffered version of the source signal. The feedback element is responsive to a buffered version of the output of the delay element. A corresponding method for reducing frequency induced delay variation in a programmable delay element is disclosed.

Abstract: A variable delay circuit 1 includes: a multistage delay circuit 20 constructed by connecting delay elements D1 to Dn in series; a selecting unit 21 which selects one delayed signal obtained by introducing different amounts of delay by passing a reference clock through one or more of the delay elements D1 to Dn; a decision unit 23 which, at decision timing synchronized to the reference clock, makes a decision on the logic state of each delayed signal sequentially selected from among the plurality of delayed signals; and a changing point detection unit 24 which detects at least two delay elements Dm and Dk where a change has occurred in the logic state of the reference clock at the decision timing, and wherein the difference (k?m) between the numbers of delay elements through which the clock signal has passed until reaching one of the two detected delay elements Dm and Dk is used as the number of delay elements that provides a desired delay time.

Abstract: A delay circuit is disclosed. A switched-capacitor group includes a plurality of switched-capacitor units, each of which have a switching element and a capacitive element charged/discharged by turning on/off the switching element. The switched-capacitor units are connected such that the input signal is input in common to all of the switched-capacitor units and the capacitive elements are charged as well such that the capacitive elements are discharged to allow the output signal to be output from the switched-capacitor units. A switching control unit performs on/off control of the switching elements to cause the capacitive elements to be charged in sequence based on the input signal, causing the capacitive element charged last time to be discharged to allow the output signal to be output in sequence from the switched-capacitor units, and performs control of all of the switching elements to be turned off upon on/off switching of the switching elements.

Abstract: A method of delaying successive first and second input signals by first and second different selectable time periods using a programmable delay line comprising a sequence of delay elements, each introducing a delay, the method comprising the steps of: providing a control signal to each delay element, the control signal selectively being in a first logic state or a second logic state wherein in a first logic state the delay element selects an input from an adjacent delay element thereby to select the delay elements as part of a set of delay elements introducing said selectable time period and in a second logic state the delay element is not selected in the set; setting the control signals for a first number of adjacent delay elements to the first logic state to introduce the first selectable time period wherein the control signals for the delay elements in the sequence not in the first number are set to the second logic state; and setting the control signals of a second number of adjacent delay elements to the

Abstract: A device for determining an interference with a regulated voltage provided by a control loop with a unit for monitoring a control variable of the control loop and a unit for generating a notification signal if the control variable or a change in the time of the control variable is beyond a tolerance range around a normal value.

Abstract: A tunable delay line is calibrated to maintain the delay of the delay line at a desired value or within a desired range of values. In some aspects a signal is passed through a delay line multiple times so that the cumulative delay of the signal through the delay line (e.g., as indicated by a count) may be calculated over a period of time. The count is compared with an expected count and, based on this comparison, the delay of the delay line is adjusted as necessary. In some aspects the signal may comprise a digital signal. In some aspects a delay through a delay line may be calculated based on analysis of amplitude changes in a signal caused by a phase shift imparted on the signal by the delay line. In some aspects a delay line is incorporated into a transmitted reference system to generate and/or process transmitted reference signals.

Abstract: It is an object of the invention to provide a variable delay apparatus in which, even immediately after the delay amount of the variable delay apparatus is changed, a signal of a timing that is different from a set delay amount is not output. The variable delay apparatus of the invention includes: a variable delay block 108 having N (N is a natural number) delay elements 101a to 101n, and N selectors 102a to 102n; a variable delay block 109 having N delay elements 103a to 103n, and N selectors 104a to 104n; and a selector 107. After selection signals 105a to 105n and 106a to 106n are changed, and after an output timing of a delay amount set by the variable delay blocks 108, 109 is attained, the signal to be output is switched by the selector 107, thereby avoiding a situation where, immediately after the delay amount is changed, a signal of a timing that is different from the set delay amount is output as an output signal.

Abstract: A DLL circuit includes a delay unit configured to generate a DLL clock signal by delaying a reference clock signal while adjusting a delay amount in response of a level of a control voltage. An initial operation control unit is configured to control an initial level of the control voltage and generate a detection enable signal. A delay control unit is configured to generate the control voltage by comparing a phase of the reference clock signal and a phase of the DLL clock signal in response to the detection enable signal.

Abstract: A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse.

Abstract: A time-delay buffer having a CMOS inverter and a capacitor is disclosed. The CMOS inverter of the time-delay buffer has a silicide layer partially disposed on the transistor gate of the CMOS and a non-silicide region lain in between the silicide layers. Therefore, the time-delay buffer of the present invention has a resistance therein, and results in a period of time delayed in the circuit.

Abstract: A delay circuit comprising a delay measurement unit, a delay mapping unit and a map delay module. The delay measurement unit generates a mapping table according to a reference signal and a reference clock signal. The delay mapping unit generates a mapped delay selection signal according to an input selection signal and at least a mapping value from the mapping table. The map delay module delays an input data signal to generate an output data signal according to the mapped delay selection signal.

Abstract: An absolute time delay generating device includes a PVT (process-voltage-temperature) detection device and a delay-timing generator. The PVT detection device includes at least a delay module and a signal phase/frequency control module. The delay module includes a control unit and a reference unit. The control unit differs from the reference unit in sensitivity of delay property to PVT. The delay module compares phase or frequency differences generated when origin signals pass through the control unit and reference unit respectively, and produce delay parameters of the delay module. The signal phase/frequency control module receives and compares the delay parameters to determine an ambient PVT condition for the absolute time delay generating device, so as to control and correct the delay-timing generator and thereby generate accurate absolute time delay. Under various PVT influences, the absolute time delay generating device is capable of generating accurate, absolute time signals.

Abstract: Embodiments of programmable delay line circuits are disclosed herein. The delay line circuit may comprise a first multiplexer having a first input coupled with an input line; a second multiplexer having a first input, and a second input coupled with an output of the first multiplexer, and an output coupled with a second input of the first multiplexer; a third multiplexer having a first input coupled with the output of the second multiplexer, a second input coupled with the input line, and an output coupled with an output line; a first control gate coupled with the third multiplexer to control the third multiplexer; and a second control gate coupled with the second multiplexer to control the second multiplexer; wherein the first and second control gates selectively control the second and third multiplexer, responsive to a delay value encoded in Gray Code.

Abstract: A delay circuit acquiring an output signal delayed from an input signal, comprising: a switched capacitor group that includes a plurality of switched capacitor units, wherein each of the plurality of switched capacitor units has a charging MOS transistor and a discharging MOS transistor, and a capacitive element which is connected to sources of the charging and the discharging MOS transistors; and a switching control unit that performs on/off control of the charging and the discharging of the MOS transistors, to cause each of the capacitive elements to be charged in sequence based on the input signal, and that, upon causing the each of the capacitive elements to be charged in sequence based on the input signal, causes the capacitive element charged last time to be discharged, to allow the output signal to be output in sequence.

Abstract: Herein disclosed is a variable delay circuit, including a first delay portion that delays an input signal; an output portion; and a variable impedance portion provided coupled between the first delay portion and an the output portion.

Abstract: Provided are a digital phase interpolator, which performs linear phase interpolation irrelevantly to input order of two input signals, and a semi-digital delay locked loop (DLL), which includes and controls the same. The phase interpolator includes: a first clocked inverter controlled by a phase indicating signal and providing a first output signal to a common output terminal by inverting a first input signal, and a second clocked inverter controlled by the phase indicating signal and providing a second output signal to the common output terminal by inverting the second input signal. The second clocked inverter is clocked by the first input signal when the phase indicating signal is in a first logic state, and the first clocked inverter is clocked by the second input signal when the phase indicating signal is in a second logic state.

Abstract: Circuits, systems, and methods for generating a delayed clock signal. The circuit generally includes a first ramp generator configured to produce a first ramp signal in response to a reference clock signal, a first comparison circuit configured to compare the first ramp signal to a first threshold value in response to the reference clock signal to produce a comparison signal, a second ramp generator configured to produce a second ramp signal in response to the comparison signal, and a second comparison circuit configured to compare the second ramp signal to a second threshold value to produce the delayed clock signal.

Abstract: One embodiment of the present invention provides a system that biases a floating node within an integrated circuit. During operation, the system first identifies the floating node within the integrated circuit to be biased. The system then determines a desired bias voltage. Next, the system couples a low-power bias source to the floating node to supply the desired bias voltage, wherein the floating node is biased without stopping data transmission through the floating node during biasing.

Abstract: A delay circuit has a second delay element 8 supplied with a delay time control signal Vcntl from a frequency variable oscillator 2 including a first delay element 8 of which delay time as a concomitant of signal propagation is controlled by a delay time control signal and a phase inverting element 9 inverting a phase of the signal, and an adjusting element 10, connected in series to the second delay element 8, to which the signal is propagated, wherein a total of the delay time of the second delay element 8 and the delay time of the adjusting element 10 is adjusted.

Abstract: A semiconductor device wherein a delay chain is integrated; the semiconductor device having a semiconductor layer. The delay chain includes a plurality of delay cells placed in the semiconductor layer and electrically connected to each other so as to form the delay chain. The semiconductor device includes a first and second metal lines respectively connected to a supply voltage and a reference voltage and placed in a longitudinal direction on a surface of the semiconductor layer; each delay cell of the plurality of cells is electrically connected with the first and second metal lines. Any delay cell and its successive or preceding delay cells of the delay chain are placed in a transversal direction with respect to the first or the second metal line.

Abstract: Delay lock loop circuits are described, which may include two or more delay stages that each includes a plurality of selectable delay elements. A reference signal drives an input of the first delay stage, which provides a first output. The first output drives an input of the second delay stage, which provides a second output. The circuits further include a first selector register that is associated with the first delay stage. A value maintained in the first selector register determines a number of the selectable delay elements utilized in the first delay stage. The circuits further include a second selector register associated with the second delay stage. A value maintained in the second selector register determines a number of the selectable delay elements utilized in the second delay stage. Modification of the values maintained in the first and second selector registers are synchronized to the first and second outputs, respectively.

Abstract: A delay circuit includes an interface for giving a command of setting a delay time and a delay device that can be set to any desired delay time, and the delay time of the delay device is set according to a command from the interface.

Abstract: A circuit synchronizes parallel data of different timing for transfer. The synchronous data transfer circuit includes a plurality of first flip-flop circuits in which the parallel data are set by a data strobe signal, a plurality of delay circuits, and a plurality of second flip-flop circuits. By configuring the second flip-flop circuits to share generation of a delay amount, the second flip-flop circuits are utilized for data synchronization by the synchronous data transfer circuit. Thus, it becomes possible to configure the delay circuits with a remarkably reduced amount of delay elements.

Abstract: A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse.

Abstract: Certain exemplary embodiments can provide a system, which can comprise a circuit adapted to cause an actuation of an output device according to a control output. The control output can be generated comprising a control signal, the control signal extracted from a sequence of clock pulses. The sequence of clock pulses can comprise the control signal.

Abstract: A delay line architecture is presented. In one embodiment, the delay line is used to introduce delay compensation into a circuit design at the top level of the circuit design.