Abstract: Two delay chains having in each case n series-connected unidirectional delay elements are provided for controllably delaying electrical signals between a circuit input and at least one circuit output. Each delay element is an active circuit with a fixed transit time. The input of the first delay element of the first chain is connected to the circuit input and the output of each delay element of the first delay chain is selectively connectable to the input of the (n?i+1)th delay element of the second delay chain via a respectively associated switch of a first group of switches, wherein i=1 . . . n is the ordinal number of the delay elements of the first delay chain. The output of the last delay element of the second chain is connected as a circuit output.

Abstract: System and method of calibrating delay mismatch for high-spectral purity applications. For example, a method includes measuring the delay of one delay element at a time in a fixed topology by moving a time reference generated by an auxiliary delay-locked loop. The auxiliary DLL may have a replica structure of the primary DLL being calibrated. The calibration method uses one output clock signal of the primary DLL and measures delay mismatch using a reference phase previously measured using the same topology. The calibration method takes into account all delay mismatches in the topology up to the primary DLL output clock signal, including any delay generated by an associated multiplexer.

Abstract: A voltage controller (150), the controller comprising: a voltage comparator (700) operative to provide a digital error signal (152); a compensator (300) operative to determine a digital control signal (154) based on said provided error signal; and a modulator (400) operative to provide a power control signal (156) based on said determined digital control signal, wherein said comparator, said compensator, and said modulator are implemented entirely with digital logic gates.

Abstract: A delay circuit, including: a plurality of first delay units coupled in series and each configured to generate a delay time that is approximately double a unit delay time; a second delay unit configured to generate the unit delay time and coupled to a last stage of the plurality of first delay units; and a selector configured to select either an output signal of the last stage of the plurality of first delay units or an output signal of the second delay unit, wherein an external input signal is input to the first delay unit and to each second delay unit, and the first delay unit and the second delay unit each include a switch circuit configured to output with a delay either an output signal of a previous stage delay unit or the external input signal.

Abstract: A variable delay element includes first and second input stages, each input stage comprising a charge pumping circuit and a discharging circuit, each charge pumping circuit and each discharging circuit associated with the first and second input stages configured to operate on opposite phases of an input signal, and an output stage comprising at least two transistors. The transistors are independently controlled by the first and second input stages and produce an output signal which is a delayed version of the input signal.

Abstract: Disclosed is a semiconductor device having a delay adjusting circuit including a delay line having N stages of differential delay circuits and N stages of differential interpolators. A differential interpolator of an Mth (where M<N holds) stage receives an output signal of a differential delay circuit of the Mth stage and an output signal of a differential interpolator of an (M+1)th stage. A differential amplifier of an Nth stage receives an output signal of a differential delay circuit of the Nth stage as an input and synthesizes this signal into a signal with a synthesizing ratio of 100%. One differential interpolator from among differential interpolators from first to (N?1)th stages performs waveform synthesis over a range of 0% to 100% in accordance with an analog control signal from a digital-to-analog converter. The output of the differential interpolator of the first stage becomes an output signal, the delay of which has been adjusted.

Abstract: In a time measuring circuit, a pulse delay circuit is provided with a plurality of delay units. The pulse delay circuit is configured to transfer a pulse signal through the plurality of delay units while the pulse signal is delayed by the plurality of delay units. A delay time of each of the plurality of delay units depends on a level of a first drive voltage being input to each of the plurality of delay units. A generating circuit is configured to obtain a number of the delay units through which the pulse signal has passed within a predetermined period to generate, as time measurement data, digital data based on the obtained number. A first setting unit is configured to variably set the level of the first drive voltage being input to each of the plurality of delay units.

Abstract: One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned prior to fabrication as well as after fabrication. The three building blocks may be incorporated into a modular architecture, enabling designers to easily generate well-characterized, flexible, generic timer circuits.

Abstract: One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned prior to fabrication as well as after fabrication. The three building blocks may be incorporated into a modular architecture, enabling designers to easily generate well-characterized, flexible, generic timer circuits.

Abstract: An auto-calibration method is applied to a delay circuit, which includes a plurality of delay chains. If the number of accumulative errors of a designated delay chain as a current delay path is larger than a threshold value, the delay circuit scans all the delay chains and records their accumulative error numbers during a unit of time; otherwise, the current delay path is maintained. Afterwards, the number of accumulative errors is compared between all the delay chains to find out which one of the delay chains has a minimum accumulative error number, and the delay chain with a minimum accumulative error number is designated as a new current delay path.

Abstract: The present invention relates to an integrated circuit on a semiconductor chip with at least one phase shift circuit (56), at least one data input terminal (70) and at least one clock input terminal (38; 68), wherein the phase shift circuit (56) comprises at least two delay chains (10; 20) of the same kind, the delay chain (10; 20) comprises a plurality of inverting elements (12; 22), the phase shift circuit (56) comprises at least one digital control circuit (30), the delay chain (10; 20) is provided to delay a digital signal in a functional mode, the delay chain (10; 20) is provided to operate in a calibration mode, and at least two delay chains (10; 20) are provided to operate alternating between the functional mode and the calibration mode.

Abstract: A voltage measuring apparatus for a semiconductor integrated circuit includes a first delay unit configured to delay a reference clock in a first region, a second delay unit configured to delay the reference clock in a second region and an analysis unit configured to analyze a difference in voltage level between the regions based on the phases of associated with the delayed clock signals generated by the first and second delay units.

Abstract: A digital clock modulator provides a smoothly modulated clock period to reduce emitted electro-magnetic radiation (EMR). The digital clock modulator includes a plurality of delay elements connected in series and receiving as an input an unmodulated clock signal. A multiplexer receives inputs from unequally spaced taps between the delay elements. A control block provides selection inputs to the multiplexer, and receives the unmodulated clock signal from the delay elements. The delay elements include a last delay element providing the unmodulated clock signal to the control block. The last delay element has a predetermined delay for ensuring that the delay elements and related signal paths are in a same stable state before control to the multiplexer changes.

Abstract: A delay circuit, including: a plurality of first delay units coupled in series and each configured to generate a delay time that is approximately double a unit delay time; a second delay unit configured to generate the unit delay time and coupled to a last stage of the plurality of first delay units; and a selector configured to select either an output signal of the last stage of the plurality of first delay units or an output signal of the second delay unit, wherein an external input signal is input to the first delay unit and to each second delay unit, and the first delay unit and the second delay unit each include a switch circuit configured to output with a delay either an output signal of a previous stage delay unit or the external input signal.

Abstract: A delay line is periodically configured into a delay-locked loop for calibration purposes. That is, the delay line is operated in an open loop mode during a first time period in which a signal, such as an aperiodic signal, is the input signal into the delay line. Periodically, the delay line is configured into a delay-locked loop and the delay line is recalibrated based on a periodic signal supplied to the delay-locked loop.

Abstract: A system and method for adaptively providing a power supply voltage. The system includes an oscillator configured to receive an output voltage and generate a firs signal. The first signal is associated with a first frequency and a first period. Additionally, the system includes a frequency comparator configured to receive the first signal associated with the first frequency and a second signal associated with a second frequency and to generate a third signal if the first frequency and the second frequency are not equal, and a voltage regulator coupled to the frequency comparator and configured to generate the output voltage based on at least information associated with the third signal. The output voltage is received by a powered system, and the powered system is configured to receive a clock signal associated with a clock frequency. The clock frequency is equal to the second frequency.

Abstract: A controllable delay line includes an anti-jitter unit, a dependent current source, a first current mirror, a second current mirror, a regulation capacitor, a compensation capacitor and an output buffer unit. The anti-jitter unit receives a first bias voltage and produces a second bias voltage based on the first bias voltage. When the voltage source used in the controllable delay line has a variation, the second bias voltage varies therewith. The regulation capacitor is used for reducing the variation of the voltage difference between the voltage source and a node voltage of the first current source. The compensation capacitor is used for reducing the influence of a transition of the input signal of the output buffer unit on the node voltage, so as to lower the jitter amount of the output signal of the output buffer unit.

Abstract: The present invention provides a delay apparatus for delaying an input signal by a predetermined delay amount, including: a plurality of delay units for respectively delaying the input signal by the predetermined delay amount, each delay unit having a plurality of delay cells for respectively delaying the input signal by a certain delay period; and a sub decoding unit for generating a plurality of sub control signals to each of the delay units according to a first control signal and a selecting signal, wherein only delay cell of all the delay units is outputted at a time according to the sub controls signals.

Abstract: A semiconductor circuit allows a timing adjustment after detailed routing without rearrangement and rerouting, an adjustment of delay variance due to process variation, and a delay adjustment even after chip formation using a primitive cell with a built-in means for adjusting delay time. The circuit connected between an input pad and an output pad, an operating method for the same, and a delay time control system circuit, which externally adjusts delay time of a plurality of control terminal-equipped/variable capacitance embedded buffers configures a semiconductor circuit. The structure includes: a first buffer connected between the input pad and the output pad; and a plurality of capacitances connectable in parallel between a fixed potential and a current flowing path, which is positioned between the first buffer and the output pad, and that controls connection between each of the plurality of capacitances and the output pad.

Abstract: A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse.

Abstract: A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Abstract: A delay-locked loop includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includes delay cells having various unit time delays. The number of delay cells is adjusted in response to a shift signal. The delay line receives the external clock signal and outputs an output clock signal. The filter unit generates the shift signal in response to the error control signal. In the delay-locked loop, the front delay cells, which compensate for a delay of an external clock signal having a high frequency, have short unit time delays. The rear delay cells, which compensate for a delay of the external clock signal having a low frequency, have long unit time delays.

Abstract: A pulse jitter reduction circuit employs a low jitter system clock coupled to synchronize a pulse generating device and an ultra low jitter flip-flop to generate substantially jitter-free trigger signals employed to generate high voltage pulses for a flight tube of a time-of-flight mass spectrometer. By eliminating time fluctuations due to jitter in the triggering signal, the predictability of the arrival time of ions along a flight tube of a time-of-flight mass spectrometer is greatly improved, thereby improving the resolution of the mass spectrometer.

Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: One embodiment pertains generally to a method of delaying based on a single clock signal. The method includes providing a first clock signal and generating a second clock signal based on the first clock signal and a third clock signal that is the inverse of the second clock signal. The method also includes generating a unit of delay based the first clock single and generating a half unit of delay based on the first and second clock signal.

Abstract: A delay circuit includes: an input signal line (IN) through which an input signal is inputted; a capacitor (106) charged with and discharging electric charge; a first switch (101) connected to the input signal line and operating according to the input signal when the capacitor is to be charged with electric charge; a second switch (102) connected to the input signal line and operating according to the input signal when the electric charge is to be discharged from the capacitor; and a comparison circuit (107) comparing a voltage of the capacitor and a reference voltage to output a delay signal of the input signal.

Abstract: An analog delay circuit to impart a group delay to an analog input signal is described. The analog delay circuit may comprise a capacitor to impart at least a portion of the group delay to the analog output signal and a buffer circuit coupled between the capacitor and an input stage to substantially remove at least a portion of a capacitive load at the input stage.

Abstract: The invention relates to a DLL circuit for providing an adjustable time delay of a periodic input signal, said circuit having controllable delay elements which are connected in series and form a delay chain, having a phase detector in order to generate a control signal on the basis of the periodic input signal and a periodic signal which has been delayed by the delay chain, the delay of each of the delay elements being adjusted on the basis of the control signal, and having a selection unit which is respectively connected to one of the delay elements in order to apply an output signal from one of the delay elements to an output of the DLL circuit on the basis of a selection variable which has been provided, and a compensation circuit which modifies the selection signal such that an additional delay (which is caused at least by the selection unit) between the periodic input signal and the output signal from the DLL circuit is compensated for.

Abstract: A memory device, delay lock loop circuit (DLL) and DLL reset circuitry are described. The DLL includes a shift register and a measured delay for pre-loading the shift register. The reset circuitry selectively filters a clock signal propagation through the measured delay during a reset operation.

Abstract: A delay circuit includes a delay time setting circuit to set a delay time of an output signal with respect to an input signal, a first transistor connected to an input terminal of the delay time setting circuit and configured to set a first voltage to the input terminal of the delay time setting circuit and a second transistor connected to an output terminal of the delay time setting circuit and configured to reset the output terminal of the delay time setting circuit to a second voltage and clear the reset of the output terminal of the delay time setting circuit after the first voltage is set.

Abstract: A delay circuit comprises a plurality of delay blocks connected in series, and a driving portion adapted to logically combine signals transmitted by the plurality of delay blocks to generate a delay circuit output signal. Each of the plurality of delay blocks delays an output signal from an immediately previous delay block and transmits a resulting delayed output signal to a next delay block when a delay operation is enabled based on a corresponding control signal. However, where the delay operation of a delay block is disabled based on the corresponding control signal, the delay block transmits the output signal of the immediately previous delay block to the driving portion.

Abstract: A system for verifying signal propagation delays of circuit traces of a printed circuit board (PCB) layout includes a computer (1). The computer includes: a setting module (10) for setting a minimum propagation delay and a maximum propagation delay for a trace to be verified, and making a selection regarding whether to calculate a propagation delay of a lead wire connected with the trace; a selecting module (11) for selecting a segment from a segment set of the trace; a calculating module (12) for calculating a propagation delay of the segment, the trace and the lead wire, and a total propagation delay; and a determining module (13) for determining whether all segments of the trace have been calculated, and whether the total propagation delay is between the minimum propagation delay and the maximum propagation delay. A related method is also disclosed.

Abstract: An apparatus and method for an analog fine delay line, a hybrid delay line, and a delay locked loop (DLL) is described. In the DLL, a coarse phase detector compares a reference signal and feedback signal in controlling coarse phase adjustment signals indicating whether a delay of a coarse delay line should be increased or decreased. Similarly, a fine phase detector compares the reference signal and feedback signal to generate a locking bias signal, which may increase or decrease a delay of an analog fine delay line. The analog fine delay line and coarse delay line may be connected in series creating the hybrid delay line having a total delay comprised of the coarse delay and the fine delay. Additionally, a fine bias generator may control the fine delay in response to an initiating bias signal from an analog phase generator or the locking bias signal.

Abstract: A voltage controlled delay line (VCDL). The VCDL includes one or more cells. Each of the one or more cells includes two or more inputs and an output. Each of the one or more cells is configured to provide a delay as well as an interpolation function and a multiplexer function. The VCDL may be used to provide delay in a delay locked loop (DLL).

Abstract: A system and method for adaptively providing a power supply voltage. The system includes an input/output subsystem configured to receive a first voltage, an analog subsystem configured to receive a second voltage and coupled to the input/output subsystem, a first digital subsystem configured to receive a third voltage and coupled to the input/output subsystem, and a second digital subsystem configured to receive a fourth voltage and coupled to the input/output subsystem, the first digital subsystem, and the analog subsystem. Additionally, the system includes a first adaptive power supply configured to receive an input voltage and generate the third voltage, and a second adaptive power supply configured to receive the input voltage and generate the fourth voltage.

Abstract: A delay line for a ring oscillator circuit includes at least one delay stage having a multiple logic gate delay cells driven by a multiplexer. The multiplexer is symmetrically configured and includes multiple logic gates that are similar to the logic gates of the delay stage.

Abstract: A delta-sigma modulator that provides improved SNR performance in applications such as low-power mobile wireless communications and high frequency radar applications is disclosed. Multiple comparators 10, each comprising a sequence of three latches 20, 22, 24, connect the modulator's input filter circuit 12 to the modulator's output interfaces 14, providing quantization of the integrated, filtered signal provided by the filter circuit 12. A clock signal having a cycle period Tc enables a first latch 20 connected to the signal input of each comparator 10 to provide a digital signal to the signal input of a second latch 22. The second latch 22 supplies a digital signal to a third latch 24 in the sequence, in response to the signal received from the first latch 20, by a lagged clock signal derived from the given clock signal Tc by providing a first lag time TL where Tc/2?TL>0. A third latch in the sequence is enabled by a clock signal having a second lag time TS=Tc/2+TE, and the delay TE<<Tc/2.

Abstract: A delay line includes a delay chain consisting of series-connected NAND gate delay stages with a delayed output signal extracted from the final delay stage. Tap decode gates are preferably used to “inject” the input signal to be delayed into the delay chain using one input of the NAND gate delay stage, referred to as an “injection point.” The desired delay is achieved by selecting an injection point relative to the final delay stage, or exit point, of the delay chain. Selection of an injection point is provided by the binary decode of a tap address that activates the injection NAND gate delay stage, allowing the injected signal to propagate from the activated injection point to the exit point of the delay chain.

Abstract: A delay circuit is constructed by connecting taps TAP0–n for providing with a unit delay time (?) in series on multiple stages. Each tap has the same configuration and an objective signal is inputted to a signal input terminal IN1. The output terminal of a preceding stage tap is connected to a between-stages connecting terminal IN2. An output terminal O is connected to the between-stages connecting terminal of a next stage tap. The signal input terminal and the between-stages connecting terminal are connected to one input terminal of NAND gates 1, 2 and a tap selection signal is inputted to the other input terminal. The output terminal is connected to a NAND gate 3. One of the NAND gates 1, 2 functions as a logical inversion gate corresponding to a tap selection signal so as to enable propagation of the signal. At this time, in the other NAND gate, the output signal is fixed to high level and the NAND gate 3 also functions as a logical inversion gate.

Abstract: A digital delay line including a first feedback delay line having a first number of interlinked first delay elements, at least one second feedback counter having a second number of second interlinked counting elements, the counting elements being clocked by one of the first delay elements.

Abstract: A delay signal generator circuit is provided. A delay circuit including a plurality of series-connected inverters for sequentially delaying a first clock signal and for generating a plurality of delay signals and a multiplexer for selecting one of the delay signals. A delay control circuit samples the selected delay signal in response to a transition of a second clock signal. The second clock signal has twice the frequency of the first clock signal, and the delay control circuit controls the delay circuit based upon the sampled value(s) so that the selected delay signal output from the delay circuit has a delay time of ¼ clock cycle relative to the first clock signal.

Abstract: A delay locked loop includes a forward path for receiving an input signal to provide an output signal, a feedback path for providing a feedback signal based on the output signal, and a controller responsive to a timing relationship between the feedback signal and the input signal for adjusting a timing of the output signal. The feedback path includes an adjustable delay circuit for adjusting a timing of the feedback signal.

Abstract: To enhance the accuracy of the delay time of the delay device by reducing the change in the power supply voltage for the delay device, and a delay device that delays an incoming transmission signal, comprising: a delay element that operates on a power supply voltage Vdd and a power supply voltage Vss and delays the transmission signal, the voltage Vdd being larger than the voltage Vss; an addition circuit that outputs to an output of the delay element, a predetermined voltage that is larger than the voltage Vss and smaller than the voltage Vdd. This delay element includes a digital circuit that outputs one of output voltages of two possible values in correspondence with an input voltage. Furthermore, the addition circuit outputs a voltage substantially similar to a threshold voltage that said output of the digital circuit inverts from one of the output voltages of two possible values to another thereof.

Abstract: An apparatus and method for an analog fine delay line, a hybrid delay line, and a delay locked loop (DLL) is described. In the DLL, a coarse phase detector compares a reference signal and feedback signal in controlling coarse phase adjustment signals indicating whether a delay of a coarse delay line should be increased or decreased. Similarly, a fine phase detector compares the reference signal and feedback signal to generate a locking bias signal, which may increase or decrease a delay of an analog fine delay line. The analog fine delay line and coarse delay line may be connected in series creating the hybrid delay line having a total delay comprised of the coarse delay and the fine delay. Additionally, a fine bias generator may control the fine delay in response to an initiating bias signal from an analog phase generator or the locking bias signal.

Abstract: A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Abstract: An apparatus for generating a phase delay is disclosed. The apparatus includes a buffer utilized for buffering an input signal and then outputting an output signal; a digital to analog converter (DAC) utilized for converting a digital value representative of phase delay into a corresponding control voltage and outputting a control voltage; and a variable capacitor that has a capacitance value controlled by the control voltage. By controlling the variable capacitance value, the apparatus for generating a phase delay can adjust the phase delay between the input signal and the output signal.

Abstract: A method of transmitting adjacent signals is disclosed. Sensing is performed on signals in the group and adjacent signals are either switched or delayed if the adjacent signals are switching at the same time. The method is used in networks where coupling and capacitance effects are possible.

Abstract: A delay line unit of a delay locked loop (DLL) circuit, includes a first delay line having a plurality of first unit delays, each first unit delay having a first delay; a second delay line having a plurality of second unit delays, each second unit delay having a second delay; and a third delay line having a plurality of third unit delays, each third unit delay having a third delay, wherein the first delay is shorter than the second delay, and the second delay is shorter than the third delay.

Abstract: A device which may be configured to generate delayed clock signals by a specified phase difference, which may include a clock generator circuit for generating at least one clock signal, a delayed clock signal generator for delaying the at least one clock signal, a phase detect circuit for generating a selecting signal based on the amount of phase delay detected according to a half-cycle (?), and in comparison with the clock signal, a phase interpolation circuit for controlling the delay time of the delayed clock signals and interpolating the delayed clock signals, and a selecting circuit which outputs the delayed clock signal delayed by a specified phase difference.

Abstract: A clock data recovery (CDR) circuit to recover a clock signal and data signal from an input signal. The CDR circuit includes a control circuit, a select circuit and a phase adjust circuit. The control circuit generates a first control signal according to a phase relationship between the input signal and a first clock signal. The select circuit is coupled to receive the first control signal from the control circuit and coupled to receive a second control signal. The select circuit is responsive to a select signal to select either the first control signal or the second control signal to be output as a selected control signal. The phase adjust circuit is coupled to receive the selected control signal from the select circuit, the phase adjust circuit being responsive to the selected control signal to adjust the phase of the first clock signal.