Having Specific Active Circuit Element Or Structure (e.g., Complementary Transistors, Etc.) Patents (Class 327/285)
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Publication number: 20100308871Abstract: A delay chain circuit including at least two delay elements, wherein each delay element is configured to: receive a first signal; output a second signal after a delay period; and be operable in at least two modes of operation wherein in a first mode of operation each delay element has a first delay period and in a second mode of operation each delay element has a second delay period.Type: ApplicationFiled: December 19, 2008Publication date: December 9, 2010Inventors: Petri Antero Helio, Jouni Tapio Kinnunen, Niko Juhani Mikkola, Paavo Sakari Vaananen
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Publication number: 20100295593Abstract: A delay circuit (100) includes capacitor elements constituted of nMOS transistors (141, 142) between an input inverter circuit (110) and an output inverter circuit (120). The input inverter circuit (110) includes a pMOS transistor (PM1) and an nMOS transistor (NM1) that are directly connected between a power source potential (VDD) and a ground potential (VSS) through a resistor (R1). Between a signal line (130) and the gate of the nMOS transistor (141), and between the signal line (130) and the gate of the nMOS transistor (142), pMOS transistors (151, 152) are provided, respectively. In this structure, in the case where an input signal is changed from L to H, the PVT sensitivity of a delay circuit is automatically alleviated. As a result, the PVT sensitivity is automatically alleviated.Type: ApplicationFiled: May 3, 2010Publication date: November 25, 2010Inventor: Masahiro YOSHIDA
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Patent number: 7728643Abstract: A delay circuit that includes a logic gate through which an input signal passes, a capacitor configured to be charged and discharged at an output terminal of the logic gate and delaying the input signal, and a mirroring unit configured to constantly maintain current output by the logic gate by mirroring current output by a constant current source.Type: GrantFiled: December 3, 2008Date of Patent: June 1, 2010Assignee: Hynix Semiconductor, Inc.Inventor: Kwang-Myoung Rho
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Patent number: 7688020Abstract: A step motor driving circuit is provided. An exemplary step motor driving circuit includes an input voltage source set, a reference voltage source, a voltage level shift unit, a logic unit, a reset voltage source, and an output voltage terminal. The input voltage source set provides an input voltage set. The reference voltage source provides a reference voltage. The voltage level shift unit raises one of the levels of the input voltage set to a level of the reference voltage. The logic unit receives the reference voltage and the input voltage set and outputs a control voltage. The reset voltage source outputs a reset voltage to reset the logic unit. The output voltage terminal receives the control voltage and outputs an output voltage.Type: GrantFiled: July 24, 2007Date of Patent: March 30, 2010Assignee: Princeton Technology CorporationInventor: Jung-Yen Kuo
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Publication number: 20090219073Abstract: A time-to-digital converter (TDC) can have a resolution that is finer than the propagation delay of an inverter. In one example, a fractional-delay element circuit receives a TDC input signal and generates therefrom a second signal that is a time-shifted facsimile of a first signal. The first signal is supplied to a first delay line timestamp circuit (DLTC) and the second signal is supplied to a second DLTC. The first DLTC generates a first timestamp indicative of a time between an edge of a reference input signal to the TDC and an edge of the first signal. The second DLTC generates a second timestamp indicative of a time between the edge of the reference input signal and an edge of the second signal. The first and second timestamps are combined and together constitute a high-resolution overall TDC timestamp that has a finer resolution than either the first or second timestamps.Type: ApplicationFiled: March 3, 2008Publication date: September 3, 2009Applicant: QUALCOMM INCORPORATEDInventors: Bo Sun, Zixiang Yang
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Publication number: 20090212838Abstract: A delay circuit has a long delay time and a semiconductor device includes the delay circuit. The delay circuit includes an inverter circuit unit having at least one inverter. Each of the inverters includes a first transistor connected to a supply voltage and a second transistor connected to a ground voltage. The inverter circuit unit receives a first signal and outputs a second signal by delaying the first signal. At least one capacitor unit is connected to an input terminal of the inverter such that a loading capacitance of the inverter circuit unit is increased.Type: ApplicationFiled: February 24, 2009Publication date: August 27, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Tae-Hyung Kim, Min-Su Kim
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Patent number: 7576586Abstract: In a differential bucket-brigade device (BBD) pipeline it is necessary for proper circuit function to maintain the common-mode charge within an acceptable range at each pipeline stage. Embodiments of the present invention provide for reducing common-mode charge variations in a differential charge-domain pipeline. Common mode charge at a given stage of the pipeline is adjusted according to one or more measured characteristics, thereby controlling common mode charge variation throughout the differential charge-domain pipeline.Type: GrantFiled: February 8, 2008Date of Patent: August 18, 2009Assignee: Kenet, Inc.Inventor: Michael P. Anthony
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Patent number: 7573769Abstract: A sense amplifier enable signal generator has two stages. Each stage offsets transistor performance variation in the other stage to produce an enable signal output relatively immune from the effects associated with transistor mismatches. In one embodiment, a memory device comprises a plurality of memory cells, sense amplifier circuitry and the enable signal generator. The sense amplifier circuitry is coupled to one or more of the memory cells and senses the state of the one or more memory cells when enabled. The enable signal generator has first and second stages and generates an enable signal applied to the sense amplifier circuitry. The enable signal generator counteracts delay variation when generating the enable signal so that operation of the enable signal generator is substantially unaffected by transistor performance variation in either stage of the enable signal generator.Type: GrantFiled: January 3, 2008Date of Patent: August 11, 2009Assignee: Qimonda North America Corp.Inventor: Hoon Ryu
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Patent number: 7564285Abstract: A controllable delay line includes an anti-jitter unit, a dependent current source, a first current mirror, a second current mirror, a regulation capacitor, a compensation capacitor and an output buffer unit. The anti-jitter unit receives a first bias voltage and produces a second bias voltage based on the first bias voltage. When the voltage source used in the controllable delay line has a variation, the second bias voltage varies therewith. The regulation capacitor is used for reducing the variation of the voltage difference between the voltage source and a node voltage of the first current source. The compensation capacitor is used for reducing the influence of a transition of the input signal of the output buffer unit on the node voltage, so as to lower the jitter amount of the output signal of the output buffer unit.Type: GrantFiled: May 29, 2007Date of Patent: July 21, 2009Assignee: Faraday Technology Corp.Inventors: Chia-Wei Chang, Yeong-Jar Chang
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Patent number: 7548104Abstract: A delay line including a sequence of identical delay cells with improved gain and in built duty cycle distortion control and a method thereof is disclosed. Each delay cell of the sequence includes a current source, four transistors, and a load capacitor. A gate of the current source receives a voltage bias that controls a delay of the delay cell. A drain of the first transistor is connected to the drain of the current source. The first and second transistor gates receive an input clock signal. The second transistor drain is connected to the source of the current source. The third transistor gate and the load capacitor are also connected to the drain of the current source. The fourth transistor drain is connected to the third transistor drain. The fourth transistor gate is coupled to an output of a second consecutive delay cell for duty cycle distortion control.Type: GrantFiled: June 10, 2007Date of Patent: June 16, 2009Assignee: Cosmic Circuits Private LimitedInventors: Prasenjit Bhowmik, Sundararajan Krishnan, G. Sriram
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Publication number: 20090079487Abstract: A time delay line comprises a plurality of delay elements connected in series. Each delay element comprises one or more transistors that exhibit a reverse short channel effect at channel lengths within a certain range. The transistors are configured to have a channel length in the certain range in order to reduce time delay sensitivity to process variations.Type: ApplicationFiled: September 26, 2007Publication date: March 26, 2009Applicant: Telefonaktiebolaget LM Ericsson (publ)Inventors: Torkel Arnborg, Roland Strandberg
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Publication number: 20090058488Abstract: Disclosed herein is a delay circuit for performing one of a charge and a discharge in two stages, and delaying a signal, the delay circuit including an output section configured to output a delayed signal; two power supplies; and a delay inverter; wherein the delay inverter has a first transistor and a second transistor of an identical channel type for one of a first charge and a first discharge, the first transistor and the second transistor being connected in series with each other between the output section and one power supply, and the delay inverter has a third transistor of a different channel type from the first transistor and the second transistor for one of a second charge and a second discharge, the third transistor being connected in parallel with one of the first transistor and the second transistor.Type: ApplicationFiled: August 18, 2008Publication date: March 5, 2009Applicant: Sony CorporationInventors: Werapong Jarupoonphol, Yoshitoshi Kida
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Patent number: 7498859Abstract: A driving device using a CMOS inverter performs a stable operation by using a compensating circuit to compensate variation widths when the process condition or external environment is changed. The driving device comprises a power regulating unit for regulating a driving voltage level depending on characteristics of a MOS transistor and a delay unit comprising a plurality of CMOS inverters driven by the driving voltage regulated by the power regulating unit.Type: GrantFiled: June 29, 2004Date of Patent: March 3, 2009Assignee: Hynix Semiconductor Inc.Inventor: Keun Kook Kim
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Patent number: 7486125Abstract: Delay line circuits include a plurality of delay cells connected in series. The delay cells respectively include a first to a third logic gate. The first logic gate, in response to a selection signal, generates a first signal based on an input signal. The second logic gate generates a second signal based on the input signal in response to the selection signal. The third logic gate generates a third signal based on either a return signal or an output signal of the second logic gate.Type: GrantFiled: July 11, 2006Date of Patent: February 3, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Kwan-Yeob Chae
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Publication number: 20090002046Abstract: In a skew signal generation circuit, a pad is connected to an external resistor and a code generator compares a voltage of the pad with a reference voltage to generate a plurality of codes. A skew signal extractor extracts a skew signal from the codes, the skew signal containing information about a current characteristic of a MOS transistor. A driver calibrates a drivability in response to the skew signal.Type: ApplicationFiled: December 27, 2007Publication date: January 1, 2009Inventor: Ho Uk Song
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Publication number: 20080238516Abstract: A programmable timing interpolator circuit includes low output impedance buffer circuitry driving a node having a capacitance that varies in response to a programmed delay to be introduced by the interpolator. The low output impedance buffer circuitry receives a subset of course delay signals and, after buffering, provides the buffered course delay signals to fine delay circuitry. The buffer may include two source follower stages coupled to each other. The first source follower stage shifts the level of the received signal down. The second source follower stage shifts the level of the signal from the first source follower stage up. The first and second source follower stages are implemented using NMOS and PMOS technology.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Applicant: Teradyne, Inc.Inventor: Cosmin Iorga
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Patent number: 7408394Abstract: A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A digital signal is applied to an initial delay unit in the measuring delay line and it sequentially propagates through the delay units until a second digital signal is received. These outputs are applied to control inputs to the signal generating delay line to control the number of delay units through which a clock signal propagates before being output from a final delay unit. Each of the delay units in the measuring delay line includes a pair of series connected NOR gates. A NOR gate to which the digital signal is initially applied is coupled to a second NOR gate as a flip-flop so that the output of the NOR gate remains constant after the digital signal has been applied to the measuring delay line.Type: GrantFiled: September 11, 2007Date of Patent: August 5, 2008Assignee: Micron Technology, Inc.Inventor: David A. Zimlich
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Patent number: 7362155Abstract: One embodiment pertains generally to a method of delaying based on a single clock signal. The method includes providing a first clock signal and generating a second clock signal based on the first clock signal and a third clock signal that is the inverse of the second clock signal. The method also includes generating a unit of delay based the first clock single and generating a half unit of delay based on the first and second clock signal.Type: GrantFiled: December 29, 2005Date of Patent: April 22, 2008Assignee: Xerox CorporationInventor: Chi M. Pham
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Patent number: 7288978Abstract: In a delay circuit, when a first conductivity-type transistor (M6) becomes conductive on the basis of one level of its input signal, a first current path is formed through a source side transistor (M4), the first conductivity-type transistor (M6), and a second drive transistor (M9) between a source power line and a sink power line, and its output signal being the delayed inverse of the one level of the input signal is output from a connection point of another source side transistor (M5) and a sink side transistor (M11), and when a second conductivity-type transistor (M7) becomes conductive on the basis of the other level of the input signal, a second current path is formed through a first drive transistor (M3), the second conductivity-type transistor (M7), and another sink side transistor (M10), and the output signal being the delayed inverse of the other level of the input signal is output from the connection point.Type: GrantFiled: January 30, 2006Date of Patent: October 30, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Hirohisa Suzuki, Kazuo Hasegawa, Eiji Akama
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Patent number: 7274237Abstract: A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A digital signal is applied to an initial delay unit in the measuring delay line and it sequentially propagates through the delay units until a second digital signal is received. These outputs are applied to control inputs to the signal generating delay line to control the number of delay units through which a clock signal propagates before being output from a final delay unit. Each of the delay units in the measuring delay line includes a pair of series connected NOR gates. A NOR gate to which the digital signal is initially applied is coupled to a second NOR gate as a flip-flop so that the output of the NOR gate remains constant after the digital signal has been applied to the measuring delay line.Type: GrantFiled: September 1, 2005Date of Patent: September 25, 2007Assignee: Micron Technology, Inc.Inventor: David A. Zimlich
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Patent number: 7167035Abstract: One use for delay adjustment circuit (32), coarse-grain delay offset circuit (34), and fine-grain delay synthesis circuit (36) may be as part of a delay replication circuit (30) used to replicate the frequency versus voltage behavior of an integrated circuit (29). Also, a circuit (30) and method for determining optimal power and frequency metrics of integrated circuit (29) is also described. In addition, a method for determining programmable coefficients to replicate frequency and supply voltage correlation is described.Type: GrantFiled: February 22, 2005Date of Patent: January 23, 2007Assignee: Freescale Semiconductor, Inc.Inventor: Lipeng Cao
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Patent number: 7102407Abstract: A delay circuit. The delay circuit includes a first circuit, a falling edge delay circuit and a rising edge delay circuit. The first circuit includes a circuit input for receiving a reference signal and a circuit output for outputting a delayed signal. The falling edge delay circuit is coupled to the first circuit to control delay of a falling edge of the reference signal. The rising edge delay circuit is coupled to the first circuit to control delay of a rising edge of the reference signal.Type: GrantFiled: March 31, 2004Date of Patent: September 5, 2006Assignee: Intel CorporationInventor: Darren Slawecki
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Patent number: 7038519Abstract: A digital clock manager having differential clock signal paths is provided. The differential clock signal paths are provided by replacing single-ended circuit elements of a conventional digital clock manager with symmetrical cascade voltage switch logic (CVSL) circuit elements, including CVSL delay buffers, CVSL multiplexers, CVSL AND gates, CVSL OR gates and CVSL set-reset latches. These symmetrical CVSL AND gates, CVSL OR gates and CVSL set-reset latches represent new circuit elements.Type: GrantFiled: April 30, 2004Date of Patent: May 2, 2006Assignee: Xilinx, Inc.Inventors: Raymond C. Pang, Jennifer Wong
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Patent number: 7019576Abstract: A circuit having a process, voltage, and temperature (PVT) invariant delay element is disclosed. In one embodiment, the present invention includes a first and second operational transconductance amplifier (OTA), a first and second switched capacitor driven by a clock, and a first and second clock-controlled switch. In addition, the present invention includes a trip inverter, a delay inverter, and a plurality of transistors. In so coupling the first and second OTA, the first and second switched capacitor, the first and second clock-controlled switch, the trip inverter, the delay inverter, and the plurality of transistors, a circuit having a PVT invariant delay element is provided.Type: GrantFiled: March 18, 2004Date of Patent: March 28, 2006Assignee: Cypress Semiconductor CorporationInventors: Sanjay K. Sancheti, Suwei Chen
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Patent number: 7012459Abstract: One embodiment of the present invention provides a system that regulates heat within an asynchronous circuit. During operation, the system monitors a temperature within the asynchronous circuit. If the temperature exceeds a threshold value, the system introduces a delay into the asynchronous circuit that causes signals to propagate more slowly through the asynchronous circuit. This causes circuit elements within the asynchronous circuit to switch less frequently and consequently causes the circuit elements to generate less heat.Type: GrantFiled: May 20, 2003Date of Patent: March 14, 2006Assignee: Sun Microsystems, Inc.Inventor: Ivan E. Sutherland
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Patent number: 6900683Abstract: A semiconductor arrangement is provided for generating a predetermined time delay. Two clocks are connected to two parallel, redundant semi-conductor circuits emitting clock signals from multiplexers. The redundant circuits receive delayed clock signals from one of the clocks, and from the other clock, clock signals that are delayed in adjustable delay circuits to be phased in with the clock signals from the first clock. A number of delay elements and a first reference number of delay elements, providing a predetermined delay time, are connected in a reference delay circuit. A quotient of the two numbers is stored. One of the semi-conductor circuits is replaced by an alternative semi-conductor circuit, the reference delay circuit of which is set on the predetermined delay time, corresponding to a second reference number of delay elements. An adjustable delay circuit is set on the same delay time as the replaced semi-conductor circuit by means of the second reference number and the quotient.Type: GrantFiled: December 5, 2000Date of Patent: May 31, 2005Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Mikael Lindberg, Stefan Davidsson, Ulf Hansson
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Patent number: 6885231Abstract: A method and apparatus for delay tuning an integrated circuit which includes a delay element that includes a plurality of delay stages interconnected in a cascaded relationship, each stage imposing an incremental delay upon the input signal when enabled, the delay element receives a selection signal that determines how many of the delay stages are enabled. By varying the select signal, the delay element imposes, a variable delay upon the input signal for testing and evaluation.Type: GrantFiled: June 20, 2003Date of Patent: April 26, 2005Assignee: Intel CorporationInventors: Ravishankar Kuppuswamy, Gregory Taylor
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Patent number: 6798298Abstract: A balancing circuit and method of operation thereof for use with a circuit having first and second complementary drivers exhibiting different current gain characteristics. In one embodiment, the balancing circuit includes a sensing subcircuit that provides a correction signal indicating a first current gain characteristic of the first driver. The balancing circuit also includes a compensation subcircuit that generates a current gain compensation signal to the first driver to substantially match a second current gain characteristic of the second driver based on the correction signal.Type: GrantFiled: November 16, 2001Date of Patent: September 28, 2004Assignee: Agere Systems Inc.Inventors: Paul C. Davis, Irving G. Post
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Patent number: 6788126Abstract: A transition delay circuit having an input terminal and an output terminal is disclosed. According to one embodiment, the transition delay circuit also includes a first MOS capacitor, a second MOS capacitor, and a delay circuit. The first MOS capacitor includes a first terminal connected to the input terminal of the transition delay circuit and a second terminal that is connected to the output terminal of the transition delay circuit. The second MOS capacitor includes a first terminal connected to the input terminal of the transition delay circuit and a second terminal that is connected to the output terminal of the transition delay circuit. The second MOS capacitor has a different polarity than the first MOS capacitor. The delay circuit includes a first terminal connected to the input terminal of the transition delay circuit and a second terminal that is connected to the output terminal of the transition delay circuit.Type: GrantFiled: December 11, 2002Date of Patent: September 7, 2004Assignee: Micron Technology, Inc.Inventor: Eric J. Stave
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Patent number: 6686788Abstract: A delay circuit of a clock synchronization device that includes an operational amplifier for setting the level of a current control voltage according to a voltage difference between a regulation voltage and a reference voltage. A number of unit delay cells connected in series are included, each having a delay time set according to a resistance control voltage and the current control voltage. Also, a variable resistance unit is included having a resistance value adjusted according to the resistance control voltage, where the variable resistance unit includes a cross coupled adjustment device that outputs signals to a next unit delay cell. The delay cells are controlled by using the operational amplifier and a replica cell to have a wide delay range. As a result, the working range can be set wide, jitters may be reduced and the chip size may also be reduced.Type: GrantFiled: May 6, 2002Date of Patent: February 3, 2004Assignee: Hynix Semiconductor Inc.Inventors: Se Jun Kim, Sang Hoon Hong
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Patent number: 6628157Abstract: A method and apparatus for delay tuning an integrated circuit which includes a delay element that includes a plurality of delay stages interconnected in a cascaded relationship, each stage imposing an incremental delay upon the input signal when enabled, the delay element receives a selection signal that determines how many of the delay stages are enabled. By varying the select signal, the delay element imposes a variable delay upon the input signal for testing and evaluation.Type: GrantFiled: December 12, 1997Date of Patent: September 30, 2003Assignee: Intel CorporationInventors: Ravishankar Kuppuswamy, Gregory Taylor
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Patent number: 6624680Abstract: In one embodiment, a digital circuit element has a propagation delay that is substantially constant over a range of supply voltages applied to the digital circuit element. In another embodiment, a digital circuit element may include an input node, an output node, and at least one gate coupling the input node and the output node. A plurality of possible voltage transition curves may be associated with a corresponding change of a first voltage at the input node over time, each voltage transition curve being determined by a corresponding supply voltage and the curves intersecting within a relatively narrow range of voltages. The gate may be operable to change a second voltage at the output node in response to the first voltage reaching a threshold voltage of the gate, and the threshold voltage may be set within the relatively narrow range of voltages in which the voltage transition curves intersect in order to reduce the dependence of the propagation delay on the supply voltage.Type: GrantFiled: December 3, 2001Date of Patent: September 23, 2003Assignee: Texas Instruments IncorporatedInventor: Stephen R. Schenck
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Patent number: 6549051Abstract: A method for generating a variable delay of a signal, including: providing a clock indicating a sequence of sample times at regular intervals and receiving a sequence of input samples representing input values of the signal at respective sample times indicated by the clock. The method further includes determining the delay with a temporal resolution substantially finer than the clock interval to be applied to the signal at each of the respective sample times. For each of the sample times, responsive to the respectively-determined delay, one or more of the input samples are processed so as to generate a corresponding output sample representing a delayed output value of the signal at the sample time.Type: GrantFiled: March 20, 2000Date of Patent: April 15, 2003Assignee: Qualcomm, Inc.Inventors: Maurizio Di Veroli, Ayal Bar-David
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Patent number: 6525583Abstract: A compensation circuit includes at least one of an n-channel device connected to oppose a high-to-low transition and a p-channel device connected to oppose a low-to high transition. The n-channel and p-channel devices may be diodes, transistors, or transistors connected to function as diodes. The n-channel and p-channel devices may be connected to a large variety of devices and circuits, such as phase locked loops, delay locked loops, clock circuits, or any circuit which requires two balanced paths, one through n-channel devices and one through p-channel devices, to compensate for process variations. Methods for balancing a circuit path and compensating for process variations are also disclosed.Type: GrantFiled: January 16, 2002Date of Patent: February 25, 2003Assignee: Micron Technology, Inc.Inventor: Brian W. Huber
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Patent number: 6515529Abstract: The present invention is directed to a transition delay circuit. The transition delay circuit includes a delay circuit which is responsive to an input signal. The transition delay circuit produces an output signal at a common node. The transition delay circuit also includes a first MOS capacitor connected between the input signal and the common node and a second MOS capacitor connected between the input signal and the common node. A method for delaying an input signal to a buffer circuit is also disclosed.Type: GrantFiled: August 13, 2001Date of Patent: February 4, 2003Assignee: Micron Technology, Inc.Inventor: Eric J. Stave
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Patent number: 6492847Abstract: A digital driver circuit with one or more CMOS inverters intended as input stages, whereby for the MOS FETs of the inverters the channel width/length (W/L) ratio increases from stage to stage. The digital driver circuit includes an intermediate stage with two further CMOS inverters, connected between a supply voltage Vcc and ground. The driver circuit also includes an output stage having two MOS FETs with the drain terminals of both the MOS FETs of the output stage connected both to each other and to the output of the circuit, the W/L ratio of both MOS FETs exceeding that of the MOS FETs of the intermediate stage. The switch-over of the two MOS FETs of the output stage, occurring with changes of the digital input signal at the input of the circuit, is offset in time with respect to each other, thereby reducing current peaks.Type: GrantFiled: October 12, 2000Date of Patent: December 10, 2002Assignee: Texas Instruments Deutschland GmbHInventors: Laszlo Goetz, Stefan Reithmaier, Martin Rommel
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Patent number: 6456137Abstract: First and second wires are disposed adjacent to each other. Even pairs of buffers and inverters are disposed on the wires. A buffer and an inverter in each of the pairs are disposed on the first or second wires respectively. The first and second wires are respectively divided to even wire sections by the even pairs and a device or terminal connected to the output side of the pairs. Lengths of the wire sections are equal to each other between adjacent wire sections of the first and second wires. Gaps between the first and second wires are equal to each other between each two wire sections from the input side of the first and second wires.Type: GrantFiled: November 22, 2000Date of Patent: September 24, 2002Assignee: NEC CorporationInventor: Kazuki Asao
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Patent number: 6448833Abstract: A delay circuit using MOS transistors for use of load capacitance which produces a stable delay effect for variations in signal voltage is provided. A gate of a P-type MOS transistor for load capacitance and a gate of an N-type MOS transistor for load capacitance are connected to a signal line. A resistor and CMOS inverters are used to apply a boosted voltage higher than a supply voltage VDD to a source-drain of the P-type MOS transistor for load capacitance and a substrate voltage lower than a ground voltage to a source-drain of the N-type MOS transistor for load capacitance. As a result, a gate voltage range for allowing the MOS transistors for load capacitance to have a capacitance is extended, and a stable delay effect is assured for a widened variation of signal current flowing on the signal line.Type: GrantFiled: March 6, 2001Date of Patent: September 10, 2002Assignee: NEC CorporationInventor: Yukitoshi Hirose
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Patent number: 6434061Abstract: A compensation circuit includes at least one of an n-channel device connected to oppose a high-to-low transition and a p-channel device connected to oppose a low-to high transition. The n-channel and p-channel devices may be diodes, transistors, or transistors connected to function as diodes. The n-channel and p-channel devices may be connected to a large variety of devices and circuits, such as phase locked loops, delay locked loops, clock circuits, or any circuit which requires two balanced paths, one through n-channel devices and one through p-channel devices, to compensate for process variations. Methods for balancing a circuit path and compensating for process variations are also disclosed.Type: GrantFiled: August 31, 2000Date of Patent: August 13, 2002Assignee: Micron Technology, Inc.Inventor: Brian W. Huber
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Patent number: 6388491Abstract: A delay circuit includes a capacitor, a charging/discharging control circuit receptive of an input signal for controlling at least one of the charging and the discharging of the capacitor to set a delay time in accordance with a capacitance value of the capacitor, and a comparing circuit for comparing a voltage at a first terminal of the capacitor with a first reference voltage to produce an output signal which becomes inverted after the delay time when the voltage at the first terminal of the capacitor crosses over the first reference voltage during one of charging and discharging of the capacitor, and comparing a voltage at the first terminal of the capacitor with a second reference and producing an output signal which becomes inverted when the voltage at the first terminal of the capacitor is higher than the second reference voltage so that the delay time is reduced when the first terminal of the capacitor becomes short-circuited to an abnormally high voltage level.Type: GrantFiled: April 26, 1999Date of Patent: May 14, 2002Assignee: Seiko Instruments Inc.Inventors: Koichi Yamasaki, Hiroshi Mukainakano
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Patent number: 6359488Abstract: There is provided a semiconductor integrated circuit including a clock buffer capable of suppressing the increase of its chip size and decreasing its electric power consumption even if the capacity increases or even if the functional operations are varied.Type: GrantFiled: March 9, 2001Date of Patent: March 19, 2002Assignee: Kabushiki Kaisha ToshibaInventor: Takao Nakajima
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Patent number: 6351169Abstract: An internal clock signal generating circuit according to the present invention has a minute delay stage that can change a delay amount minutely and a delay stage that changes its delay amount by a larger amount. The minute delay stage responds to a control signal output from a control circuit and fine adjusts its delay amount. The delay stage includes a plurality of fixed delay circuits that realize a relatively large delay amount, respectively. The fixed delay circuit to be connected to the minute delay stage is selected based on the control of the control unit. Accordingly, internal clock signal generating circuit is applicable to a wide range of frequency, occupying a very small space.Type: GrantFiled: March 22, 1999Date of Patent: February 26, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Shigehiro Kuge
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Patent number: 6320438Abstract: A clock generator has a duty cycle correction circuit that adjusts the duty cycle to 50%. A modulator is an inverter with extra source-limiting transistors in series to the power and ground supplies. A control voltage of about Vcc/2 is applied to the source-limiting transistors, causing them to operate in the linear region with limited current. A slow-slew output from the modulator is buffered by a driver. The driver output is filtered by a linear detector with a series resistor and input capacitor. The detector output is compared to a reference voltage of Vcc/2 by an error amp. The error amp generates the control voltage fed back to the modulator. An output capacitor creates a dominant pole with the error amp to ensure stability. A variable-threshold gate can be added between the driver output and the detector to separately adjust the measurement threshold voltage from the reference voltage to the error amp.Type: GrantFiled: August 17, 2000Date of Patent: November 20, 2001Assignee: Pericom Semiconductor Corp.Inventor: Christopher G. Arcus
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Patent number: 6278310Abstract: The present invention is directed to a transition delay circuit. The transition delay circuit includes a delay circuit which is responsive to an input signal. The transition delay circuit produces an output signal at a common node. The transition delay circuit also includes a first MOS capacitor connected between the input signal and the common node and a second MOS capacitor connected between the input signal and the common node. A method for delaying an input signal to a buffer circuit is also disclosed.Type: GrantFiled: April 25, 2000Date of Patent: August 21, 2001Assignee: Micron Technology, Inc.Inventor: Eric J. Stave
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Patent number: 6262616Abstract: A technique for compensating for supply voltage variations in a delay circuit by utilizing a bias circuit to maintain the delay substantially constant with respect to the supply voltage. The bias circuit generates a bias current having a fixed component and a variable component, in which the variable component varies proportionately to variations in the supply voltage to maintain the delay substantially constant.Type: GrantFiled: October 8, 1999Date of Patent: July 17, 2001Assignee: Cirrus Logic, Inc.Inventors: Vishnu S. Srinivasan, John Pacourek, John James Paulos
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Patent number: 6262618Abstract: A time delay circuit for generating a dead time for a high-side/low-side transistor pair. A four transistor comparator circuit is employed with an input voltage reference transistor and output current reference transistor, and with a single capacitor determining the total time delay between the turn on of one of the output power devices and the turn off of the other. The time delay is closely related to the capacitance value (within 10%); power dissipation is minimized; the circuit is reduced to six transistors, and the time delay (or “dead time”) can be accurately and easily programmed by the user.Type: GrantFiled: December 17, 1999Date of Patent: July 17, 2001Assignee: International Rectifier CorporationInventor: Joseph Maggiolino
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Patent number: 6255878Abstract: A precision delay circuit having two delay chains to provide equal delay periods is described. A rising edge of an input pulse signal is supplied to the first delay chain and the falling edge is supplied to the second delay chain. The resultant output signal maintains the pulse width of the input signal and pulse distortion is minimized. In another aspect, a delay circuit for generating a delayed assertion signal that does not maintain the width of the original input signal pulse and which is substantially immune to noise problems is described. An assertion edge of a resultant pulse is timed by the incoming pulse, but the de-assertion edge is timed by the delayed de-assertion edge of the incoming pulse.Type: GrantFiled: May 7, 1999Date of Patent: July 3, 2001Assignee: LSI Logic CorporationInventors: Coralyn S. Gauvin, William K. Petty, Brian K. Herbert
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Patent number: 6232814Abstract: An input-output (I-O) buffer for an I-O node of an integrated circuit. The buffer includes a group of transistors to pull the node up. A shift register has each of two or more of its storage cells coupled to a gate of each of the transistors to control the impedance of the buffer.Type: GrantFiled: November 10, 1998Date of Patent: May 15, 2001Assignee: Intel CorporationInventor: Kenneth R. Douglas, III
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Patent number: 6222396Abstract: In one embodiment, a multistage output buffer supplies current to a load by successively turning ON output buffer circuits which transition from an OFF state to approximately a saturated state during approximately mutually exclusive periods of time. Thus, the aggregate dI/dt of the contributed by the output buffer drivers is primarily associated with a single output buffer driver. Additionally, the respective output driver transition periods are controlled by delay stage impedance to reduce dI/dt. The consecutive activation of the output buffer drivers may be achieved by using respective delay stages to control activation of associated, respective output buffer drivers. Each delay stage receives a delayed output control signal from a previous delay stage, except for the first delay stage which receives a control input signal from a signal source. Each delay stage also delays activation of its own output control signal with delay circuit elements such as relatively HIGH impedance IGFETs.Type: GrantFiled: August 27, 1999Date of Patent: April 24, 2001Assignee: Legerity, Inc.Inventor: Gregory C. Woodward
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Patent number: RE37124Abstract: A ring oscillator having an odd number of single ended stages, each stage including two transistors connected as a current mirror. The stage provides for low-voltage performance and improved process tolerance characteristics.Type: GrantFiled: June 11, 1998Date of Patent: April 3, 2001Assignee: STMicroelectronics LimitedInventors: Trevor K. Monk, Andrew M. Hall