Abstract: A variable threshold comparator receiving, on an input node, an input signal having a voltage, and providing an output signal on an output node when the voltage of the input signal exceeds a selectable threshold voltage of the comparator. The comparator includes a transistor coupled by way of its source and drain between a power supply and an output node, and having its gate coupled to the input node. Also included are a plurality of pairs of transistors coupled together by a source of a first one of the pair of transistors and drain a drain of a second one of the pair of transistors, and coupled in series between the output node and a ground, a gate of the first one of the transistors coupled to the input node, and a gate of the second one of the transistors coupled to a control signal specific to the second one of the transistors. The threshold voltage of the comparator is selectable by the application of one or more of the control signals to a respective one or more of the second ones of said transistors.

Abstract: The present invention is directed to a transition delay circuit. The transition delay circuit includes a delay circuit which is responsive to an input signal. The transition delay circuit produces an output signal at a common node. The transition delay circuit also includes a first MOS capacitor connected between the input signal and the common node and a second MOS capacitor connected between the input signal and the common node. A method for delaying an input signal to a buffer circuit is also disclosed.

Abstract: A delay circuit which resists noise present in the power supply or ground includes a waveform modification circuit for varying the rise and fall of inputted pulse signals, and a switch for connecting a power supply and an output terminal when the voltage of the modified waveform exceeds the threshold value related to the power supply voltage. The waveform modification circuit includes a voltage control circuit for varying the output voltage of the waveform modification circuit in accordance with changes in the voltage of the power supply. To reshape a waveform, an input signal is compared with the power supply voltage as a reference value, and the input signal and power supply voltage are switched in accordance with the comparison results. The voltage control circuit changes the output of the waveform modification circuit in accordance with the changes in the reference when noise contained in the power supply voltage is applied to the output of the waveform modification circuit.

Abstract: An impedance device has a first conductor and a second conductor, the first and second conductors being positioned in relation to each other so as to provide magnetic coupling between them. The impedance of the impedance device is controlled by receiving, in the first conductor, a first electric signal having a first amplitude and a first phase angle, generating a second electric signal having a second amplitude and a second phase angle, delivering the second electric signal to the second conductor, and controlling the second phase angle.

Abstract: A controlled delay circuit having a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: An apparatus and method for delaying a signal using a variable delay line circuit. A variable delay line circuit includes first and second delay lines, each including a plurality of delay elements. A multiplexer is coupled to respective outputs of the first and second delay lines and selectively couples the output of one of the first or second delay lines to an output of the multiplexer. A control circuit is coupled to the multiplexer and the first and second delay lines, and controls the multiplexer so as to produce a delayed signal at the multiplexer output using one of the first or second delay lines, and changes a delay factor of the other one of the first or second delay lines by varying a resistance and a current of one or more delay elements of the other one of the first or second delay lines.

Abstract: A delay cell for use in binary delay line which includes a delay circuit having N outputs where N.gtoreq.2, each delay circuit coupled to an input through N-1 serially connected unit cells. For each output there are P unit cells having a unit delay of t.sub.P0 and N-1-P unit cells having a unit delay of t.sub.p1. The N outputs are ordered such that each output other than the first is delayed with respect to an immediately preceding output by t.sub.p1 -t.sub.p0, and P goes in succession from N-1 to 0 in unit steps. Each value of P corresponds to only one of the N outputs.

Abstract: A programmable delay line has delay elements that are responsive to at least one of two different calibration signals for varying their drive power characteristics and hence the delay period. Preferably, there are two sets of delay elements, responsive to a respective calibration signal, with one set comprising much fewer delay elements than the other set. The delay elements may be responsive to a digital calibration signal for discrete control, an analog calibration signal for continuous control, or both.

Abstract: According to the present invention, by setting the logic state of one or more delay signals to appropriate values, the resistive value of a plurality of power supply delay elements throughout an integrated circuit having distributed circuit blocks may be modified to produce desired delay times or pulse width adjustments throughout the integrated circuit. Setting delay signals to desired logic states may be accomplished by a variety of means including forcing test pads to a logic level, blowing fuses, or entering into a test mode.

Abstract: A semiconductor device is provided having an input driver and an output receiver connected by a bus line, the bus line including pulse generating and driver circuitry responsive to threshold levels of voltage change so as to perform high speed switching which compensates for the load of the bus line.

Abstract: A delay element including a stack of p-channel transistors connected in series and a stack of n-channel transistors connected in series with the source of the top p-channel transistor connected to a positive voltage and the source of the bottom n-channel transistor connected to ground. The drain of each n-channel transistor is connected to the drain of a corresponding one of the p-channel transistors and all gates are interconnected and serve as the input to the delay element. The output of the delay element can be any one of the drain connections.

Abstract: A device for compensating a signal delay introduced by a second circuit is provided. The second circuit is configured to receive a signal and to output the signal with the first delay if the first signal transitions from a first to a second logic level. The second circuit is configured to output the signal with the second delay if the first signal transitions from the second to the first logic level. The device according to the present invention includes a first circuit that is configured to receive the signal. The first circuit is configured to introduce the first delay, if the signal transitions from a second to a first logic level. The first circuit is configured to introduce the second delay if the signal transitions from the first to the second logic level.

Abstract: A reduced area delay circuit and method are disclosed. The delay circuit uses a constant current source and a constant current drain to charge and discharge a capacitor and thus control the delay time of the delay circuit. The constant current source and drain can be implemented using current mirrors formed by configuring MOSFET transistors in a common source configuration. The delay circuit method includes the steps of receiving an input signal, delaying the input signal by using a constant current source or drain in combination with a capacitor, and then buffering the voltage on the capacitor using two inverters. A programmable delay circuit is also disclosed by adding additional pairs of current mirrors to the delay circuit and selectively enabling the pairs to adjust the delay time.

Abstract: A power applying circuit for an internal logic circuit includes a plurality of basic power applying units coupled to the internal logic circuit in parallel, each of the basic power applying units including a logic gate unit outputting a pulse in response to two input signals having a time interval with respect to each other, and a transmission gate coupled to the logic gate unit and receiving the pulse.

Abstract: A scale of circuit is reduced when a plurality of variable delay circuits are provided with respect to the same signal. A variable delay circuit is constructed such that variable delay circuit elements each comprising a delay circuit element composed of buffer gates each having an identical amount of delay connected in series and a selector e for selecting the input and output of the delay circuit element are connected in series in n-1 stages, wherein the number of the delay elements of the delay circuit element in each variable delay circuit element is 2.sup.i-1 (i: number of stages) in the order from the final stage.

Abstract: This invention describes a delay circuit for integrated circuits that has the capability to delay the rising and falling transitions separately and independent of each other. A signal is fed through an RC network to a Schmitt trigger and then through an inverter to the output of the delay circuit. Two MOS transistors are connected as capacitors and in parallel but in opposing directions between the delay circuit output and the input to the Schmitt trigger to form part of the RC network. The biasing of the two transistors is such that the inversion layer capacitance is active in only one transistor for each signal transition. Thus the falling and rising transition of an input signal can be delayed separately. Changing the gate and channel size in one transistor acting as a capacitor changes the delay in one signal transition. Changing the other gate and channel size changes the delay in the other transition.

Abstract: According to the present invention, clock control logic circuitry of a clocked memory device using precharged data path techniques generates a self-timed pulse. The self-timed pulse is representative of a pulsed path active strobe or a reset strobe of the clocked memory device. The clock control logic circuitry of the present invention is characterized as having at least a first delay timing chain, a second delay timing chain, and means for selectively changing the width of a self-timed pulse generated by the clock control logic circuitry. Selectively changing the width of the self-timed pulse is accomplished by selectively adding the delay of the first delay timing chain to the delay of the second delay timing chain during a special mode of operation of the clocked memory device.

Abstract: The present invention discloses a delay circuit which obtains constant a delay time of delay circuit using an output capacitor by making the resistance of MOS transistor lowest, at the low voltage, middle at the intermediate voltage, and largest at the high voltage, so that the delay time of delay circuit using an output capacitor is kept constant regardless of the change in power source voltage.

Abstract: A skew logic circuit device comprises:two or more inverters which are connected in series with one another between an input line and an output line; first control switching means for switching voltage from a first power voltage source toward an output terminal of every odd inverter; second control switching means for switching voltage from a second power voltage source toward an output terminal of every even inverter; and edge signal generating means for sequentially controlling the operation of the first and second control switching means by the edge signal of a fixed pulse width caused by logically combining the signal from the input line.

Abstract: A delay circuit which employs a Miller effect to delay a signal while driving a subsequent amplifier stage. The Miller effect is dependent upon loading of the circuits on an integrated circuit upon which the delay circuit is implemented, which allows the delay circuit to compensate its delay in relation to other process variation delays present on the integrated circuit. The delay circuit has a first delay stage which delays an input signal and drives a second stage. The delay circuit incorporates a dummy drive stage which adds loading to the first delay stage. In addition, the dummy stage experiences dynamic loading of the delay chain between the first and second stages which allows the coupling of the effect of this dynamic loading back to the first stage through the Miller effect.

Abstract: A clock driver circuit (100) comprises an input (102) for a reference clock signal. A filter (106) is connected to the input to receive the reference signal and output a filtered signal. A complementary FET driver circuit (108) having a cross-over threshold is coupled to the filter to receive the filtered signal and output a conditioned clock signal.

Abstract: The speed gap between rise and fall times of a buffer biased by a power supply having a power supply voltage, the speed gap varying in a first manner with respect to the power supply voltage and in a second manner inverse to the first manner with respect to a bias current supplied to the buffer, is controlled by generating the bias current such that the bias current varies inversely with respect to the power supply voltage, thereby compensating for fluctuations in the power supply voltage and maintaining the speed gap within a predetermined range when the power supply voltage is greater than a power supply voltage threshold level.

Abstract: A cascoded cmos differential delay element is described. The delay element provides a controlled delay useful in forming voltage controlled oscillators or other circuits. The delay element provides high gain enabling it to be useful in multistage delay element circuits. The circuit described includes cascoded complementary differential amplifiers and replicated bias clamps.

Abstract: A pulse generator has an input and two outputs at which to respectively generate pulses in relation to different types of signal edges received at the input of the generator. The generator provides two distinct logic circuit blocks of the sequential type, the blocks being mutually independent for generation of the pulses at the two outputs. In this manner it is possible to easily control the characteristics of the pulses. In addition, if two blocks are connected with appropriate and simple logic networks, it is possible in the generation phase to impose conditions between the pulses at the two outputs in a simple manner and with a certain freedom.

Abstract: A delay line and clock multiplying circuit are disclosed. A plurality of phase shifters impart on a reference clock successively increasing phase shifters, wherein the phase shifters have a plurality of outputs for the successively phase shifted signals. A plurality of first AND gates combine the phase shifted signals in groups to obtain a number of pulses. The pulses are then combined in a plurality of OR gates to obtain a number of pulse signals. A clock signal generator generates, from the pulse signals, mutually time delayed clock signals. A controller is arranged to control the time delay of a delay line circuit. The controller receives at least two mutually phase shifted signals from the outputs of the phase shifters and determines a delay error. The controller then generates a control signal for the delay line circuit, the magnitude of which depends upon the delay error.

Abstract: A variable delay circuit capable of changing delay time includes a latch circuit constituted of a pair of inverters cross-coupled to each other and a transistor serving for reducing voltage difference between two inputs of the latch circuit based on a control signal given thereto. The control signal is also supplied to a pair of transfer gates to control the delay time of the variable delay circuit. The latch circuit has two inputs, between which the transistor is coupled, coupled to the respective transfer gates' ends, at which buffers are respectively coupled to feed output signals. When the control signal reaches a high level, the state of the transistor becomes one of low impedance, so that the voltage difference between the two inputs of the latch circuit is reduced, and so that the state of the latch circuit can be quickly and easily changed with little energy.

Abstract: A pipelined microprocessor is provided including a latch circuit wherein a first transmission gate is electrically coupled in series with a second transmission gate between an output line of a first pipeline stage and an input stage of a subsequent pipeline stage. The latch circuit is controlled by a single clock signal wherein a delay element is employed to simultaneously enable both transmission gates upon an edge of the clock signal. The length of time during which both transmission gates are enabled is determined by an electrical delay associated with the delay element. When both transmission gates are enabled, the input line is electrically coupled to the output line. A keeper circuit at the output of the second transmission gate retains a logical value at the output of the latch after the input line is decoupled from the output line.

Abstract: The method of this invention prevents transient currents at high-frequency disable cycles and disables DC current paths after a minimum delay time, thereby reducing power dissipation. This invention includes a delay circuit functioning to prevent disablement of DC paths where chip-disable times occur at intervals below a minimum duration. The result is a decrease in the number of undesired voltage drops on internal power buses due to transient currents. The method detects external chip-disable pulses that occur before a minimum time duration, then prevents those pulses from powering down internal direct-current paths. At the same time, the output driver high impedance functionality of the chip-disable signal is preserved.

Abstract: A partitioned constant delay logic network 208 has a number of constant delay logic elements. The delay of each logic element is held constant by applying a controlled bias voltage, V.sub.bias. The source of the controlled bias voltage is a phase locked loop 201 which has a voltage controlled oscillator 203 constructed out of an odd plurality of constant delay logic elements.

Abstract: The subject of the invention is an integrated delay circuit (10), including two amplifiers (11a, 11b), furnishing different delays, and having a common input, and a control block (12) connected to two terminals of the two amplifiers, respectively, in order to vary the phase offset between the two amplifiers. This circuit is integrated into a III-V semiconductor, such as gallium arsenide.

Abstract: A BiCMOS digital delay chain includes two signal paths coupled between an input terminal and an output terminal. The first signal path has two CMOS inverters coupled in series, while the second path has one CMOS inverter coupled to an BiNMOS inverter, with the latter being coupled to a BiCMOS pull-down circuit. By providing two signal paths between the input and output terminals of the delayed chain, a zero-static-power low-voltage circuit is obtained in which power-supply sensitivity is higher in one switching direction than in the other. This feature permits operation over a wide range of power supply potentials while minimizing changes in integrated circuit performance.

Abstract: A delay line circuit is provided that precisely delays the incoming referenced clock signal by utilizing two delay cells and a sample-and-hold circuit. The circuit eliminates the need for sensing circuitry at the output to determine if the need to monitor the delay line circuit is operating in an undesirable operation. By eliminating the sensing circuitry the reliability of delay line circuit is significantly increased.

Abstract: A ring oscillator having an odd number of single ended stages, each stage including two transistors connected as a current mirror. The stage provides for low-voltage performance and improved process tolerance characteristics.

Abstract: An analog switch includes first and second thin film field effect transistors having their gate connected in common to a control terminal. Current paths of the first and second thin film field effect transistors are connected in series between an input terminal and a capacitive load. A voltage adjusting capacitive element is connected to a common connection between the current paths of the first and second thin film field effect transistors.

Abstract: Disclosed is a digital phase-locked loop circuit which provides a control signal (332, 334) for a delay circuit (304, 306, 308, 310) within the feedback path of the phase-locked loop. The circuit has a first series of delay circuits (304, 306, 308, 310), which have an incremental control signal input (332, 334), to delay an input clock signal (302) to provide the D input (311) to a D flip flop (312). The input clock signal (302) is also connected to a second series of delay circuits (314, 316, 318, 320, 322). The output of this second series (314, 316, 318, 320, 322) is connected to the clock input (323) of the D flip flop (312). The voltage controlled delay signal input for the second series of delay circuits (314, 316, 318, 320, 322) is supplied by a reference control signal (124, 126). The output of the D flip flop (312) is passed through a resistor-capacitor filtering circuit (324, 325) and fed back to the first series of delay circuits (304, 306, 308, 310) as the incremental control signal.