Plural Outputs Patents (Class 327/295)
  • Patent number: 10258260
    Abstract: A hearing test system comprising an computerized device (100) having an electro-acoustical output transducer (104) and a graphical user interface (102) and further being adapted to estimate a hearing loss of an individual test person. The invention also relates to a non-transitory computer readable medium carrying instructions which, when executed by a computer, cause a hearing loss of an individual test person to be estimated and a method of estimating a hearing loss.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: April 16, 2019
    Assignee: Widex A/S
    Inventors: Francis Kok-Ming Kuk, Petri Mikael Korhonen, Bryan Lee Crose, Eric Christopher Seper, Chi-Chuen Lau
  • Patent number: 10168233
    Abstract: Disclosed here is an apparatus that includes a sensor including a plurality of sense nodes, a plurality of first latch circuits including a plurality of first input nodes and a plurality of first output nodes, respectively, the plurality of first input nodes coupled to the plurality of sense nodes, respectively, a plurality of second latch circuits including a plurality of second input nodes and a plurality of second output nodes, respectively, the plurality of second input nodes coupled to the plurality of first output nodes, respectively, and a selector including a plurality of third input nodes coupled respectively to the plurality of first output nodes, a plurality of fourth input nodes coupled respectively to the plurality of second output nodes and a plurality of third output nodes.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Kiyohiro Furutani
  • Patent number: 10075154
    Abstract: An analog front end circuit of an optical pulse energy digitizer includes a multiphase clock circuit, a demultiplexer configured to demultiplex a current pulse stream into demultiplexed current pulse streams, and integrate-and-dump circuits coupled with the demultiplexer. Each ingrate and dump circuit is configured to convert one of the demultiplexed current pulse streams to provide a demultiplexed voltage pulse stream. The multiphase clock circuit includes latches having outputs coupled to a combination logic circuit. The combination logic circuit is configured to provide clock signals for the integrate-and-dump circuits.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: September 11, 2018
    Assignee: ROCKWELL COLLINS, INC.
    Inventor: Han Chi Hsieh
  • Patent number: 9934342
    Abstract: Embodiments provided herein include a method for a clock gating verification during a register transfer level (RTL) circuit design stage, including: obtaining clock gating information defined in a clock gating (CG) specification according to a clock gating format, wherein the clock gating information describes a target clock gating behavior of at least a first gated clock signal utilized by an integrated circuit design, the CG specification comprises a template structure defining a relationship between an output gated clock and an input clock, based on an enable condition, and a top mapping associating top level signals, including the first gated clock signal, of the integrated circuit design to the template structure; and automatically generating a first clock gating (CG) checker to verify a clock gating behavior, based on an expected output time and an expected gated time during testing of the integrated circuit design.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: April 3, 2018
    Assignee: NXP USA, Inc.
    Inventors: Song Huang, Yifeng Liu, Lei Ji
  • Patent number: 9798352
    Abstract: A circuit for implementing a scan chain in an integrated circuit having a clock domain crossing is described. The circuit comprises a first dual-edge storage circuit configured to receive an input signal at a scan input and to receive a first clock signal in a first clock domain at a clock input; a storage element having a data input configured to receive an output of the first dual-edge storage circuit; a second dual-edge storage circuit configured to receive an output of the storage element at a scan input and to receive a second clock signal in a second clock domain at a clock input; and a pulse generator configured to provide, to a clock input of the storage element, a pulse signal having a pulse width selected to enable the second dual-edge storage element to store the output of the first dual-edge storage element.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: October 24, 2017
    Assignee: XILINX, INC.
    Inventors: Amitava Majumdar, Balakrishna Jayadev
  • Patent number: 9658645
    Abstract: Control circuits for generating output enable signals are disclosed. In one aspect, a control circuit is provided that employs combinatorial logic to generate an output enable signal that meets timing constraints using a standard clock signal, a feedback clock signal based on the standard clock signal, and a single data rate (SDR) data output stream. The control circuit includes a double data rate (DDR) conversion circuit configured to generate a DDR output stream based on a received SDR output stream. The control circuit includes an output enable circuit configured to receive the standard clock signal, feedback clock signal, and DDR output stream, and to generate the output enable signal that is asserted and de-asserted according to the defined timing constraints. The control circuit is configured to generate an accurately timed output enable signal without the need for a fast clock signal in addition to the standard clock signal.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: May 23, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Lior Amarilio, Meysam Azin, Alexander Khazin, Le Wang
  • Patent number: 9614500
    Abstract: An electronic circuit includes a clock control unit having a first input for receiving a first clock signal, a second input for receiving a second clock signal, a first clock output, and a second clock output, a first flip-flop having a first data input, a first clock input connected to the first clock output, and a first output, and a second flip-flop having a second data input, a second clock input connected to the second clock output, and a second data input connected to the first output of the first flip-flop. The clock control unit provides the first clock signal to the first clock input of the first flip-flop through the first clock output and the second clock signal to the clock input of the second flip-flop through the second clock output terminal in a sequential order.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: April 4, 2017
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Jing Zhang, Wei Fang, Jindong Pan
  • Patent number: 9529957
    Abstract: Placing a circuit design may include partitioning circuit elements of the circuit design into circuit element sets and grouping bins of an integrated circuit into bin sets. The bins include circuit elements of the circuit design from an initial placement. Placing a circuit design also may include determining a dependency connectivity metric for the circuit elements and, using a processor, selectively relocating circuit elements concurrently, for a plurality of iterations, using a cost metric for relocating the circuit elements and using an order of processing the circuit elements determined from the bin sets, the circuit element sets, and the dependency connectivity metrics.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: December 27, 2016
    Assignee: XILINX, INC.
    Inventors: Grigor S. Gasparyan, Xiao Dong, Marvin Tom
  • Patent number: 9501089
    Abstract: An integrated circuit package including an induction-coupled clock distribution system is disclosed. An exemplary embodiment of the disclosure includes a transmission module coupled to a main clock line, a clock reception module coupled to the transmission module, the clock reception module including a clock output line, and an electronic circuit coupled to the clock output line of the clock reception module, the electronic circuit including at least one clocked element and configured to operate synchronously with a clocking signal received through the clock output line of the clock reception module. The transmission module may be disposed on the supporting case of the IC package, and the electronic circuit and the clock reception module may be disposed on the semiconductor die of the IC package.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: November 22, 2016
    Assignee: Broadcom Corporation
    Inventors: David Chang, Ajat Hukkoo
  • Patent number: 9438217
    Abstract: A system and method of clocking an integrated circuit (IC) includes determining operating characteristics of the IC. The IC has multiple domains and each domain receives a respective domain clock signal. A skew value is determined for each of the domain clock signals, where each skew value is associated with a respective domain of the IC. The domain clock signals are generated from a reference clock signal and each domain clock signal is skewed from the reference clock according to the respective skew value.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: September 6, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Narayanan Kannan, Rohit Srivastava
  • Patent number: 9436210
    Abstract: Systems, methods, and other embodiments are described that are associated with selective shorting of clock branches. In one embodiment, an apparatus includes a selective shorting device connected between a first clock branch that conducts a slow clock signal having a first frequency and a second clock branch that conducts a fast clock signal having a second frequency that is an integer multiple of the first frequency. The selective shorting device is configured to electrically connect and disconnect the first clock branch and the second clock branch. The selective shorting control mechanism is configured to control the selective shorting device to electrically connect the clock branches during a controlling portion of the slow clock signal.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: September 6, 2016
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Kim Schuttenberg, Franco Ricci
  • Patent number: 9430601
    Abstract: Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: August 30, 2016
    Assignee: SYNOPSYS, INC.
    Inventor: Anand Arunachalam
  • Patent number: 9240791
    Abstract: An integrated circuit includes a plurality of logic tiles, wherein each logic tile includes a plurality of edges and is configurable to connect with adjacent logic tile. Each logic tile includes a plurality of input/output clock paths, wherein each input/output clock path is associated with a different edge of the logic tile. The plurality of input/output clock paths include a plurality of input clock path, each input clock path configurable to receive a tile input clock signal from an adjacent first logic tile, and a plurality of output clock paths, each output clock path configurable to output a tile output clock signal to an adjacent second logic tile. An output clock path includes a u-turn circuit to receive a tile clock signal having a first predetermined skew and provide a tile clock signal having a second predetermined skew.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: January 19, 2016
    Assignee: Flex Logix Technologies, Inc.
    Inventor: Cheng C. Wang
  • Patent number: 9189007
    Abstract: Power supply regulators, integrated circuits including a power supply regulator, and methods of regulating a power supply are provided. In one embodiment, a power supply regulator includes a first self-bias circuit configured to receive a supply voltage from a power supply, a second self-bias circuit coupled to a reference voltage, and a clamping circuit coupled between the first and second self-bias circuits. The clamping circuit includes a NMOS transistor coupled to the first self-bias circuit and a PMOS transistor coupled to the second self-bias circuit. The clamping circuit is further configured to generate an output voltage less than the supply voltage at substantially the same time as when the supply voltage is received from the power supply.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: November 17, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Ting Ko, Jinn-Yeh Chien
  • Patent number: 9178730
    Abstract: A clock distribution module for a digital synchronous system is described. The clock distribution module comprising a first node arranged to comprise a clock signal comprising a propagation delay relative to a reference clock signal, at least one further node arranged to comprise a clock signal comprising a propagation delay relative to the reference clock signal corresponding to that of the first node, and a clock configuration module. The clock configuration module is arranged to receive at least one indication of clock skew between the first node and at least one further node of the clock distribution module, and to selectively couple the first node to the at least one further node based at least partly on the at least one indication of clock skew there between.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: November 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Priel, David Dzebisashvili, Leonid Fleshel
  • Patent number: 9172383
    Abstract: An integrated circuit package including an induction-coupled clock distribution system is disclosed. An exemplary embodiment of the disclosure includes a transmission module coupled to a main clock line, a clock reception module coupled to the transmission module, the clock reception module including a clock output line, and an electronic circuit coupled to the clock output line of the clock reception module, the electronic circuit including at least one clocked element and configured to operate synchronously with a clocking signal received through the clock output line of the clock reception module. The transmission module may be disposed on the supporting case of the IC package, and the electronic circuit and the clock reception module may be disposed on the semiconductor die of the IC package.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: October 27, 2015
    Assignee: Broadcom Corporation
    Inventors: David Chang, Ajat Hukkoo
  • Patent number: 9154188
    Abstract: An embodiment of a RF identification device is formed by a tag and by a reader. The tag is formed by a processing circuit and a first antenna, which has the function both of transmitting and of receiving data. The reader is formed by a control circuit and by a second antenna, which has the function both of transmitting and of receiving data. The processing circuit is formed by a resonance capacitor, a modulator, a rectifier circuit, a charge-pump circuit and a detection circuit. The antenna of the tag and the processing circuit are integrated in a single structure in completely monolithic form. The first antenna has terminals connected to the input of the rectifier circuit, the output of which is connected to the charge-pump circuit. The charge-pump circuit has an output connected to the detection circuit.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: October 6, 2015
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Alessandro Finocchiaro, Giovanni Girlando, Giuseppe Palmisano, Giuseppe Ferla, Alberto Pagani
  • Patent number: 9148155
    Abstract: An integrated circuit (IC) includes multiple circuit modules that have specific clocking requirements, multiple clock sources (e.g., PLLs, duty cycle re-shaper, etc.), and at least one clock input port. The clock sources have specific clock source specifications, and the circuit modules have specific clocking requirements. The clock sources are selected based on an identification of the most common clocking requirements, and then placed at routing distances measured from the input port that are less than corresponding predetermined maximum routing distances such that the clocking requirements of the circuit modules are met. The IC thus generates clock signals internally, rather than externally.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: September 29, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Amit Aggarwal, Himanshu Goel, Ashish Malhotra, Ankit Pal
  • Patent number: 9124256
    Abstract: A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: September 1, 2015
    Inventor: Laurence H. Cooke
  • Patent number: 9041452
    Abstract: A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: May 26, 2015
    Assignee: Silicon Laboratories Inc.
    Inventors: Michael Robert May, David S. Trager
  • Patent number: 9018999
    Abstract: A hardware/PLC logic combination which enables measurement of a plurality of analog voltage points (e.g., multiples of 8 points) on a single high speed PLC input without separate synchronization inputs or outputs. This is accomplished through the use of a multiplexer circuit [clock, binary counter, analog multiplexer, voltage to frequency converter], and a high speed counter function at the PLC. Synchronization between the PLC and circuit is through the detection of a fixed voltage on channel “one” of the circuit, which is set well above the typical range (e.g., 0-10V) of the remaining analog inputs.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: April 28, 2015
    Assignee: M&R Printing Equipment, Inc.
    Inventor: Keith R. Falk
  • Publication number: 20150109029
    Abstract: A method for generating a digital signal of tunable frequency may include generating a periodic first analog signal, determining a sign of a first difference between a value of the first analog signal and a first control value to determine sign flips, wherein the first control value is a variable value, and generating the digital signal of tunable frequency on the basis of the determined sign of the first difference, wherein the digital signal of tunable frequency is generated such that a subset of switches of the signal level are coincident with a respective sign flip of the determined sign of the first difference.
    Type: Application
    Filed: May 11, 2012
    Publication date: April 23, 2015
    Applicant: EUROPEAN SPACE AGENCY
    Inventors: Enrico Lia, Andreas Lauer, Dietmar Koether, Rüdiger Follmann
  • Patent number: 9007132
    Abstract: An oscillation signal generator includes a quadrature voltage-controlled oscillator (QVCO), a phase corrector and a frequency adjusting circuit. The QVCO provides multiple oscillation signals having difference phases. The phase corrector selects one of the oscillation signals as a first oscillation signal and outputs the first oscillation signal from a first output terminal, and selects one of the oscillation signals as a second oscillation signal and outputs the second oscillation signal from a second output terminal. A phase difference between the first and second oscillation signals satisfies a predetermined relationship. The frequency adjusting circuit is coupled to the phase corrector, and generates a quadrature signal and an in-phase signal according to the oscillation signals. The frequency of the oscillation signals is a non-integral multiple of the frequencies of the quadrature and in-phase signals.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: April 14, 2015
    Assignee: MStar Semiconductor, Inc.
    Inventor: Jian-Yu Ding
  • Patent number: 9000823
    Abstract: An integrated circuit includes a clock source tier and at least two clock tree tiers disposed in a vertical stack with the clock source tier. The clock source tier includes a clock circuit, and each of the at least two clock tree tiers includes a clock tree circuit. The clock circuit is disposed in the clock source tier is coupled to the clock tree circuits disposed in the at least two clock tree tiers by at least one inter-layer via.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Mu-Shan Lin
  • Patent number: 8988144
    Abstract: A demodulator including a delay line adapted for receiving an input signal at an input frequency, phase or frequency modulated by symbols with a duration equal to a period of the input signal or very close to that period. The delay line has Nd outputs producing Nd signals at the input frequency but with Nd different delays offset by ?T relative to one another, Nd being an integer number greater than or equal to 1. The demodulator also includes a register of Nd latches each receiving a respective output of the delay line and a clock signal which is the input signal, in order to store the state of the outputs of the delay lines at the end of a period of the clock signal in the register. The content of the register represents a value of an input signal modulation symbol.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: March 24, 2015
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventor: David Lachartre
  • Publication number: 20150070067
    Abstract: An integrated circuit includes a clock source tier and at least two clock tree tiers disposed in a vertical stack with the clock source tier. The clock source tier includes a clock circuit, and each of the at least two clock tree tiers includes a clock tree circuit. The clock circuit is disposed in the clock source tier is coupled to the clock tree circuits disposed in the at least two clock tree tiers by at least one inter-layer via.
    Type: Application
    Filed: September 12, 2013
    Publication date: March 12, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Mu-Shan Lin
  • Patent number: 8963605
    Abstract: Disclosed is a multi-phase clock signal generation circuit including two circuit blocks, each of which includes a cross-coupled structure and two delay units, and the delay units are adjustable. One circuit block (MD1) includes two NMOS transistors, two PMOS transistors, and two delay units, and the other circuit block (MD2) may include two NMOS transistors, two PMOS transistors, and two delay units. The circuit can generate clock signals with respective phases whose relationship is relatively independent of integration process, operating voltage and temperature, thereby allowing guaranteed efficiency for a multi-phase charge pump.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: February 24, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Weiwei Chen, Lan Chen, Shuang Long
  • Patent number: 8963587
    Abstract: Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: February 24, 2015
    Assignee: Apple Inc.
    Inventors: Erik P. Machnicki, Raman S. Thiara, Shane J. Keil, Timothy J. Millet
  • Patent number: 8963603
    Abstract: A clock generation device includes a first delay unit, a frequency divider, an angle delay unit and a first calculating unit. The first delay unit receives an input clock and delays the input clock by a first preset period to generate an input delay clock. The frequency divider divides a frequency of the delay clock to generate a first frequency-divided clock and a second frequency-divided clock. A frequency of each of the first frequency-divided clock and the second frequency-divided clock is a preset multiple of the input delay clock. The angle delay unit delays the first frequency-divided clock by a second preset period to generate a first delay clock. The first calculating unit determines a trigger time of a first edge of a first output clock with reference to voltage levels of the first frequency-divided clock and the first delay clock and determines a falling time of a second edge of the first output clock with reference to voltage levels of the input clock and the first delay clock.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: February 24, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventors: Shih-Hsiun Huang, Shian-Ru Lin
  • Patent number: 8952732
    Abstract: A signal processor includes: a plurality of frequency converters which perform frequency conversion of input signals to output converted signals; and an output section which combines the converted signals output from the plurality of frequency converters and outputs a composite signal, wherein the plurality of frequency converters are formed in a one-chip semiconductor chip, and the plurality of frequency converters perform frequency conversion into converted signals in different frequency bands.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: February 10, 2015
    Assignee: Sony Corporation
    Inventor: Kenichi Kawasaki
  • Patent number: 8947148
    Abstract: In one example, there is disclosed a hybrid analog-digital point-of-load controller (ADPOL) for use in a power supply. The ADPOL is configured to respond to transient current loads. In the presence of moderate current transients, power is clocked by a digital power core, which may be programmatically configured to adjust pulse width in response to the transient. In the presence of larger current transients, control may be passed to an analog transient compensator, which includes high-speed circuitry selecting between a very high-duty-cycle clock and a very low-duty-cycle clock, which will drive the transient back to the digital control domain.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: February 3, 2015
    Assignee: Analog Devices Technology
    Inventor: Kareem Atout
  • Patent number: 8947149
    Abstract: Embodiments of a clock distribution device and a method of clock distribution are described. In one embodiment, a clock distribution device includes a stacked clock driver circuit configured to perform clock signal charge recycling on input clock signals that swing between different voltage ranges and a load circuit. The stacked clock driver circuit includes stacked driver circuits configured to generate output clock signals that swing between the different voltage ranges. The load circuit includes load networks of different semiconductor types. Each of the load networks are configured to be driven by one of the output clock signals. Other embodiments are also described.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: February 3, 2015
    Assignee: NXP B.V.
    Inventors: Ajay Kapoor, Ralf Malzahn, Rinze Ida Mechtildis Peter Meijer, Peter Thueringer
  • Patent number: 8928387
    Abstract: A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: January 6, 2015
    Inventor: Laurence H. Cooke
  • Publication number: 20140368242
    Abstract: Various systems and methods utilizing a digitally controlled oscillator having frequency steps that increase in magnitude as a target output clock frequency increases are described. An integrated circuit in accordance with the disclosure includes a plurality of first transistor units fixedly coupled to an input voltage and a plurality of second transistor units switchably coupled to the first transistor units. An output coupled to the plurality of second transistor units and the plurality of first transistor units conveys an output signal having a frequency dependent on which select ones of the second transistor units are enabled. The plurality of second transistor units include a first switchable transistor unit having a transistor of a first width, a second switchable transistor unit having a transistor of a second width greater than the first width, and a third switchable transistor unit having a transistor of a third width greater than the second width.
    Type: Application
    Filed: June 30, 2013
    Publication date: December 18, 2014
    Inventor: Gregory Alyn Unruh
  • Patent number: 8907711
    Abstract: A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section formed by connecting logic devices in series corresponding to a number of logic devices included in a clock signal path between a clock signal source and the latch circuit data input. The delay circuit also includes a second delay section having a delay time equal to an interconnect delay time corresponding to a wiring length of the clock signal path.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: December 9, 2014
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Masakuni Kawagoe
  • Patent number: 8890584
    Abstract: Disclosed herein is a device that includes: a frequency division circuit that divides a frequency of a first clock signal to generate a second clock signal; a first logic circuit that receives a first chip select signal and the second clock signal to generate a second chip select signal; and a command generation circuit that is activated based on the second chip select signal, and generates a second command signal based on a first command signal.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: November 18, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Chikara Kondo
  • Publication number: 20140333364
    Abstract: A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.
    Type: Application
    Filed: May 10, 2013
    Publication date: November 13, 2014
    Inventor: Laurence H. Cooke
  • Patent number: 8872566
    Abstract: A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section formed by connecting logic devices in series corresponding to a number of logic devices included in a clock signal path between a clock signal source and the latch circuit data input. The delay circuit also includes a second delay section having a delay time equal to an interconnect delay time corresponding to a wiring length of the clock signal path.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: October 28, 2014
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Masakuni Kawagoe
  • Publication number: 20140292391
    Abstract: A semiconductor integrated circuit includes an identification information storage, an intermediate clock generator and an operating clock generator. The identification information storage stores identification information of the semiconductor integrated circuit. The intermediate clock generator generates an intermediate clock having a frequency higher than that of a reference clock using the reference clock input to the semiconductor integrated circuit from the outside of the semiconductor integrated circuit. The operating clock generator generates the operating clock having a frequency higher than that of the reference clock and lower than that of the intermediate clock in synchronization with a timing allotted according to the identification information stored in the identification information storage, using the intermediate clock.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 2, 2014
    Applicant: KYOCERA Document Solutions inc.
    Inventor: Masataka Takemura
  • Publication number: 20140266377
    Abstract: In one example, there is disclosed a hybrid analog-digital point-of-load controller (ADPOL) for use in a power supply. The ADPOL is configured to respond to transient current loads. In the presence of moderate current transients, power is clocked by a digital power core, which may be programmatically configured to adjust pulse width in response to the transient. In the presence of larger current transients, control may be passed to an analog transient compensator, which includes high-speed circuitry selecting between a very high-duty-cycle clock and a very low-duty-cycle clock, which will drive the transient back to the digital control domain.
    Type: Application
    Filed: January 23, 2014
    Publication date: September 18, 2014
    Applicant: ANALOG DEVICES TECHNOLOGY
    Inventor: Kareem Atout
  • Patent number: 8839019
    Abstract: A semiconductor apparatus includes a clock frequency change block configured to output a plurality of internal clocks with different frequencies by dividing a frequency of an external clock in response to a mode register set signal and a setting command to enable the plurality of internal clocks to be outputted, and generate a flag signal to designate the completion of the output, and a command generation block configured to receive a command and generate the setting command in response to the flag signal and the mode register to set signal.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: September 16, 2014
    Assignee: SK Hynix Inc.
    Inventor: Choung Ki Song
  • Publication number: 20140247080
    Abstract: A multi-level clock signal distribution network comprises a plurality of lower network levels comprising at least a first lower network level and a lowermost network level that is connected to one or more lowermost clock signal driving circuits connectable to receive a clock signal; and a topmost network level arranged to distribute the clock signal to a plurality of clocked circuits, and connected to a plurality of topmost clock signal driving circuits connected to receive the clock signal from the first lower network level. The lowermost network level comprises at least one net and each of the plurality of lower network levels except the lowermost network level comprises a plurality of nets and is connected to a corresponding plurality of lower clock signal driving circuits being connected to receive the clock signal from a subjacent one of the plurality of lower network levels, wherein each of the plurality of nets is driven by all nets of the subjacent one.
    Type: Application
    Filed: November 4, 2011
    Publication date: September 4, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Lior Moheban, Avi Elazary, Amir Nave, Noam Sivan
  • Patent number: 8823437
    Abstract: Embodiments of the present invention provide a clock signal generator, and the clock signal generator is applied to a physical layer subsystem supporting data transmission at multiple baud rates. The clock signal generator includes: a source clock signal generator, and two or more processors connected to an output end of the source clock signal generator; where the source clock signal generator outputs multiple source clock signals with the same frequency according to a reference signal of a reference clock in the subsystem; the processors perform frequency dividing processing on the multiple source clock signals through a digital logic circuit according to an oversampling technology, to obtain a synchronous clock signal corresponding to a baud rate of data transmission in the subsystem, so as to implement timing and transceiving functions when data is transmitted at the baud rate.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: September 2, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Wei Cao, Jindi Zhang, Yingyan Shan
  • Patent number: 8823438
    Abstract: A signal transmission circuit 200 transmits input signals IN1 and IN2 each having a different transmission speed in a mutually electrically insulated manner. Signal transmission circuit 200 includes a pulse generation unit 210, transmission units 230 and 235, a latch circuit 250, and an oscillation determination circuit 270. Transmission units 230 and 235 transmit pulse signals PLS_A and PLS_B generated by pulse generation unit 210 in accordance with logical states of input signals IN1 and IN2 to latch circuit 250 and oscillation determination circuit 270 in a mutually electrically insulated manner. Latch circuit 250 restores input signal IN1 in accordance with rising edges of pulse signals PLS_A and PLS_B. Oscillation determination circuit 270 restores input signal IN2 based on oscillation states of pulse signals PLS_A and PLS_B. With such a configuration, a plurality of signals each having a different transmission speed can be transmitted in a mutually electrically insulated manner.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: September 2, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Daiki Yanagishima, Toshiyuki Ishikawa
  • Patent number: 8797082
    Abstract: A system and method for efficiently performing timing characterization of high-speed clocks signals with low-speed input/output pins. An integrated circuit includes a clock generator that generates a high-speed clock signal. A clock characterizer circuit receives the high-speed clock signal. The clock characterizer generates a corresponding low-speed clock signal. The generated low-speed clock signal is output through a low-speed general-purpose input/output (GPIO) pin for measurement. The generated low-speed clock signal is sent to a sequential element for staging. The staging of the generated low-speed clock signal is done with sequential elements that use a reverse polarity of a clock signal than the polarity used by a previous stage. The high-speed clock signal is used for the staging. The output of each stage is sent to a low-speed GPIO pin for measurement.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: August 5, 2014
    Assignee: Apple Inc.
    Inventors: Ravi K. Ramaswami, Geertjan Joordens
  • Patent number: 8754676
    Abstract: A high voltage waveform is generated that is similar to a low voltage input waveform. The high voltage waveform is a series of pulses that are applied directly to the device. An error signal controls the frequency, magnitude, and duration of the pulses. A feedback signal derived from the high voltage waveform is compared with the input waveform to produce the error signal.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 17, 2014
    Assignee: Rogers Corporation
    Inventor: Karl Edward Sprentall
  • Publication number: 20140152366
    Abstract: A circuit generates low-skew true and complement output signals from an input signal using an inverter, true signal generation circuitry, and complement signal generation circuitry. The inverter operates between a high-voltage reference source (VDD) and a low-voltage reference source (VSS) and inverts the input signal to generate a delayed complement input signal. The true signal generation circuitry, which comprises a p-type transistor in series with an n-type transistor, (i) operates between (a) one of VDD and VSS and (b) one of the true input signal and the complement input signal and (ii) generates a true output signal. The complement signal generation circuitry, which also comprises p-type transistor in series with an n-type transistor, (i) operates between (a) one of VDD and VSS and (b) one of the true input signal and the complement input signal and (ii) generates a complement output signal.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Applicant: LSI Corporation
    Inventors: Manish Trivedi, Manish Umedlal Patel
  • Patent number: 8742817
    Abstract: A clock system of an integrated circuit includes first and second transistors forming a switch that is used when switching the clock system between a resonant mode of operation and a non-resonant mode of operation. An inductor forms a resonant circuit with capacitance of the clock system in resonant mode. The switch receives a clock signal and supplies the clock signal to the inductor when the switch is closed and disconnects the inductor from the clock system when the switch is open. First and second high impedance voltage sources supply respective first and second voltages to the switch and a gate voltage of the first transistor transitions with the clock signal around the first voltage and a gate voltage of the second transistor transitions with the clock signal around the second voltage such that near constant overdrive voltages are maintained for the first and second transistors.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: June 3, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Visvesh S. Sathe, Samuel D. Naffziger
  • Patent number: 8736340
    Abstract: Disclosed is a differential clock signal generator which processes a first differential clock signal using a combination of differential and non-differential components to generate a second differential clock signal. Specifically, the first differential clock signal is converted into a single-ended clock signal, which is used either by a finite state machine to generate two single-ended control signals or by a waveform generator to generate a single-ended waveform control signal. In any case, a deskewer, which comprises a pair of single-ended latches and either multiplexer(s) or logic gates, processes the first differential clock signal, the single-ended clock signal, and the control signal(s) in order to output a second differential clock signal that is different from the first differential clock signal in terms of delay and, optionally, frequency, but synchronously linked to it.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventor: David W. Milton
  • Patent number: 8736351
    Abstract: A charge pump includes a first node configured to receive a first voltage and a second node coupled to the first node through a first transistor. The second node is configured to output a voltage having a greater voltage magnitude than the first voltage. A first capacitor is coupled to a third node, and a fourth node is configured to receive a first clock signal. The third node is disposed between a drain of the first transistor and the fourth node. A leaky circuit device is coupled in parallel with the first capacitor for draining charges of a first polarity away from the second node.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tien-Chun Yang, Yvonne Lin, Ming-Chieh Huang