Abstract: Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications.

Abstract: A clock system includes a clock signal generating circuit and a controlling circuit. The clock signal generating circuit is used for generating a primary clock signal and a reference clock signal both derived from an oscillating signal of the clock signal generating circuit. The controlling circuit is coupled to the clock signal generating circuit and used for receiving the primary clock signal under a normal mode and compensating timing information generated from the primary clock signal according to the reference clock signal when the clock system exits a power saving mode. The primary clock signal is de-activated when the clock system enters the power saving mode and is activated when the clock system exits the power saving mode. The clock system can keep a continue clock for system to use when the primary clock signal is gated or power saving mode is entered.

Abstract: A clock system includes a clock signal generating circuit and a controlling circuit. The clock signal generating circuit is used for generating a primary clock signal and a reference clock signal both derived from an oscillating signal of the clock signal generating circuit. The controlling circuit is coupled to the clock signal generating circuit and used for receiving the primary clock signal under a normal mode and compensating timing information generated from the primary clock signal according to the reference clock signal when the clock system exits a power saving mode. The primary clock signal is de-activated when the clock system enters the power saving mode and is activated when the clock system exits the power saving mode. The clock system can keep a continue clock for system to use when the primary clock signal is gated or power saving mode is entered.

Abstract: The present invention discloses a charge pump system with low noise and high output current and voltage, comprising: a four phase clock generator used to generate a first signals group; a serial of delay circuits coupled to said four phase clock generator, wherein each of said delay circuits is coupled to a previous delay circuit relative to each of said delay circuits for delaying a signals group received from said previous delay circuit; a first charge pump circuit coupled to the four phase clock generator and the delay circuits; and an output terminal coupled to the first charge pump circuit; wherein high level of said first signal overlaps two sections of high level of said third signal to generate a first overlapping time and a second overlapping time, and said first overlapping time is not equal to said second overlapping time.

Abstract: Integrated jitter compliant clock signal generation apparatus and methods are provided. Input signals having different frequencies are used to generate respective clock signals having closely spaced frequencies. The input signals might be generated, for example, in adjacent Phase Locked Loops (PLLs) which receive reference clock signals. The reference clock signals, or signals from which the reference clock signals originate, are also closely spaced. The closely spaced reference clock signals are effectively separated for cleanup and then brought back together to provide the closely spaced clock signals. This allows cleanup of the closely spaced reference clock signals to occur at staggered and more widely spaced frequencies. These techniques could also be applied to reference clock signals which are harmonically related and are used to generate harmonically related output clock signals.

Abstract: A system is provided for generating a plurality of different voltage level clock signals. The system comprises an electrical energy storage pack having a plurality of series coupled electrical energy storage cells that provide a plurality of different output voltage level, a reference oscillator that provides a reference clock signal and a plurality of voltage clamps that receive the plurality of different output voltage levels and output the plurality of different voltage level clock signals at respective output nodes. The plurality of voltage clamps are configured to clamp each of a given output node to a respective high-side voltage level in response to pulling up of the given output node toward a respective high output voltage level and to clamp each of the given output node to a respective low-side voltage level in response to pulling down of the output node toward a low output voltage level.

Abstract: Various embodiments of a semiconductor integrated circuit. According to one exemplary embodiment, a semiconductor integrated circuit includes a multi-phase clock generator that is configured to generate a multi-phase internal clock; a first edge combining unit that is configured to generate a first output clock having a first frequency by combining rising edges of clocks included in the internal clock, and transmit the first output clock to a first port; and a second edge combining unit that is configured to generate a second output clock having a second frequency by combining rising edges of clocks included in the internal clock, and transmit the output clock to a second port.

Abstract: A data communication network may, include a first sub-network and a second sub-network. The first sub-network may include two or more two master clocks, and a synchronization system connected to the master clocks. The synchronization system may, for determine a time-base for the master clocks and control the master clocks based on the determined time-base. The first sub-network may include one or more slave synchronization data source for generating slave clock synchronization data derived from time information of the master clocks. The second sub-network may include one or more slave clocks and a slave clock time-base controller connected to the slave synchronization data source. The time-base controller may receive the slave clock synchronization data and control one or more of the one or more slave clocks in accordance with the slave clock synchronization data.

Abstract: A system and method for implementing an IQ generator includes a master latch that generates an I signal in response to a clock input signal, and a slave latch that generates a Q signal in response to an inverted clock input signal. A master selector is configured to provide a communication path from the master latch to the slave latch, and a slave selector is configured to provide a feedback path from the slave latch to the master latch. The foregoing I and Q signals are output directly from the respective master and slave latches without any intervening electronic circuitry.

Abstract: A system is provided for generating a plurality of different voltage level clock signals. The system comprises an electrical energy storage pack having a plurality of series coupled electrical energy storage cells that provide a plurality of different output voltage level, a reference oscillator that provides a reference clock signal and a plurality of voltage clamps that receive the plurality of different output voltage levels and output the plurality of different voltage level clock signals at respective output nodes. The plurality of voltage clamps are configured to clamp each of a given output node to a respective high-side voltage level in response to pulling up of the given output node toward a respective high output voltage level and to clamp each of the given output node to a respective low-side voltage level in response to pulling down of the output node toward a low output voltage level.

Abstract: According to an aspect of the embodiment, a skew detecting unit includes at least one over delay path or racing path for detecting skew. A clock adjusting unit sets a set value of delay based on the skew detected by the skew detecting unit. A clock cell adjusts delay in a first clock according to the set value of the delay, and outputs the result as a second clock.

Abstract: The invention provides display control circuits for Vacuum Fluorescent Displays (VFDs). The display control circuit controls a plurality of display units of the VFD and comprises an image signal generator generating a plurality of image signals, a clock signal generator generating a clock signal, and a plurality of control signal generators. Each control signal generator receives one of the image signals and the clock signal, generates a control signal for one of the display unit, and determines the duty cycle of the control signal according to the received image signal and the clock signal. The brightness of one display unit varies with the duty cycles of the corresponding control signal. The clock signal generator comprises a plurality of flip-flops coupled in series and a plurality of logic gates.

Abstract: Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications.

Abstract: A data communication network may include two or more master clocks, and a synchronization system connected to the master clocks. The synchronization system may determine a time-base for the master clocks. The synchronization system may control the master clocks according to the determined time-base. The data communication network may include one or more slave clocks. The slave clocks may be controlled by a slave clock time-base controller based on time information of a single selected master clock selected from the master clocks.

Abstract: A digital synchronous circuit includes a clock generator for generating a reference clock signal, a plurality of delays for delaying the reference clock signal by predetermined different times, a transition varying buffer for controlling input transitions of the clock signals received from the plurality of the delays, a transition controller for controlling operation of the transition varying buffer, and a plurality of registers driven by the clock signals from the plurality of delays.

Abstract: A charge pumping circuit is provided to regulate the amount of charge to be pumped according to a driving voltage to reduce the loss of power and increase charge pumping efficiency. The charge pumping circuit includes: a driving voltage sensing unit sensing a driving voltage to generate one or more sensing signals for determining the amount of charge to be pumped; a multi-level clock generation unit generating a pair of clock signals each having an amplitude corresponding to a signal value of each of the one or more sensing signals; and a charge pumping unit charging the pair of clock signals to generate a charged voltage, adding the charged voltage to the driving voltage, and outputting the same.

Abstract: A semiconductor device includes: a clock generator generating a first internal clock signal based on an external clock signal; a clock divider generating second and third internal clock signals based on the first internal clock signal and including an edge adjustor adjusting a timing of one of rising and falling edges of the third internal clock signal, an adjustment information holder supplying an edge adjustment signal to the edge adjustor, and a data strobe generator receiving the second and third internal clock signals to generate a first data strobe signal based on the second internal clock signal, and a second data strobe signal with a phase different from that of the first data strobe signal, based on the third internal clock signal. The edge adjustor adjusts the timing of at least one of the rising and falling edges of the third internal clock signal based on the edge adjustment signal.

Abstract: A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signals in accordance with the clock signal. A respective adjustment circuit in the plurality of adjustment circuits is to provide a respective pair of clock signals in the plurality of pairs of clock signals to a respective pair of outputs in the plurality of pairs of outputs. The respective pair of clock signals includes a first clock signal and a second clock signal. The first clock signal is a complement of the second clock signal and duty-cycle and skew errors in the first clock signal and the second clock signal are less than corresponding pre-determined values.

Abstract: A pulse generator that can generate pulses separated by 120 degrees phase on each of three separate phase output leads for use with a 3-phase motor power driver. These output pulses can be of any desired frequency and voltage. In a particular embodiment of the invention, the phase output pulses take a logic level of 0-12 volts (12 volts peak) with an adjustable frequency of around 250 Hz and a duty cycle of around 50%. This combination of parameters is ideal for driving a 3-phase motor in a vehicle application. Any combination of pulse width or duty cycle, output level and frequency is within the scope of the present invention.

Abstract: A voltage generating circuit has: an operational amplifier, first to third voltage generating units, a first resistor and a second resistor. The operational amplifier generates a control signal depending on first and second voltages that are input thereto. The first voltage generating unit generates the first voltage depending on the control signal and outputs the first voltage from a first node. The second voltage generating unit generates the second voltage depending on the control signal and outputs the second voltage from a second node. The third voltage generating unit generates a third voltage as a reference voltage depending on the control signal and outputs the third voltage from a reference voltage output node. The first resistor is connected between the first node and the reference voltage output node. The second resistor connected between the second node and the reference voltage output node.

Abstract: An object of the present invention is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. In an embodiment of the pulse signal output circuit, a transistor has a source terminal or a drain terminal connected to a gate electrode of another transistor having a source terminal or a drain terminal forming an output terminal of the pulse signal output circuit, the channel length of the transistor being longer than the channel length of the other transistor. Thereby, the amount of a leakage current modifying the gate potential of the other transistor can be reduced, and a malfunction of the pulse signal output circuit can be prevented.

Abstract: A semiconductor integrated circuit includes a plurality of areas, each of which generates phase clocks in accordance with an external clock and control signals and performs a predetermined process assigned to each of the phase clocks. The semiconductor integrated circuit includes a control signal distributing unit that adjusts a timing at which the control signal is turned ON or OFF for each of the areas and distributes the adjusted control signals to the plurality of areas so that the plurality of areas do not perform a same process at a same timing.

Abstract: Methods and apparatuses provide a clocked digital device having dynamically adjustable operating characteristics. The digital device comprises a digital clock management (“DCM”) circuit in which the amount of delay between receipt of an active edge of a clock signal at the input of the DCM circuit and appearance of an active edge of another clock signal at the output of the DCM circuit depends on a phase adjustment signal applied to the DCM circuit's phase adjust input. A phase adjustment circuit provides the phase adjustment signal to the DCM circuit's phase adjust input for controlling the amount of the delay between the clock signal at the input of the DCM circuit and the clock signal at the output of the DCM circuit.

Abstract: A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signals in accordance with the clock signal. A respective adjustment circuit in the plurality of adjustment circuits is to provide a respective pair of clock signals in the plurality of pairs of clock signals to a respective pair of outputs in the plurality of pairs of outputs. The respective pair of clock signals includes a first clock signal and a second clock signal. The first clock signal is a complement of the second clock signal and duty-cycle and skew errors in the first clock signal and the second clock signal are less than corresponding pre-determined values.

Abstract: A PWM control system includes a multi-phase PWM controller and at least one single-phase PWM controller. The multi-phase PWM controller is capable of generating a multi-phase PWM signal. The at least one single-phase PWM controller is capable of generating a single-phase PWM signal. A phase difference between the single-phase PWM signal and the multi-phase signal is greater than 0 degree and less than 180 degree.

Abstract: An A/B-phase signal generator wherein an up/down count unit 52C counts up by an up-count command or counts down by a down-count command at fixed intervals, an angle comparison unit 51 compares the count result ACNT of up/down count unit 52C with an input rotation angle ? and generates a count request, which is an up-count request or a down-count request, a count request comparison unit 52B compares a previous count request with a next count request and generates an up-count command or a down-count command only when the previous count request and the next count request are both up-count requests or down-count requests, respectively, and an A/B-phase pulse generator 53 receives a least significant bit and a second least significant bit of up/down count unit 52C and generates and outputs an A-phase pulse signal and a B-phase pulse signal.

Abstract: Methods and systems to generate multiple phases of a clock may include a delay locked loop (DLL) to generate a bias signal to control a delay time through DLL delay elements in response to a first clock, and a plurality of a quadrature slave delay lines (SDLs), each to generate a plurality of successively phase shifted clocks over a quadrant of a corresponding selected phase of a second clock. The SDLs may be biased with the DLL bias signal to control phase differences between the generated clocks. One or more phase interpolators, such as contention based phase interpolators, may be coupled to outputs of each SDL. A frequency of the second clock may be equal to or greater than a frequency of the first clock. The SDLs may be implemented with fewer delay elements than the DLL.

Abstract: Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

Abstract: An integrated circuit including one or more data links. A respective data link includes a precharge circuit, a voltage generator circuit, and a transmitter circuit. The precharge circuit is configured to precharge a data line to a predefined voltage level between transmission of symbols on the data line. The voltage generator circuit is configured to generate one or more transmit voltage levels, wherein a respective transmit voltage level represents a respective symbol to be transmitted on the data line and provide current from a voltage source to a transmitter circuit to drive the data line to a transmit voltage level representing a symbol to be transmitted, wherein the current drawn from the voltage source is independent of previously transmitted symbols. The transmitter circuit is configured to receive the symbol to be transmitted and drive the data line to the transmit voltage level using the current provided by the voltage generator circuit.

Abstract: Embodiments of the invention relate to an integrated circuit comprising at least one functional unit configured to operate at a first clock frequency. The integrated circuit also comprises at least one first interconnect originating from a contact pad and leading to at least one frequency divider configured to receive a clock signal having a second frequency and generate one or more clock signals to operate the functional unit at the first frequency. The integrated circuit further comprises at least one second interconnect coupling an output of the frequency divider and an input of the functional unit, wherein a total length of the second wired interconnect is less than a total length of the first wired interconnects.

Abstract: An integrated circuit includes a first clock island, a second clock island, a clock generator, and a first programmable delay element. The first clock island is configured to receive a first clock signal. The second clock island is configured to receive a second clock signal. The clock generator is configured to provide a generated clock signal and the first and second clock signals are based on the generated clock signal. The first programmable delay element is coupled between the clock generator and the first clock island. The first programmable delay element is configured to receive the generated clock signal and provide the first clock signal. The integrated circuit is configured to account for a clock skew between the first and second clock signals when information is transferred between the first and second clock islands.

Abstract: A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; and a multi-phase clock generating unit to generate a plurality of multi-phase clocks, a phase difference between the adjacent multi-phase clocks being equal to a second phase difference between pulse signals of a pulse signal pair, based on a plurality of unit-phase clock generating units receiving the pulse signal pairs.

Abstract: A semiconductor integrated circuit device includes a target circuit of a low power consumption mode having at least one flip-flop circuit to which a clock signal is supplied in a normal operation mode and in a low power consumption mode, and a logic circuit to which each output of the at least one flip-flop circuit is input, wherein each of the flip-flop circuits includes a selector that selects a normal data signal in the normal operation mode, selects an inverted output of the flip-flop circuit in the low power consumption mode, based on an operation-mode switching signal that designates switching between the normal operation mode and the low power consumption mode, and inputs the selected signal to a data input terminal of the flip-flop circuit.

Abstract: A timing generator reduces operation-dependent power consumption (AC component) and noises generated from a clock distribution circuit itself in distributing a clock, and further reduces a skew attributed to the clock distribution. A clock distribution circuit 20 for distributing the clock to timing generating sections 10-1 to 10-n has a clock main path 21 connected to a main path buffer 24 and a clock return path 26 connected to a return path buffer 27. A load capacity of the main path buffer 24 is equal to that of the return path buffer 27. Biases of the buffers are the same potential and are generated by a delay locked-loop circuit 30. A propagation delay time of the clock distribution circuit is controlled so as to be an integral multiple of a clock period.

Abstract: A clock generator includes a delta sigma modulator, a counter and a first phase lock loop. The delta sigma modulator sequentially generates a plurality of variable parameters according to a predetermined value and a first input clock signal. The counter, which is connected to the delta sigma modulator, is used to generate an output clock signal in accordance with a counting value and a second input clock signal. The counting value is relevant to the variable parameters. The first phase lock loop, which is connected to the output of the counter, is used to generate an objective clock signal in accordance with the output clock signal.

Abstract: Memories, multi-phase clock signal generators, and methods for generating multi-phase duty cycle corrected clock signals are disclosed. For example, one such clock signal generator includes a delay-locked loop having a first multi-tap adjustable delay line configured to delay a reference signal to provide a plurality of clock signals having different phases relative to the reference clock signal. A periodic signal generated by the delay-locked loop is provided to a second multi-tap adjustable delay line as an input clock signal. Clock signals from taps of the second multi-tap adjustable delay line are provided as the multi-phase duty cycle corrected clock signals.

Abstract: A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.

Abstract: A multi-phase signals generator is disclosed. The multi-phase signals generator mentioned above includes a frequency divider and N delay circuits. The frequency divider receives a clock signal and divides a frequency of the clock signal to generate a divided frequency clock signal. The N delay circuits are connected in series. The delay circuit connected in a first stage receives the divided frequency clock signal. The delay circuit connected in an ith stage receives an output of the delay circuit connected in an (i?1)th stage, wherein i is an integer larger than 2. The delay circuits respectively delay a received signal according to the clock signal and generate N delay output signals, wherein N is an integer larger than 3. Moreover, a plurality of times for transmitting the clock signal to all of the delay circuits are the same.

Abstract: A data output clock generating circuit for a semiconductor memory apparatus includes a rising data output clock generating unit configured to combine a rising clock with a rising clock extraction signal generated in response to a rising output enable signal and a falling clock, to generate a rising data output clock; and a falling data output clock generating unit configured to combine the falling clock with a falling clock extraction signal generated in response to a falling output enable signal and the rising clock, to generate a falling data output clock; wherein the rising data output clock generating unit and the falling data output clock generating unit are independently driven in parallel.

Abstract: A data outputting apparatus of a semiconductor integrated circuit if presented for use in standardizing output timing brought about by different electrical output path lengths. The apparatus includes a data clock signal generating section and a data output section. The data clock signal generating section is configured to use an external clock signal in order to generate a plurality of data clock signals in which output timings of the data clock signals vary depending on a data output mode. The data output section is configured to be controlled by the plurality of data clock signals to output inputted data to the outside through a plurality of data input/output pads that have different path lengths.

Abstract: Some of the embodiments of the present invention provide an integrated circuit device including a clock distribution network, the clock distribution network comprising an inner band, an outer band, and a clock distribution tree including a plurality of stages, each stage including a plurality of signal drivers, wherein all signal drivers of at least one stage of the clock distribution tree are placed in an area between the inner band and the outer band. Other embodiments are also described and claimed.

Abstract: Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed.

Abstract: A clock generating circuit generates a high frequency clock having a constant duty and the same period as that of an external clock. A clock generating circuit generates a clock signal (hereinafter “the clock”) used for outputting a data signal to a data pin. The clock generating circuit includes at least a dividing portion and a clock generating portion. A dividing portion divides an internal clock signal (hereinafter “the internal clock”) generated based on an external clock signal (hereinafter “the external clock”) and outputs a plurality of divided clock signals (hereinafter “the divided clocks”). The clock generating portion performs a predetermined logical operations combining the divided clocks to generate the clock having a constant duty and the same period as the external clock.

Abstract: Various embodiments of a semiconductor integrated circuit. According to one exemplary embodiment, a semiconductor integrated circuit includes a multi-phase clock generator that is configured to generate a multi-phase internal clock; a first edge combining unit that is configured to generate a first output clock having a first frequency by combining rising edges of clocks included in the internal clock, and transmit the first output clock to a first port; and a second edge combining unit that is configured to generate a second output clock having a second frequency by combining rising edges of clocks included in the internal clock, and transmit the output clock to a second port.

Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal ?(0) to ?(2i?1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal ?(0) to j(2i?1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal ?(0) to ?(2i?1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

Abstract: A clock generating circuit includes: a phase detector for detecting a phase difference between an input clock and a reference clock to generate a control signal corresponding to the phase difference; a filter for filtering the control signal to generate a filtered control signal; a controllable oscillator for generating a plurality of output clocks according to the filtered control signal, wherein the plurality of output clocks correspond to an oscillating frequency and correspond to a plurality of different phases respectively; a phase selector for selecting an output clock as a feedback clock from the plurality of output clocks according to a phase select signal; and a feedback circuit for generating the input clock according to the feedback clock.

Abstract: Multi-channel pulser driver circuitry for a sub-beam forming transmitter of an ultrasound system in which sub-beam signals are formed by delaying sub-beam pulse pattern data in accordance with sub-beam pulse delay data and multiple clock signals.

Abstract: A central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews.

Abstract: Clock management is implemented using a variety of systems, devices and methods. According to one embodiment a clock transitioning circuit arrangement (104) is implemented for receiving data from a processor system (102) via a data bus (212, 214) and for modifying a state a clock-generation unit (106) having a local memory for controlling a plurality of clock outputs that provide clock signals for use by the processing system (102). The arrangement has a memory circuit (206) for storing the data from the processor system (102) and a control circuit (208) for accessing the data in the memory circuit (206) in response to a request to change a clock signal provided by an output of the plurality of clock outputs and for providing corresponding data to the local memory of the clock generation unit (106).

Abstract: The described embodiments provide a configurable pulse generator circuit. More specifically, the described embodiments include a pulse generator circuit; an inverting difference oscillator (IDO) enabling circuit coupled to the pulse generator circuit; and a disable signal coupled to the IDO enabling circuit. When the disable signal is asserted, the IDO enabling circuit is disabled and the pulse generator circuit is configured as a pulse generator. In contrast, when the disable signal is deasserted, the IDO enabling circuit is enabled and the pulse generator circuit is configured as part of an IDO.