Abstract: A clock splitter circuit for providing a Single Event Upset (SEU) tolerant clock signals to latches in a space-based environment. The splitter circuit includes an event offset delay. The event offset delay receives an undelayed clock signal and generates an undelayed inverted clock, a delayed clock signal and an inverted delayed clock signal. The delayed clock signal and the inverted delayed clock signal are delayed by the known duration of Single Event Effects (SEE) on logic. The delayed and undelayed clock signals are passed to a pair of event blocking filters which block any disturbance in the undelayed and/or undelayed clock signals. The event blocking filters each generate a pair of in-phase inverted output signals. The event blocking filters are designed such that both pairs of outputs may not be low simultaneously.

Abstract: A system for preventing a powered-up sub-unit from driving a powered-off low-impedance load transitions to a NO_CLOCK state and tri-states output drivers of the sub-unit output unless a clock signal is received from a connected sub-unit. While in the NO_CLOCK state, the sub-unit periodically transmits bursts of clock signals to signal the other sub-unit that it is powered up.

Abstract: A clock tree topology distributes a clock signal from a single input terminal 400 to three terminals 421-423 with an equal phase delay. The topology includes four lines 401-404 connected together at a first end 450 with adjacent lines forming right angles. A second end of the line 404 forms the clock signal input terminal 400. A second end of the remaining lines 401-403 are connected to first ends of lines 411-413. Second ends of the lines 411-413 form the terminals 421-423. A right angle is formed between each of the lines 401-403 and the respective one of the lines 411-413 to which it connects.

Abstract: A system and method for actively deskewing synchronous clocks in a VLSI circuit by introducing a controllable delay unit within a local clock buffer within each of a number of circuit zones and applying a controllable delay at each of the local clock buffers in response to a phase comparison of clock signals from one or more adjacent clock zones. The system can be added to any of a number of various clock distribution networks on a VLSI circuit through the introduction of controllable clock zone buffers and localized phase comparators. By adjusting each localized clock buffer delay unit in response to measured clock signal phase differences from adjacent circuit zones, clock skew problems can be minimized across various clock zones on a VLSI circuit.

Abstract: An IC (Integrated Circuit) including internal circuitry to which a multiphase clock is distributed includes 1/n clock, main wiring drivers each including a frequency divider for dividing the frequency of an input clock by n and a drive circuit for delivering the resulting 1/n clock to a corresponding 1/n clock main wiring. Normal clock, main wiring drivers each include a delay for delaying an input clock to thereby output a normal clock and a drive circuit for delivering the normal clock to a corresponding normal clock main wiring. A clock distributing circuit includes clock wirings for distributing a clock input via a clock input circuit and a plurality of repeat buffers for distributing the distributed clock to each of the 1/n clock and normal clock, main wiring drivers. The IC additionally includes a wiring wiring the outputs of the repeat buffers, a wiring wiring the outputs of 1/n clock, main wiring drivers, and wiring wiring the outputs of the normal clock, main wiring drivers.

Abstract: A method and apparatus for clocking an integrated circuit. The apparatus includes an integrated circuit having a clock driver disposed in a first side of a semiconductor substrate, and a clock distribution network coupled to the clock driver and disposed in a second side of the semiconductor substrate to send a clock signal to clock an area of the integrated circuit.

Abstract: A current pulse generator with process-independent and temperature-independent symmetric switching times, includes a differential stage which is adapted to generate a transmission current and a circuit for driving the differential stage which is adapted to generate a control voltage for the differential stage. The generator also includes a circuit for compensating the variations in the values of degeneration resistors of the differential stage, to generate, with the differential stage driving circuit, a current for controlling the differential stage, to keep the switching times of the current pulses of the generator substantially unchanged and symmetrical despite variations in the manufacturing process of the generator and the temperature.

Abstract: An ASIC device and method provide clock signals to load circuits having a balanced clock tree including a master clock line, for example a clock trunk or H-tree, and branched clock lines feeding the clock signals to load circuits and being balanced with respect to the delays and loads in domains of the ASIC device to which the branched clock lines supply the clock signals. The ASIC device and method generate derived clock signals by gating the master clock signal, in which the derived clock signals have a frequency reduced by a factor n>1 (n=2, . . . , N), which is adapted to the need of the load circuits in a particular domain, and route the master clock signal and/or the derived clock signal for a particular domain to the load circuit of said domain.

Abstract: A method of generating and distributing clock signals is described. The method provides synchronous clock signals in as many phases as a designer of a given circuit finds useful. The method acknowledges timing constraints of the controlled system, and adjusts the clock phases appropriately to meet the needs of the local data circuits using the clock signals. The method uses stages of clock signal generators which are coupled to appropriate portions of the datapath and to each other for controlling the datapath and to provide information about clock signal timing to each other. By adding delay elements, the method can also be used to test the design of the given circuit.

Abstract: A two phase clock generation circuit uses a current mirror and a crossbar switch to generate true and complement output clock signals that are relatively insensitive to process, voltage, and temperature variations. The current mirror generates a charging current and a discharging current that have a fixed magnitude ratio. The crossbar switch then alternately couples the charging current and the discharging current to the true and complement outputs of the clock generation circuit to generate the output clock signals. A selection signal generation unit is provided for generating the selection signal(s) required to appropriately control the switch. Because the charging and discharging currents are at fixed magnitudes and the crossbar switch is a balanced structure, the output clock signals remain aligned to a high degree of accuracy over a wide variety of conditions.

Abstract: In a semiconductor integrated circuit device, a clock buffer is arranged at the center of a chip by using a core I/O technique for arranging an input/output buffer at an arbitrary position. A clock is wired such that, with reference to a wire extending to a circuit in a chip which is farthest from the clock buffer and must be synchronously controlled. Wires extending to the other circuits are intentionally bypassed to make wires extending to all the circuits electrically equal to each other in length. Thus, a skew of a clock can be suppressed due to the isometric wiring.

Abstract: The present invention comprises a master global clock distributed in a low-skew manner over a relevant clock domain area coupled with a plurality of locally generated clocks in said clock domain area. The plurality of locally generated clocks are tuned to allow for skew and jitter tolerance. The present invention further comprises embodiments with 3, 4, 5, and 6 locally generated clocks.

Abstract: In an internal clock signal generation circuit, a plurality of internal clock signals of different phases are generated based on an external clock signal. The internal clock signals are synchronized with the external clock signal by a PPL circuit. The plurality of internal clock signals are respectively supplied to a plurality of internal circuit blocks. Since the phases of the generated internal clock signals are different the phases of the internal clock signals arriving at the internal circuit blocks can be matched even if delays of the signals between the internal clock signal generation circuit and the plurality of internal circuit blocks are different. Thus, clock skews between the plurality of internal clock signals can be reduced and the phase of the internal clock signal and the phase of the external clock signal can be synchronized.

Abstract: A delay generation circuit comprising (i) a circuit configured to generate a reference clock signal having a period, (ii) a divide circuit and (iii) an output circuit. The divide circuit may be configured to generate a first divided clock signal and a second divided clock signal in response to said reference clock signal. The output circuit may be configured to generate (i) a first output clock signal and (ii) a second output clock signal in response to (i) the first and second divided clock signals and (ii) the reference clock signal. The second output clock signal may have a delay with respect to the first output clock signal. The delay may be (i) a multiple of or (ii) a fraction of the period of the reference clock signal.

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Abstract: A plurality of intermediate driving devices are included in stages between a clock generator and a bank of synchronous logic devices. The outputs of the intermediate devices in each stage are connected in parallel over a wide linear dimension. The timing delay of each circuit is then subject to a small variation depending on the irregularities associated with the device characteristics used in its construction. The outputs of the intermediate devices in each stage are tied together to restore regularity and uniformity to all clock generation circuit outputs.

Abstract: The present invention relates to an integrated circuit including at least one logic circuit, able to operate at a first operating frequency, and a clock distribution circuit, the clock distribution circuit receiving a first clock signal and providing to the logic circuit a second clock signal, generated from the first clock signal, the frequency of the second clock signal being substantially equal to the first operating frequency. The clock distribution circuit includes a frequency multiplying circuit for generating the second clock signal, so that the frequency of the first clock signal may be lower than the first operating frequency to reduce or minimize the power consumed by the clock distribution circuit.

Abstract: A clock signal generator comprises a clock input CK and N stages where N is greater than three. Each of the stages comprises a transmission gate M3, M4 which passes clock pulses from the clock Input CK in response to a control signal a from the preceding stage. A control signal generating circuit M5, M6, D7, M8 supplies a control signal e to the succeeding stage when the control signal a from the preceding stage and the clock pulse from the transmission gate M3, M4 have ended. The control signal generating circuit M5, M6, D7, M8 ends the control signal e when the succeeding stage produces its control signal F.

Abstract: A dual-phase clock divider circuit provides the ability to generate high speed complementary clocks with low skew. The dual-phase clock divider circuit runs off a single clock input, such as provided by a high speed VCO. This eliminates the effect of clock skew in the highest speed portion of the circuit. The dual-phase clock divider then generates complementary outputs of low skew to be used by other clocked elements.

Abstract: A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equalized in length in the form of a tree structure, and clock lines connecting lower stage clock drivers are made as short as possible.

Abstract: An improved clock generator performs clock multiplication using selectable generation of clock edges. A clock multiplier divides an input clock period into N edges by generating N non-overlapping clock pulses synchronized to the period of the reference clock—these edges are selectably combined to produce an output clock with the desired multiplication and duty cycle. The sequence of non-overlapping pulses is synchronized to the period of the input reference clock, i.e., to the first harmonic of the reference clock. A pulse generator network includes N pulse generators PG1-PGN, with the output of each pulse generator being coupled to the input of the next pulse generator. When triggered, each pulse generator generates a pulse P with a leading edge and a trailing edge, and a pulse width determined by a selectable pulse-width delay signal.

Abstract: A system for generating voltages on an integrated circuit utilizes an overlapping clocking scheme. An oscillator generates the overlapping clock signals, which are coupled through oscillator buffers, to row pumps. In response to the overlapping clock signals, row pumps generate high voltages, typically higher than the VDD voltage of the integrated circuit. These high voltages may be used to program programmable memory cells or interface to logic components of the integrated circuit.

Abstract: In a clock control circuit there are provided a counter for dividing a reference clock signal so as to generate a plurality of divided clock signals and selectors for selectively outputting one of the plurality of divided clock signals and the reference clock signal as an operation clock signal relative to a CPU or as an operation clock signal relative to a peripheral circuit.

Abstract: An integrated circuit which generates a plurality of local clock signals with substantially no phase difference from an internal clock signal and a stable internal clock generating circuit that generates an internal clock having with reduced sensitivity to variations in a manufacturing process, temperature, supply voltage and noise are provided. The local clock signal generating circuit includes a plurality of phase blenders, each which receives the signals at two points on a clock signal line which transmits the internal clock signals, blends the received signals, and generates a local clock signal having a phase intermediate the phases of the signals at the two points. The internal clock signal generating circuit includes a feedback circuit and a delay lock loop (DLL) circuit.

Abstract: A complementary clock generator and a method for generating complementary clocks are disclosed. A complementary clock generator according to the present invention includes a first inverter, a first transmitting switch and a second transmitting switch. The first inverter outputs inverted clock signals by inverting input clock signals. The first transmitting switch has an input terminal, an output terminal, a first control input terminal and a second control input terminal, and connects the input terminal to the output terminal when the input clock signal reaches the first control input terminal and the inverted clock signal from the first inverter reaches the second control input terminal.

Abstract: Integrated circuit devices having synchronized signal generators therein include a first signal generator and a second signal generator. The first signal generator receives a first input signal and a complementary version of the first input signal at true and complementary inputs thereto, respectively, and generates a first output signal having a leading edge in-sync with a leading edge of the first input signal (e.g., clock signal CLK) but delayed relative thereto by a first time interval. The second signal generator receives the first input signal and the complementary version of the first input signal at complementary and true inputs thereto, respectively, and generates a second output signal having a leading edge in-sync with a leading edge of the complementary version of the first input signal but delayed relative thereto by the first time interval. First and second pulse generators are also preferably provided.

Abstract: A semiconductor integrated circuit incorporating therein a clock supply circuit drives a plurality of peripheral circuits using different frequency-divided clocks. In order to avoid enlargement of switching current there is provided a frequency-dividing circuit for dividing external clock supplied from a clock supply terminal, and a plurality of peripheral circuits which are operated by frequency-divided clocks. There is provided a first clock supply circuit which is capable of generating frequency-divided clock with the highest frequency among frequency-divided clocks required by the peripheral circuits, and a plurality of second clock supply circuits for generating frequency-divided clocks from frequency-divided clock of the first clock supply circuit. Wiring to connect the first clock supply circuit to second clock supply circuits becomes short, and the number of wiring is reduced. Therefore it becomes possible to reduce the switching current.

Abstract: A cascaded delay asynchronous clock (CDAC) for operating control logic (16) to process an event signal. The clock includes a flip-flop (15) for receiving the event signal and generating a clock enable signal and a logic gate (14) connected to the flip-flop (15) for receiving the clock enable signal and generating a clock signal. The clock signal is then communicated to the control logic (16) for use in the control process. The CDAC further includes a plurality of cascaded delays (10) connected in series, such that the first cascaded delay (10) is connected to receive as an input the clock signal, and the last delay (10) is further connected to the logic gate (14). The output of each of the plurality of cascaded delays (10) is fed back to the control logic (16) to generate timing signals. In another aspect of the invention, a variable duty cycle asynchronous clock (VDAC) for operating control logic (40) to process an event signal is disclosed.

Abstract: An integrated circuit chip comprises a plurality of clock distribution sub-networks each including a clock input for receiving a clock signal, each of the clock distribution sub-networks having a capacitance, as seen from the clock input, substantially equivalent to others of the clock distribution sub-networks; and a structured clock buffer having a size based on a load of the clock distribution sub-networks, and providing the clock signal to the clock distribution sub-networks.

Abstract: An active digital voltage regulator circuit is a two terminal device that is connected in shunt to first and second power supply input lines. The active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits. Each power supply monitor circuit further includes a differencing, non-overlapped, dual-output amplifier connected to the first and second power supply input lines. The differencing, non-overlapped, dual-output amplifier includes a predriver stage and an output stage, both of which are connected to the first and second power supply input lines.

Abstract: The circuit configuration produces complementary signals. An input signal is routed from an input terminal via a first path, through a pass element, and to a first output terminal. The input signal is also routed on a second path, connected in parallel with the first path, via an inverter, and to a second output terminal. The first and the second output terminal are connected to a first and a second output node, respectively, via a compensation device. The compensation device compensates for the different time delays in the signals on the first and on the second path.

Abstract: A system of the type including a plurality of circuit blocks is provided with an operation timing controller for controlling the operation timing of these circuit blocks by supplying associated operation control signals thereto. The operation timing controller includes a memory for memorizing respective times when a peak current state arises in these circuit blocks, thereby controlling the timing of the operation control signals in accordance with the memorized times when the peak current state arises. As a result, coincident switching noise can be suppressed no matter when the peak current state arises in these circuit blocks.

Abstract: A clock generation circuit comprises a clock wiring having opposed first and second ends, through which a clock is transmitted from the first end to the second end, and a plurality of clock phase adjustment circuits for generating internal clocks in accordance with the clock supplied from the clock wiring. Each of the clock phase adjustment circuits comprises a first-end side terminal and a second-end side terminal which are connected to a first-end side point and a second-end side point of the circuit, respectively, the points being positioned on both sides of a reference point of the clock wiring; a delay line for delaying a clock supplied from one of the terminals and outputting an internal clock; and a delay control circuit for performing feedback control on a delay of the clock in the delay means in accordance with the phase of the clock supplied from the other terminal so that the phase of the internal clock matches the phase of the clock at the reference point of the cock wiring.

Abstract: A method for synchronizing multiple subsystems using one voltage-controlled oscillator. The method includes transmitting a phase and frequency aligned output of a voltage-controlled oscillator to each subsystem within a digital system. A first subsystem of the multiple subsystems generates a first internal clock and outputs a synchronization signal to each of the other subsystems. The synchronization signal has a marker that defines a known point in time of the first internal clock. The other subsystems sample the synchronization signal using the output signal of the voltage controller oscillator to determine a starting indicator that indicates the known point in time of the first internal clock. Upon detection of the marker in the synchronization signal, the other subsystems starts a second internal clock that is synchronized with the first internal clock.

Abstract: A clock distribution system is described for providing synchronous clock signals in as many phases as a designer of a given circuit finds useful. The clock distribution system acknowledges timing constraints of the controlled system, and adjusts the clock phase appropriately to meet the needs of the local data circuits using the clock signals. The clock distribution system includes stages which are coupled to appropriate portions of the datapath and to each other for controlling the datapath and provide information about clock signal timing to each other.

Abstract: A clock generation system generates and distributes sinusoidal signals. Also, the clock lines are configured and shielded in a novel manner so as to provide the same overall propagation characteristics for the clock signals in all the lines, and to minimize the effects of cross-talk and electromagnetic interference.

Abstract: Two complementary clocks that are well matched are produced from a single input clock. A clock buffer includes an alternating series of edge-rate-controlled inverters and level restoring inverters. The output of this series of inverters is compared to the input clock by a race timer. If the output of the series of inverters switches in the opposite direction before the input clock, the edge rates of the series of inverters are slowed down. If the output of the series of inverters switches in the opposite direction after the input clock, the edge rates of the series of inverters are speeded up. The output of the series of inverters eventually approaches the timing of the input clock but complemented. These signals form a pair of complementary clocks with well matched timing.

Abstract: A control block clock distribution network includes a logic circuit, one or more nth-level buffers, and a (n-1)th-level buffer that drives the one or more nth-level buffers. The logic circuit includes a predefined area containing substantially only clocked logic elements. The number of clocked logic elements in the predefined area is constrained to be less than or equal to a predetermined maximum number. The one or more nth-level buffers are located within the predefined area, whereas the (n-1)th-level buffer is located outside of the predefined area. Each nth-level buffer receives the clock signal outputted by the (n-1)th-level buffer and provides a clock signal to a predetermined number of the clocked logic elements within the predefined area Because the predefined area has known dimensions, the length of the clock line from the (n-1)th buffer to the nth-level buffers is known to within a range.

Abstract: A method for positioning/routing a clock circuit for an integrated circuit compensates for phase differences by adjusting secondary amplifiers having adjustable input delays. The method includes the steps of positioning first conductive lines parallel to a first direction evenly spaced with respect to the second direction. The first conductive lines are connected to outputs of the first amplifiers. A balanced tree-like structure provides each of the first amplifiers a clock signal coming from a single source. The method further includes the steps of positioning functional blocks for forming the integrated circuit, and the positioning of second lines parallel to the second direction. Each secondary amplifier is routed to the closest second line. An equivalent electrical diagram corresponding to the path taken by the clock signal between the input of the tree-like structure device and the input of each secondary amplifier is determined.

Abstract: A multiphase clock generating circuit having: a clock generating section for generating N-phase clock signals of number N which have a frequency nearly equal to that of input clock signal and whose phases are sequentially shifted by 360 degrees/N; an input side M-division circuit that divides the frequency of the input clock signal by M, outputting a reset signal to the clock generating section; an output side M-division circuit that is fed with a delayed reset signal that the reset signal output from the clock generating section is accompanied with a predetermined delay, and, synchronized with the delayed reset signal, divides the frequency of output clock signal output from the clock generating section by M; and a controller for comparing the input side M-division clock and the output side M-division clock, and controlling a delay amount of the clock generating section based on the comparison result.

Abstract: On the surface of a semiconductor substrate between a source region and a drain region formed on the semiconductor substrate, an insulating layer, a conductive thin film used as a floating electrode, a ferroelectric thin film and a conductive thin film used as a control electrode are successively formed. Writing or erasing is performed by causing a potential difference between the control electrode and the semiconductor substrate to reverse the polarization of the ferroelectric thin film.

Abstract: A temporally redundant latch for use in integrated circuit (IC) devices redundantly samples data output from logic or other circuitry at multiple time-shifted periods to provide multiple, independent data samples from which a correct data sample can be selected. The latch has three sampling circuits (e.g., D flip-flops or DICE latches) that sample the logic data output at three different and distinct sampling times. The latch also has a sample release circuit coupled to the sampling circuits to select and output a majority of the samples collected by the sampling circuits at a fourth time that again is different and distinct from the three sampling times. The latch affords both spatial parallelism due to the multiple parallel sampling circuits and temporal parallelism resulting from the clocking scheme involving multiple time-spaced clock signals.

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Abstract: A timing circuit that utilizes the delay inherent in a clock tree to achieve a desired timing relationship between control or clock signals. The timing circuit is particularly applicable to high speed environments and to asynchronous logic, though it is also applicable to lower speed environments and synchronous logic. A method producing the desired control or clock signals is also disclosed.

Abstract: A synchronous memory device and system are described which communicates bi-directional data via a bus and data clock. To capture data from the bus, a memory device latch circuit is described which operates in response to internally generated clock signals. A pulse generator circuit is described which produces these internal clock signals, and insures accurate latching of data by minimizing signal skew between the internal clock signals to avoid wasting valuable timing. The pulse generator circuit has at least two propagation paths that are symmetrical and operate in response to clock signals which are 90 degrees out-of-phase. A second pulse generator circuit is described minimizes skew by having symmetrical clock paths and also corrects duty cycle error present on the data clock. This second circuit uses three clock signals which have relative phases of 0, 90 and 180 degrees.

Abstract: A clock distribution system in a reliable electronic system includes a predetermined number of clock signal load circuits, each having a clock signal input terminal. A first clock signal generator has the same predetermined number of clock signal output terminals coupled to the clock signal input terminals of the clock signal load circuits. A second clock signal generator also has the same predetermined number of clock signal output terminals which are also coupled to the clock signal input terminals of the clock signal load circuits.

Abstract: An integrated circuit chip having improved on-chip circuitry including a phase-locked-loop for providing accurately timed signal having different durations and differently occurring timing edges.

Abstract: A three-phase clock signal generation circuit for a source driver of TFT-LCDs. A clock signal generation circuit for LCD driver includes: a divider dividing an external main clock signal by two and generating a division clock signal; a three-phase clock signal generator receiving the division clock signal from the divider and sequentially generating first to third-phase clock signals; and a sampling mode selector receiving the first to third-phase clock signals and in response to an external mode selection signal, sequentially outputting the first to third-phase clock signals as three-phase clock signals or simultaneously outputting one of the first to third-phase clock signals as the three-phase clock signals. The three phase clock signal generator comprises first, second and third phase clock signal generators sequentially generating first, second and third clock signals with the division clock signal, respectively.

Abstract: A clock circuit is used in a semiconductor device having a control block and a macroblock in order to provide synchronous clocks. The clock circuit contains a clock source for generating the clocks; a clock tree, coupled between the clock source and the control block and the macroblock, for relaying the clocks to the control block and the macrobock; and programmable delays coupled between the clock source and the clock tree and between the clock tree and the control block and the macroblock in order to reduce overall clock skew.

Abstract: An electronic circuit comprises clocked functional circuits which receive a clock signal via a clock switch. The clock switch contains an enabled non-inverting driver which switches a connection between a power supply input and a clock output on and off under control of a clock signal only when the clock switch is enabled by an enable signal. The clock switch also contains a transmission switch coupled between a clock input and the clock output. The transmission switch is controlled from the enable input and makes a conductive connection between the clock input and the clock output only when the clock switch is enabled by the enable signal. As a result, transitions in the clock signal reach the functional circuits with less delay and power take-up needed to drive the clock signal is distributed so that there is less supply bounce.